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2022-07-17mb/amd/*/irq_tables.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ifc915e2825724fdaac67d259e1af2079893492a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17mb/amd/persimmon/mainboard.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I490a7f0c9cb32ca1ea246c14b72852814553214f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17commonlib: compiler.h: Improve wording in commentPaul Menzel
It probably was supposed to be *making these names conistent …*, but short that a little, and add a missing article. Change-Id: If88ff6d7b0a61aa83d5822b5e1c0b5b4c9d3bb3c Fixes: ac136250b26d ("commonlib: Substitude macro "__unused" in compiler.h") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65884 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-17nb/intel/sandybridge/raminit_mrc.c: Use semicolon instead of commaElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15d7e2f30b054d14009761006a2f89f45e001118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17cpu: Get rid of unnecessary blank line {before,after} barceElyes HAOUAS
Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17src/drivers/intel/i210: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Id33ef66e7388df2173ee8888265ed4379f05a93e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17security/intel/txt/common.c: Remove unuseful "else" after "return"Elyes HAOUAS
"else" is unuseful after a "break" or "return". Change-Id: I7273b9af46a2310c9981ffd20afe2c8c7e061479 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60910 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17drivers: Get rid of unnecessary blank lines {before,after} braceElyes HAOUAS
Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17include/device/device.h: Remove unneeded blank line after '{'Elyes HAOUAS
Change-Id: I3e439a293c6b4a806cae7c6a56d28e61f7e57044 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61555 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-16include/acpi: Add macros & definitions for resources types and flagsEran Mitrani
These enums & macros will be used to report resources with acpigen_* functions (Currently those resources are reported in northbridge.asl, but follow-up CLs will remove this file and add the need acpigen code). BUG=b:148759816 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I5b95c9b8370db63537eb48b640ad8f0e750efd69 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16mb/system76: Correct HID names for touchpad devicesTim Crawford
Use correct HID names instead of the CID names for the touchpad devices. Drop the now unneeded UID for the gaze15 TP devices. Tested on a gaze15 with a Synaptics device. Windows does not crash on boot and the touchpad is still detected as an I2C HID device. Change-Id: I5b6ab1a23ce667754d0c5757062385a721c5113f Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16mb/google/brya/var/osiris: Add wifi sar tableDavid Wu
1. Add wifi sar table for osiris 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:234951991 TEST=build FW and checked SAR table can load by WiFi driver. Cq-Depend: chrome-internal:4871098 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-07-16mb/system76/oryp5: Configure dGPU GPIOs in bootblockTim Crawford
Configure the dGPU power and reset pins in bootblock instead of ramstage. This fixes a conflict with our downstream driver, which configures these pins to enable dGPU power in romstage. Behavior remains unchanged without the driver as the dGPU is left powered off. Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16drivers/intel/dptf: Correct UID for TBAT deviceVarshit B Pandya
As per Intel Dynamic Tuning Spec revision 1.3.13, section 14.1.2 TBAT _UID should match the _UID implemented for battery device ACPI object for OS _UID for TBAT is currently set to "TBAT" but should be 1. Battery device is define at src/ec/google/chromeec/acpi/battery.asl Setting _UID to 1 because right now ChromeOS is the only user of DPTF driver TEST: Build and boot brya0 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1e4474e59cf01f937fbd51e5b674a609f0c47625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-16mb/system76/oryp5: Reset HDA before configuringTim Crawford
The oryp5 has several issues with audio output after a reboot: - The device is not in GNOME sound settings - The device is in GNOME sound settings, but there is no audio output - The speaker output is significantly louder than normal Reset the audio codec to resolve these issues. Tested on Pop!_OS 22.04 with Linux 5.17.15. Change-Id: I42f642820bba82142ff370930f0a25e9d1025588 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config optionFred Reitberger
The APOB in sabrina is larger than in cezanne/picasso and no longer fits in the previously allocated 64K space for it. Other symbols are placed immediately after the APOB region and end up corrupting the APOB data on sabrina. Add a Kconfig option to specify the APOB size in DRAM to reserve enough memory and increase the size for sabrina to 128K TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN. Build chausie and verify symbols do not overlap _apob region BUG=b:224056176 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-16ec/system76/ec: Provide charging thresholds by defaultTim Crawford
Battery charging thresholds are a firmware implementation and not dependent on any hardware. It is expected that all boards using System76 EC firmware will select this option, so enable it by default. Leave it disabled on clevo/cml-u, which didn't have it selected. Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16mb/google/brya/var/brya: fix comment for I2C connectionsEran Mitrani
For brya, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-16driver/wifi: Remove unused function wifi_emit_dsmVarshit B Pandya
As part of this CL https://review.coreboot.org/c/coreboot/+/61020 this function was decoupled and support for new DSM was added. This function is no longer used so remove it. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Iad9dca8e50bad87178dfcc1951276703721d5f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65850 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16soc/amd/picasso: Add MP2 I2C0 and I2C1 controller ACPI devicesRitul Guru
This change is to allow AMD MP2 I2C OS driver to access I2C0/1 devices when MP2 firmware is loaded. Change-Id: Iaf25eb4dcf949e4b512ec0e86dbe5ccbc91c3d24 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65673 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-15soc/intel/xeon_sp: Make gsi_bases platform independentChristian Walter
This commit makes gsi_bases platform independent. It introduces two new Kconfigs which set if there are IIO APICs on other devices than the PCH or not, and where they do start. Change-Id: I40db4a8fd90572757687f35bbd8eebd7229fc75a Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65531 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-15soc/intel/cannonlake: Update VR config for Coffee LakeChristian Walter
This is based on the following Intel documents: * 570805 * 570806 * 572062 * 571264 Change-Id: I199415902d26fa5341ef3212a9169836ea4df74a Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-15mb/google/nissa/var/pujjo: Remove unsupport HDA device settingStanley Wu
Pujjo only support RTL1019 amp device, remove MX98360A device setting BUG=b:238716919 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-15mb/google/brya/var/agah: Disable ASPM for dGPUTim Wawrzynczak
Since ASPM is not verified as fully functional yet, and the board is still in development, this patch disables ASPM for the dGPU. BUG=b:236676400 TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-07-15util/xcompile/xcompile: Define GCOV_${TARCH}Yu-Ping Wu
When payloads analyze the coverage using gcov (or lcov), the gcov version must match the CC version. Otherwise gcov would fail to parse the .gcno files. Therefore, define GCOV_${TARCH} in xcompile, so that payloads don't need to do tedious string manipulations to find the right gcov path. Change-Id: If2fc329810c463a3d2c56deaf4e4a3fc3c0a3ed9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-14mb/google/nissa/var/joxer: Update Joxer config to latest schematicMark Hsieh
init overridetree.cb based on the latest schematic. BUG=b:237628218 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-14soc/intel/alderlake: Support PCIe hardware compliance test modeSridahr Siricilla
The validation process verifies that hardware components comply with the standard hardware specifications. For instance, PCI express implementation must comply with the hardware PCIe specification requirements: Electrical, Configuration, Link Protocol and Transaction Protocol. To perform these tests the hardware must be configured in a particular state: some feature related to power management need to be turned off, hot plug should be enabled... This patch sets the appropriate FSP Updateable Product Data flags to get the hardware in the proper configuration: - Enable PCIe hotplug on all ports - Set clock sources to run free - Set the FSP compliance test mode flag BUG=b:235863379 TEST=Compilation with and without the flag Verify code path with instrumentation Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14soc/intel/common: Introduce SOC_INTEL_COMPLIANCE_TEST_MODEJeremy Compostella
This config can be used to make coreboot configure the hardware to meet compliance tests requirements. SoCs which support compliance testing features should set the SOC_INTEL_SUPPORTS_COMPLIANCE_TEST_MODE flag. BUG=b:235863379 TEST=Successful compilation Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Iec760ae89e2b892ef45e6750e823ab5a8609d0fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14mb/google/volteer/eldrid:add new generic DDR4 SPDs for EldridJohnny Li
Update DDR4 SPDs to Eldrid to include the following: DRAM Part Name ID to assign H5AG36EXNDX019 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019Johnny Li
Hynix H5AG36EXNDX019 is used by the volteer variant Eldrid. Add it to the DDR4 parts list and regenerate the SPDs using spd_gen. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I3383dfa4e87571d920144d204270cdf646a19abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans
This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14lib/program_loaders.c: Mark run_ramstage with __noreturnArthur Heymans
This allows the compiler to optimize out code called after run_ramstage. Also remove some die() statements in soc code as run_ramstage already has a die_with_postcode statement. Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14mb/intel/adlrvp: remove I2S2 GPIO settingsCliff Huang
It turns out that there is no device connected to I2S2. This patch clarifies the GPIO settings device association and remove unnecessary configuration. GPP_A8 -> default: GP-in ; set to NF1: SRCCLKREQ7# GPP_A9 -> default: NF1: ESPI_CLK GPP_A10 -> default: NF1: ESPI_RESET# BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I7a575f495d841fe0bf6fd86a84caeee064f6904b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-07-14mb/system76: TGL-U: Disable AER for CPU PCIe RPTim Crawford
Disable PCIe Advanced Error Reporting on the CPU root port to prevent some SSDs from timing out on S0ix suspend. AER results in the drive not being able to switch from D3 back to D0. nvme 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible) Known to affect at least the following SSD models: - ADATA XPG SX8200 Pro - Samsung 970 EVO Plus (FW version: 2B7QCXE7) Change-Id: I79da6b08ef1949f3bf1c6111aaa7e658bd29c0e2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64080 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14sb/intel/ibexpeak: Perform const correctnessBill XIE
me_bios_path_values[] in me.c should not be mutable. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I56412ff0883e1d37027b989c7ac1bd83e93661f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14tests: Adjust the order of header files to includeBill XIE
Consistent with real build process, it retains more potential to detect the build environment. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I46f2fe04bf1b8c1ca6476f05555114fa1ef2a96e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65728 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14commonlib: Substitude macro "__unused" in compiler.hBill XIE
Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14mb/google/brya/var/ghost4adl: Add EC_IN_RW_ODEric Lai
Follow latest schematic to add EC_IN_RW_OD. BUG=b:238786599 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14mb/google/brya/var/ghost4adl: Add SSD power sequence and remove weakEric Lai
Add SSD power sequence and remove the redundant weak. BUG=b:238786597 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0c1ce311d54fb92b27b17f50beda813fe66ad118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14mb/google/brya/var/ghost4adl: Add module MT62F1G32D2DS-026 WT-BJack Rosenthal
Add module MT62F1G32D2DS-026 WT:B and assign RAM code. BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I811e1bbb985efe4198928f30ff6396a5b4368856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65796 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14spd/lp5: Add support for MT62F1G32D2DS-026 WT:BJack Rosenthal
Datasheet is available in the bug. BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Iadd4bf07d38dbd2e1f47df5024282b04dec3c805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65795 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14util/spd_tools: Add support for 7500 MT/s lp5 modulesJack Rosenthal
spd_tools does not support LP5x modules yet, and the easiest way to do this is to add support for 7500 MT/s in lp5.go (reference the comments on CB:65063). BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=With follow-on CL, run: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14northbridge/intel/i945: Fix GCC optimizing out cache preload jumpPetr Cvek
Clock config setup must be run from cache. Original code used "goto" to prefetch the code required to update the VCO (by jumping after the code and back before). The GCC since at least 12.1.0 and clang since at least 13.0.1 will elimitate these jumps. Use inline assembler to force the original code flow. TEST=Verified assembly code is the same as generated by GCC 12.1.0 and boot tested on Kontron 986LCD-M. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I67c2072b5983a5bd845631af136ae5a003c7ea3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-14soc/intel/broadwell: Drop vboot supportYu-Ping Wu
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS, and replace it with VBOOT_VBNV_FLASH [1]. Since SOC_INTEL_BROADWELL doesn't support flash writes in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES), drop vboot as well as ChromeOS support for all broadwell boards, including auron, jecht and wtm2. [1] https://issuetracker.google.com/issues/235293589 BUG=b:235293589 TEST=./util/abuild/abuild -t GOOGLE_GUADO -a TEST=./util/abuild/abuild -t GOOGLE_BUDDY -a Change-Id: I002ab0f5f281c098afba16ada3621f1539c66d6b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14util/spd_tools: Add Intel Meteor Lake (MTL) platformSubrata Banik
This patch add support for MTL platform to the `spd_tools`. This would be useful to create dynamic SPD for rex variants. BUG=b:224325352 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-14soc/amd/*: Move apm call out of MP init codeArthur Heymans
This makes it easier to have common code for MP init on AMD systems. Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14soc/amd/fsp: Cache smm_region() resultsArthur Heymans
This avoids searching the HOB output multiple times when calling smm_region(). Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14configs: Update prodrive hermesPatrick Rudolph
Enable resizable BAR support and allow up to 64GiB BARs. Change-Id: If484f474aed82bf7637926c29c1d8c2907f2a161 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-14mb/google/brya/var/volmar: I2C timing fine tuneRen Kuo
Configure the I2C bus timing for all enabled I2C buses. BUG=b:237751906 TEST=Verify the build for volmar board and measure the freq is under 400KHz Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Iffa128146f5d8bec6dd3d5c2d1e7efd96895dc6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65604 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14mb/google/brya/crota: Enable MAC address passthru supportFranklin Lin
Enable the support for providing a MAC address for a dock to use based on the VPD values set in the platform. BUG=b:235045188 TEST=tested on Brya by setting VPD values and observing the string returned by the AMAC() method: > vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB" > echo 1 > /sys/module/acpi/parameters/aml_debug_output [acpi.aml_debug_output=1] ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB" ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB" ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#" Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com> Change-Id: I61b2a5e18bc17abeea0846f17e9be343e852c2b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65603 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14Remove executable flag from source codes and text filesPetr Cvek
Markdown, definition file and sconfig source codes don't need to be executables. This patch fixes that. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-14Makefile.inc: objcopy extracts a wrong section of cbfs_master_headerPetr Cvek
Commit 75226bb879837 ("Makefile.inc: Generate master header and pointer as C structs") may cause objcopy to copy a wrong section of object file resulting in miscompiled image with missing CBFS master header. This makes the usage of secondary payloads impossible. For example a wrong section for CONFIG_ANY_TOOLCHAIN + objcopy 2.38-slack151 will copy ".note.gnu.property". This patch constraints the sections to .data and .bss only. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I1b9a73ece7067c9c5100cb294775078f838e263b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-14mb/google/nissa/var/pujjo: Add WWAN power off sequenceStanley Wu
pujjo support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:238281124 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I53cd45c8030855c267d870d68d009c454350621e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-14mb/google/rex: Program EC ranges (host cmd and memory map)Subrata Banik
This patch adds chip config entries for EC host cmd and memory map ranges. BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I84a3b128a05c013d659e490a01198955ef383f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add chip config for USB devicesSubrata Banik
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | NC | NC | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | NC | NC | +-------------+----------------+------------+ | 4 | Type-C | NA | +-------------+----------------+------------+ | 5 | WWAN | NA | +-------------+----------------+------------+ | 6 | Camera | NA | +-------------+----------------+------------+ | 7 | NC | NC | +-------------+----------------+------------+ | 8 | DCI | NA | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | DCI | NA | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 1 | NA | +------+-------------------+------------+ BUG=b:224325352 TEST=Able to build Google/Rex and boot to emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iecab1318f683e3b53441cafe909bcfd978ee126b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-07-14mb/google/rex: Add chip config for gspi devicesSubrata Banik
+-----------+-------------+------------------+ | INTERFACE | PCI (B:D:F) | DEVICE | +-----------+-------------+------------------+ | GSPI-0 | 0:0x1e:2 | NA | +-----------+-------------+------------------+ | GSPI-1 | 0:0x1e:3 | Finger Print MCU | +-----------+-------------+------------------+ | GSPI-2 | 0:0x12:6 | NA | +-----------+-------------+------------------+ BUG=b:224325352 TEST=Able to build Google/Rex and boot to emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4b20e342cbca60821f82c07f72328cf63c0e5404 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14soc/intel/meteorlake: Add entry for GSPI2 deviceSubrata Banik
This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb. Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value to include GSPI2 as well. BUG=b:224325352 TEST=Able to build and boot Google/Rex platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add chip config for UART devicesSubrata Banik
This patch ensures LPSS UART 0 is used for the AP serial console as per Rex Proto 0 schematics dated 07/05. +-----------+-------------+-------------+ | INTERFACE | PCI (B:D:F) | DEVICE | +-----------+-------------+-------------+ | UART-0 | 0:0x1e:0 | For AP UART | +-----------+-------------+-------------+ | UART-1 | 0:0x1e:1 | NA | +-----------+-------------+-------------+ | UART-2 | 0:0x19:2 | NA | +-----------+-------------+-------------+ BUG=b:224325352 TEST=Able to get AP UART over LPSS UART0 using emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add chip config for I2C devicesSubrata Banik
+-----------+--------------------+-------------+--------+ | INTERFACE | PCI Number (B:D:F) | DEVICE | Speed | +-----------+--------------------+-------------+--------+ | LPSS I2C0 | 0:0x15:0 | WFC | 400KHz | | | +-------------+--------+ | | | AUDIO_DB | 400KHz | +-----------+--------------------+-------------+--------+ | LPSS I2C1 | 0:0x15:1 | Touch Panel | 400KHz | +-----------+--------------------+-------------+--------+ | LPSS I2C2 | 0:0x15:2 | NC | NC | +-----------+--------------------+-------------+--------+ | LPSS I2C3 | 0:0x15:3 | Touch Pad | 400KHz | +-----------+--------------------+-------------+--------+ | LPSS I2C4 | 0:0x19:0 | TPM | 400KHz | +-----------+--------------------+-------------+--------+ | LPSS I2C5 | 0:0x19:1 | UFC | 400KHz | | | +-------------+--------+ | | | SAR1 | 400KHz | | | +-------------+--------+ | | | SAR2 | 400KHz | | | +-------------+--------+ | | | HPS | 400KHz | +-----------+--------------------+-------------+--------+ BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76a28f175372542d441c787deb2a096382658ace Reviewed-on: https://review.coreboot.org/c/coreboot/+/65762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-07-14mb/google/rex: Drop redundant `cpu_cluster` entrySubrata Banik
This patch drops redundant cpu_cluster definition from mainboard specific devicetree.cb as soc chip config (chipset.cb) already has the required entry. BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iad42985ead7269eaa739c31bede5948c2e25c67c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add overridetree.cb for `rex0` variantSubrata Banik
This patch adds initial PCI device entries into the override devicetree. BUG=b:224325352 TEST=Able to build Google/Rex and verified on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I16326747df46769f93813ce322ed8045449ffa85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add initial devicetree.cb for `rex` baseboardSubrata Banik
This patch adds initial PCI device entries into the baseboard devicetree.cb. BUG=b:224325352 TEST=Able to build Google/Rex and verified on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I944b03a6b3c9c592c09984dde483c855f1a2cd32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14Documentation: Add mdl style fileMartin Roth
This adds a style file for the markdown linter mdl. The tool can be found on archive.org at the URL: https://web.archive.org/web/20220407032312/https://github.com/markdownlint/markdownlint This does 2 things: - Sets that line length limit to 72 characters as requested in the docs about writing the documentation. - Excludes several rules that were added for a particular markdown parser. My opinion is that these rules make the text versions of the markdown harder to read. To use this style file, run: $ mdl -s Documentation/.mdl_style.rb Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I98289492ae3e920d440f0e5c308a3590fb89d9fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/63805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-13mb/google/brya/acpi: Fix GPIO assignment for GPIO_GPU_NVVDD_ENTim Wawrzynczak
GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in power.asl, but a double check of the schematic shows that the actual pad is GPP_A17, so this patch fixes that. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Remove NV_33 power rail from GC6 entry/exit sequencesTim Wawrzynczak
I misread my notes when writing the code for the GC6I/GC6O Methods, and accidentally included NV_33 in the GC6 sequence, which is incorrect (confirmed in the Hardware Design Guide). This patch removes the code that brings NV_33 up and down during the GC6 sequences. BUG=b:236676400 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565 Reviewed-by: Robert Zieba <robertzieba@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya: Implement shutdown function for dGPUTim Wawrzynczak
Variants of brya that have a dGPU also need to perform a special shutdown sequence in the _PTS ACPI Method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib760fa65e6e021c0949187f13f038d3e952e5910 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-13mb/google/brya/acpi/peg: Fix Power Resource _ON and _OFFTim Wawrzynczak
The _ON and _OFF methods for the root port's power resource were calling the _ON and _OFF in the PEGP namespace, which was the incorrect method, it should have been NPON/NPOF, so this patch updates that. BUG=b:236676400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3653996329473f133e3f0d53306882dc3213b6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13ec/google/chromec: Update ACPI handlers for GPUTim Wawrzynczak
There is a new field in EC EMEM for arbitrary GPU data to be passed from EC to ACPI FW; this patch adds support for it. Also the current host event for _Q0C (EC_HOST_EVENT_USB_CHARGER) is unused, and is being repurposed in the next CL, so this patch drops the handler. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iff6f935a5bdc8c47277eaa6bcbedd5fc5ed311a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13mb/google/brya/acpi: Update GPIO polling methodTim Wawrzynczak
The preferred way of polling in ACPI I've seen is usually to just divide the sleep into N chunks, and ignore the time taken in between. This works in practice (validated with Timer calls before and after). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a2cd82cea05c539eff30b9b9d6ef18550d17686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Modify NBCI _DSM subfunctionTim Wawrzynczak
The NBCI "get callbacks" _DSM subfunction should utilize the same "get callbacks" subfunction from the GPS _DSM subfunction; this patch adds that Method call into the ACPI code. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf2f148b5a95acccb02f47cba1ef33a9fc16bcd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Keep track of dGPU power stateTim Wawrzynczak
To avoid extraneous calls from the kernel to _ON or _OFF, keep track of the power state of the GPU in an integer and exit _ON and _OFF routines early when attempting to enter the current state. BUG=b:236676400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13cpu/amd: Add common helpers for TSEG and SMMArthur Heymans
Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-13mainboard/msi/ms7d25/gpio.h: Remove redundant NAF_VWE definitionMichał Żygowski
The NAF_VWE bit definition is already present in src/soc/intel/common/block/include/intelblocks/gpio.h. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1fe713ee08438be49308f5e777cd466cdbc45d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-13mb/starlabs/lite/{glk/glkr}: Remove Bluetooth USB portSean Rhodes
This reverts commit 0225af3c2ba661de82e15f163258605917ca28cf as it has no effect as the USB interface is configured by FSP S. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I20ca355eb1e088d7a7c8eacbc888ffc90833194b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-13mb/google/nissa/var/pujjo: Add WFC camera settingStanley Wu
Modify USB2.0 port[6] setting for WFC camera support BUG=b:235182560 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I78dad102be2d915a251f6528eef07f2056001b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65777 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13payloads/tianocore: Limit legacy build options to CorebootPayloadPkgSean Rhodes
Limited to two legacy build options to only be set when CorebootPayloadPkg is used, as they don't exist in UefiPayloadPkg. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I71aaa940543075962e167b52b23f45976d39c616 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-13payloads/tianocore: Allow edk2 to use the full framebufferSean Rhodes
Set all PCDs relating to console size to 0, which allows edk2 to use the full framebuffer. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id105a2c822a2b05da6e45dac9deeca1f155bfa33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-13payloads/tianocore: Hook up PCI Express Base Address and LengthSean Rhodes
Hook up edk2 build options PCIE_BASE_ADDRESS and PCIE_BASE_LENGTH to CONFIG_ECAM_MMCONF_BASE_ADDRESS and CONFIG_ECAM_MMCONF_LENGTH. This patch has been reviewed upstream but not yet merged (2022/07/08). It won't cause any problems for any existing branches or forks that do not have this build option hooked up. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie5d50cc4619354d3c98adf6cde12c192be759869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-13cpu/x86/mp_init: retype do_smm element in mp_state struct to boolFelix Held
The do_smm struct element in the mp_state struct was an int even though it only had two possible states, so change it to bool to make this more obvious. Also change the return type of is_smm_enabled from int to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d2d95f0497649d67565243d14a5ab9c9cdda412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-13mb/google/nissa/var/craask: Move codec item to SSFCTyler Wang
Move audio codec item from fw_config to SSFC. BUG=b:238353613 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I361ef54cd2ee3e0a423ed5086184936d6f09e099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-13soc/mediatek: Move SPMI device table to SoC folderHui Liu
The SPMI devices on MT8188 are different from previous SoCs, so we move them to SoC folder. We also move SoC-specific definitions to soc/pmif.h. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13mb/google/geralt: add usb host supportShaocheng Wang
Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I52174306eb0c87c6e5a3665051099b5c0e8f45a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65755 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: add usb host supportShaocheng Wang
Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I3494b687b811466cb6b988164d3c5b6fecc3016a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65754 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: Enable mmu operation for L2C SRAM and DMARex-BC Chen
- Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. - Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I10f1cb8c62dfa78f59a4a5ea6087609668a0c2aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65753 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: Add video/audio mtcmos settingRex-BC Chen
Add power domain data for video and audio. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: Ic5fd496cbc6904b42eae28a62bf00a71f0ef508d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13soc/mediatek/mt8188: Add PLL and clock init supportgarmin chang
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. For usb clock setting, we also implement mt_pll_usb_clock_setting() to enable usb clock for all ports. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13mb/google/nissa: Remove GPP_B11 PAD configurationHarsha B R
Remove the pad configuration for GPP_B11 as this is not used in Nereid/Nivviks BUG=b:227694137 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-13soc/intel/meteorlake: Use double digit GPIO pad numbersKapil Porwal
Google uses two digit GPIO pad numbers for internal GPIO references and Intel has updated their GPIO naming schemes too (see the GPIO implementation worksheet #641238) so use double digit GPIO pad numbers. Format - "GPP_%c%02d", gpio_group, gpio_pad_num e.g. GPP_A0 -> GPP_A00, GPP_V2 -> GPP_V02, GPP_C9 -> GPP_C09 etc. BUG=b:238196741 TEST=Able to build meteorlake based google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13vc/intel/fsp2_0: Update partial headers to MTL.FSP2253.00Kapil Porwal
Update partial headers to MeteorLake FSP v2253.00 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If2d6c80bd35afd68588fef57e38064c5b1e1a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-12docs/infra/services: Add Gerrit SSH host keys and fingerprintsFelix Singer
Change-Id: Ic687594517e9dc8a7f3ea7047a5ec4448ed5a043 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-12doc/index: document the correct way to spell corebootFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e0c96dc4b68e60f9a36afb361c4d1c6f9742c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-12soc/samsung/exynos5420: Use int instead of char for count variablePaul Menzel
This micro optimization of using unsigned char instead of unsigned integer actually generates one more instruction. .LVL296: .LVL296: .L198: .L198: .loc 1 912 16 is_stmt 1 discriminator 1 view .LVU1740 .loc 1 912 16 is_stmt 1 discriminator 1 view .LVU1740 uxtb r2, r3 | cmp r7, r3 cmp r7, r2 < bhi .L199 bhi .L199 .loc 1 916 1 is_stmt 0 view .LVU1741 .loc 1 916 1 is_stmt 0 view .LVU1741 add sp, sp, #36 add sp, sp, #36 .cfi_remember_state .cfi_remember_state .cfi_def_cfa_offset 20 .cfi_def_cfa_offset 20 @ sp needed @ sp needed pop {r4, r5, r6, r7, pc} pop {r4, r5, r6, r7, pc} Fix it, so nobody can copy that. Change-Id: If5ffeacc7ac3c53a82b260cfb81ef7debc40034a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-12util: Allow installing to a build rootTim Crawford
Modify util Makefiles to allow installing to a build root specified by DESTDIR. Allows using the `install` target for packaging. Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60540 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-12soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clockRex-BC Chen
There are clock settings for usb in mt8195 and mt8188, so we add a new function which is implemented in pll.c to do this. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40b358b197541bc5281645879553340059829db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12soc/mediatek/mt8188: Add I2C driver supportkewei.xu
Add I2C controller drivers. TEST=build pass BUG=b:233720142 Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com> Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12mb/google/dedede/var/shotzo: Update GPIO GPP_S2/S3 pin definitionTony Huang
Based on latest schematic: Set GPP_S2 DMIC1_CLK/ GPP_S3 DMIC1_DATA to NC. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4044cb7ba963153e1e478294dbf960fb79b97b5c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-07-12mb/google/brya/var/agah: Disable thunderbolt interfaceTony Huang
Agah doesn't support TBT interface so disable it in devicetree, for fitimage configuration is at chrome-internal:4846869. BUG=b:224423318 TEST=Build and check DUT boots. Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/google/brya/var/banshee: Update VR domain settingsFrank Wu
Update the VR domain settings based on the request of internal team. - IA ac_loadline from 2.3mOhms to 2.4mOhms. - IA dc_loadline from 2.3mOhms to 2.28mOhms. - GT ac_loadline from 3.2mOhms to 3.13mOhms. - GT dc_loadline from 3.2mOhms to 2.94mOhms. BUG=b:237044562 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I665665ab8e3bcd6d4643f8b954b86fad3ef78ccd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-11soc/samsung/exynos5420: Add space between comment markers and commentPaul Menzel
Change-Id: Ica9014ee077ea416fdb4c7316c9619cf81fca510 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-11soc/intel/meteorlake: Align TCSS functions through SBIJohn Zhao
This change aligns the Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication through the sideband access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I393f6e1c7d322878cbb684cd95bfa2477195b23a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 05:10:23 +0000