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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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If ACPI is above 4G it's not possible to have a valid RSDT pointer in
RSDP, therefore swap RSDT and XSDT. Both are always generated on x86.
On other architectures RSDT is often skipped, e.g. aarch64. On top of
that the OS looks at XSDT first. So unconditionally using XSDT and not
RSDT is fine.
This also deal with the ACPI pointer being above 4G. This currently
never happens with x86 platforms.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6588676186faa896b6076f871d7f8f633db21e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This makes sure google/ovis don't get a random mac address on boot.
Additionally, program the LAN WAKE GPIO properly as per the Ovis
schematics dated July'23.
BUG=b:293905992
TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles.
Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic1533cb520a057b29fc8f926db38338cd3401b18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76295
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76070
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I9e6544c956cb3d516d2e5900357af9ae8976cc8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76131
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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TESTED acpixtract -a is able to extract all the dumped tables including
FACS and DSDT.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Arm needs very little of FADT. Just a HW reduced model bit and low power
idle bit set.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76180
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I84ab0068e8409a5e525ddc781347087680d80640
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AB-MGCL.
BUG=b:293240969
TEST=emerge-dedede coreboot
Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Configure GPIOs based on schematics and confirm with EE.
BUG=b:290248526
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable.
2. Update passive policy and critical policy.
BUG=b:285477026, b:293540179
TEST=emerge-nissa coreboot and check the OEM variable.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
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It's not expected that non-x86 arch implement x86 style sleep states and
resume.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76178
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This pulls just one commit:
* commit a4be8a21b0e2 (Avoid warning '"Pos32" is already use-visible')
Change-Id: I908d5f2b98e2251a09c587d82b3e7fab55b338a2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76868
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This pulls just one commit:
* commit 584629b9f477 (Avoid warning '"Pos64" is already use-visible')
Change-Id: I816f915d991d3d436d0468ca411037b1dc6d0e56
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76867
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This reverts commit 91f5da477677cc6a7a7d5cdc50f5d2bf71981e44.
Commit breaks booting on MDN (and likely others). Boot hangs on:
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
Change-Id: Id8042690af2764d6e46fe01287be598091b1a239
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76718
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Select this Kconfig to ensure the PSP_ADD_MSR is properly programmed
across all cores.
This resolves a Windows BSOD "CRYPTO_LIBRARY_INTERNAL_ERROR."
BUG=b:293571109
BRANCH=skyrim
TEST=build/boot google/skyrim, use rdmsr to verify MSR value identical
across all cores.
Change-Id: I67391b49496d767912f5d81c1758a52a70fca6f6
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76809
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is already selected here device/dram/Makefile.inc
Change-Id: I32a1ecc4e0f90725f9356158ce2978502b590d5c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76390
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Translate the coreboot framebuffer info from coreboot tables to
the Linux zero page.
Tested in QEMU/Q35 with a kernel w/ efifb enabled.
Change-Id: I2447b2366df8dd8ffe741c943de544d8b4d02dff
Signed-off-by: Nico Huber <nico.h@gmx.de>
Co-authored-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76431
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
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In the datasheet of ILI9882T [1] section 3.11 Power On/Off Sequence,
the TReset-CMD (Reset to First Command in Display Sleep In Mode) should
be larger than 10ms, but it's 1.1ms now. This may cause abnormal
display as some commands may be lost during power on. Fix this and
leave some margins by increasing TReset-CMD to 20ms. Also, to align
with the kernel driver structure starry_ili9882t_init_cmd, add 20ms
delay at the end of command.
[1] ILI9882T_Datasheet_20220428.pdf
BUG=b:293380212
TEST=Boot and display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76766
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iad9cbe16a2d1881d74edcc702be843168df8a4ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3d5838b825c6ac2a2959388381004993024081c3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76813
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Id19193b960935eeffca8e8db60073321592368fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76836
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I6b87680ec9f501945ae266ae4e4927efd2399d56
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76815
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iab55c57ee5cac60911c9fe4cee8d86a252bde372
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76839
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3ab3538b276fee5ed135bb4e88d9ef2cd6a00bb9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76843
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I79e4b34fe682f5f21415cb93cf65394881173b34
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76842
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I17811256b04a17539d3ed77f406892ae77e97515
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76848
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3fd3f068ff731e1d9fed7c38ba6815e1eed86450
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ibd1e4bc96a2f5eea746328a09d123629c20b272c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76851
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EFS_OFFSET is the relative address to flash base. We can not
assume the flash size is 16M.
The change will affect only Gardenia and Pademelon whose flash size
are 8M.
Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, S0iX test is failing because S0i2 susbstate is blocked.
Enable RTD3 for SSD to unblock S0i2.2 substate residency.
BUG=none
TEST=Screebo can enter into S0iX.
S0iX substate residency w/o this CL -
```
Substate Residency
S0i2.0 0
S0i2.1 38451594
S0i2.2 0
```
S0iX substate residency w/ this CL -
```
Substate Residency
S0i2.0 0
S0i2.1 12108
S0i2.2 33878424
```
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Restrict ASPM to L1 for SD controller to avoid AERs.
BUG=b:288830220
TEST=No PCIE AER on SD controller on Screebo.
w/o this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
~ # lspci -s 02:00.0 -vvv | grep -i aspm
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
~ # dmesg | grep -i -e "pci.*error"
[ 0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[ 0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[ 0.735258] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000
[ 0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[ 1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[ 1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[ 1.548894] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000
[ 1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0
```
w/ this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
~ # lspci -s 02:00.0 -vvv | grep -i aspm
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
~ # dmesg | grep -i -e "pci.*error"
```
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H54G56CYRBX247
2. H9HCNNNCPMMLXR-NEE
3. MT53E1G32D2NP-046 WT:B
4. K4UBE3D4AB-MGCL
5. K4UBE3D4AA-MGCR
BUG=b:290811418
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always
propagated to the other cores/APs. Add a hook to run a function
which will read the MSR value from the BSP, and program it into the
APs, guarded by a Kconfig. SoCs which wish to utilize this feature
can select the Kconfig.
BUG=b:293571109
BRANCH=skyrim
TEST=tested with rest of patch train
Change-Id: I14af1a092965254979df404d8d7d9a28a15b44b8
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This patch chooses to show the early splash screen which is an
OEM feature. The current implementation is relying on the Intel
FSP GFX PEIM to perform the display initialization.
Having this feature allows the platform to show the user notification
with 500ms since boot compared to traditional scenarios where first
user notification is coming from kernel (typically ~3sec+ after cpu
reset). Eventually this feature will help to improve the user
experience while booting Intel SoC platform based chromeos devices.
BUG=b:284799726
TEST=Able to see the early splash screen on google/rex.
Change-Id: I399ddb6618e774302200e8a87629647ba070d080
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These devices are not present/used on CYAN boards.
Change-Id: I012b49562c2b932822823537032e2265901ddc81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Set the ACPI status (_STA) for the PD device enabled+visible, to allow
coolstar's Windows drivers for USB4/Thunderbolt to attach.
TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify
USB4/TB ports are functional for PD and data at USB4 speeds.
Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow
coolstar's Windows drivers for the EC and keyboard backlight to attach.
TEST=build/boot Win11 on google/samus, install EC/kblight drivers,
verify keyboard backlight control functional.
Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
No drivers are needed/available, so hide the device to prevent
an unknown device from showing under Device Manager.
Linux does not use the ACPI _STA so no effect there.
Change-Id: I02efb64a845edc6e4fc559e7e99a7825abf4c2aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
While FSP programs the VmxEnable UPD per CONFIG_ENABLE_VMX, it doesn't
set the lock bit, which prevents Windows from enabling virtualization
on devices which support it. Call set_vmx_and_lock() to ensure the
lock bit is properly set.
TEST=build/boot Win11 on google/ampton,reef; verify virtualization
enabled.
Change-Id: I54ea0adb0a6d10f2df18f604b1f1e5a7a145dfb3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76804
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Ovis4ES variant supports only ESx SoCs. Existing Ovis variant will
support QS SoCs.
BUG=b:293409364
TEST=util/abuild/abuild -p none -t google/rex -b ovis4es -x -a
TEST=util/abuild/abuild -p none -t google/rex -b ovis -x -a
Change-Id: Iacf5ef6d3dfee8838fe13e68b254a84e4a6cf200
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76789
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch changes the `EC CONx Mapping` to fix the hot-plug issue
where attaching a device to USB-C port C1 can affect the USB-C
display over port C2.
Note: `PMC MUX Mapping` remains unchanged to reflect the underlying
board design where the physical MUX has swapped between C1 and C2
USB-C port.
Before:
| PMC MUX Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
| EC CONx Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
Physical Mapping between EC and SoC as below:
Port C0 - EC CON0 ----> PMC MUX CON0
Port C1 - EC CON1 ----> PMC MUX CON2
Port C2 - EC CON2 ----> PMC MUX CON1
After:
| PMC MUX Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
| EC CONx Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 1 | 3 |
| USB3-Port | 0 | 1 | 2 |
Physical Mapping between EC and SoC as below:
Port C0 - EC CON0 ----> PMC MUX CON0
Port C1 - EC CON1 ----> PMC MUX CON1
Port C2 - EC CON2 ----> PMC MUX CON2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I59e2630bc0f93321cc4b734fcf3c4cf254882477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Typically we set SaOcSupport to allow overclocking RAM, but addw2 saw a
high rate of errors when using the provided 3200 MHz DIMMs. Disable OC
so modules run at the standard 2933 MHz.
Change-Id: I469b9c73d2e6bfa0b3c9175bcc87584aeaa95f75
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Perform a codec reset to match all other System76 boards.
This applies commit 705ebbea0477 ("mb/system76: Reset Realtek codec
before configuring") to boards that were added later.
Change-Id: I618cc042f1803d07bfc067d1999e1c44ab4a1fa9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Users report having the touchscreen as a wake device causes many
spurious wakeups due to proximity to the keyboard when the lid is
closed, so remove it as a wake source.
TEST=build/boot google/glimmer, observe no unintended wakeups when
the lid is closed.
Change-Id: Id16cabcd21afa0b373ecddd9eb3b0b8befb71576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the default branch used for MrChromebox's edk2 fork from 2023-04
to 2023-06. This updated branch has been rebased on the latest upstream
stable tag (edk2-stable202305), and fixes issues booting on AMD Zen
platforms (Picasso and newer).
TEST=build/boot google boards link, panther, lulu,reef, ampton, akemi,
banshee, zork, frostflow with edk2 payload selected.
Change-Id: I4867d453514f2b00f66ffdad50e091e5b80afdcb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
This matches the change done for DDR4 in commit 8509c25eece8
("soc/intel/alderlake: Allow channel 0 for memory-down").
Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the
System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only
boards in the tree using mixed memory topology.
Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Drop the program name and split the printf call with multiple lines of
text into separate printk calls.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I43df1fd02ce0fdbb6b22e1d4eda45017811c48d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76774
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use the domain number in static references to pci device so that
device domain 0x20 on
device pci 00.0 on end
end
results in
DEVTREE_CONST struct device *const __pci_32_00_0 = &dev_#something;
in static.c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7a98b2325ee08feb1a3d1d4b333f3f4e53934b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
Set the ACPI SSID using Google's project campfire ID for EVE, to allow
coolstar's Windows drivers to identify the device (since it uses a
generic ACPI _HID). Custom drivers are necessary under Windows since
the touchpad firmware is not fully I2C-HID compliant.
TEST=build/boot Win11 on google/eve, verify touchpad fully functional.
Change-Id: I3b8d56ff01d4cca7ba5c02f1aaab1a7049607dbc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
|
|
Change-Id: I7c9c938bd20d36be8fdfb0d95bb58a7259650693
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
CB:73353 switched ADL boards from using S0ix to S3. DevSlp can be
reenabled now as it no longer breaks suspend.
Change-Id: I618696833b7ed02e49c35d06021b730be91d879e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
|
System76 EC since system76/ec@99dfbeaec3b8 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 value from
coreboot since it won't be used.
Change-Id: I2bc37f12aab11910b4fe029efcee891a93257529
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
|
Do not reconfigured LSX0 so that the FSP values are used.
Change-Id: I76e2ab01a5e853e3c1ac78b471ea0aa87d703d52
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76751
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for vell board. Please refer Intel doc#723158 for
more information.
BUG=b:293535284
TEST=build and boot vell
Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Some SoC like Genoa require this.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I01ff792e8016b16f34bc69722469b63cae5a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76468
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
The EAPD pin needs to be enabled and set in order for the headphone
jack to work properly. It's already done for the speaker in the
beep verbs, but needs to be done for the HP jack as well in order
for output to work properly under Windows.
TEST=build/boot Win11 on LINK, verify headphone output functional
when headphones plugged in.
Change-Id: I411d7317aefc1154635c4c17ca0dc1e37c9f40f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76746
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the pirrha variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:292134655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PIRRHA
Change-Id: Idc0a4dbb467cbdb91a5ed55c5e0a9e898e775b11
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76768
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Vendor changes touchscreen firmware to use hid method instead of i2c.
BUG=b:274707912
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I8e9e0b757e337db6af3fbf3cd4fdbc0079646179
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76680
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Change-Id: Ie7f2144d0af21ba111464dfd135159704a3d82b7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76474
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The EC serial port on these devices is not accessible to the end user
and exposing it to the OS via ACPI serves no purpose. Debugging over
the EC serial port (via the servo interface) does not require the
ACPI exist. Drop it since it's not needed and serves no purpose.
TEST=build/boot Win11 on auron/link/slippy, verify Windows Device
Manager no longer shows an unusable COM port.
Change-Id: If453bfca8e094aa06043293bdf91a40c38cc7866
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76793
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie153212a6efa98d7a8942097a1d263837510074d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I03c21e180e9e399e5cb451bf3b9cfb6484cab68b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I00807a435a21e078c89f797cfd0b00d03604ea0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76786
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id c161772f4:
2023-06-08 15:47:09 +0200 - (Merge "refactor(el3-spmc): add emad_advance()" into integration)
to commit id 37366af8d:
2023-07-28 17:04:54 +0200 - (Merge "fix(cpus): fix minor issue seen with a9 cpu" into integration)
This brings in 287 new commits.
Change-Id: Ic364a54154a7b4c5757f9d8abafe2047159ea3ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The non-PCI resources added to the domain device are resource consumers,
so they mustn't be reported as resource producers. To make sure that
this is the case, skip all resources that have the IORESOURCE_RESERVE
flag set in amd_pci_domain_fill_ssdt.
Commit 7a5dd781d147 ("soc/amd/common/data_fabric/domain: provide
amd_pci_domain_fill_ssdt") that introduced amd_pci_domain_fill_ssdt
already contained the bug, but since no MMIO range consumers were added
back then, the bug only became visible when commit 32169720bb67
("soc/amd/common/data_fabric/domain: report non-PCI MMIO resources")
added the reserved non-PCI MMIO resources to the domain device's
resources resulting in MMIO producer objects being generated for MMIO
consumers. Those producers that should have been consumers then
overlapped with the actual MMIO resource producers which caused Windows
to BSOD with an ACPI_BIOS_ERROR.
TEST=The non-PCI MMIO resources are no longer added as resource
producers and Windows boots again on google/frostflow.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ib099675bc5bea93bf7c2a80f741bef067fd37a58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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When iterating over the resource list in amd_pci_domain_fill_ssdt, don't
return when a resource is unassigned, but just continue to the next loop
iteration so the resulting SSDT will be complete and not broken due to
a missing resource template footer and the scope not being closed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I39fe516f27a6d971fb9c57a1e64ead79d23aff08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I80b4b2df4a38dcbb28d928018446e91acae90ee6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3d716b29d8e28584a0c9e4056d4c93dca2873114
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76780
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: If31cbc5ae184c4eb66011666c1bb655fa16afba0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ia1d597c0e3e86db8c13829e58a8a27d9de1480b4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76788
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I52b5a83e7e484889bfef5a4e45a0279fadd58890
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I495605190b2c6cd11c7f78727ab4611e10b4d9d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I53ffa4b35d35d4f8b0170377041b258d4bd2eeeb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iea63e7ce165b1c8129725136e39bff45765023e6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I688bef264ff41b2a9755133698880fa397f652d4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76755
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 49d8aa7043ea ("soc/amd/common/block/psp: Unmap EFS region after
use") removed the 'efs_is_valid' function but left the function
signature in the header file.
TEST=stoney/picasso/cezanne/mendocino/phoenix builds
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib596946679b50be63868af57e3428b4d65845419
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76750
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update SX9324 register settings based on tuning value from SEMTECH.
－ Enable GPP_B5/GPP_B6
－ Enable GPP_H19 open irq
－ Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4
BUG=b:292016304
BRANCH=None
TEST=Check register settings and confirm P-sensor function can work.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Introduce new parsing rules for ux_locales.c:ux_locales_get_text():
* Add a version byte: PRERAM_LOCALES_VERSION_BYTE in the beginning. This
provides more flexibility if we want to change the format of
preram_locales region.
* Add a new delimiter 0x01 between two string_names. This could fix the
issue that 'string_name' and 'localized_string' might be the same.
Also fix two bugs:
1. We would search for the language ID exceeding the range of current
string_name.
2. In 'move_next()', we would exceed the 'size' due to the unconditional
increase of offset.
Finally, make some minor improvements to some existing comments.
BUG=b:264666392, b:289995591
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ic0916a0badd7071fa2c43ee9cfc76ca5e79dbf8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add wifi sar table for constitution
BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I8f99c5cf486cb3e1f2825bbe3a8084f2fe57a41a
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76674
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Lower the TCC Offset by 10 degress.
Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the SSID to allow the correct Creative Labs Windows audio drivers
to attach (vs generic HDA audio ones) and provide full functionality.
Linux doesn't care about the SSID, so changing it has no effect there.
TEST=build/boot Windows, Linux on google/link, verify the correct
audio drivers attach under Windows, no regressions under Linux.
Change-Id: Ib5e523b07583289b0222ef156245fb0771ad1f1c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76745
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e75f29a52179b72b25092f0ffdfd91a182d6648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This address is more certain to not collide with other symbols.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I02eddf43a00c443a1193d6db77d6fad3715216f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Without FSP we assume TSEG is right above CBMEM.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8700803617c3fe4890e497c6d7b94f1d36e21cb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76472
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Factor out the common FSP-specific code to get the location and size of
the SMM region from the HOB that FSP has put into memory. This moves
FSP-specific code out of the common AMD SoC code into the FSP-specific
common AMD SoC code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie137bb0f4e7438a1694810ae71592a34f9d8c86e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76760
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Factor out the common FSP-specific code to report the usable and
reserved memory resources read from the HOBs that FSP has put into
memory. This both reduces code duplication and also moves FSP-specific
code out of the SoC code into the FSP-specific common AMD SoC code
folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib373c52030209235559c9cd383f48ee1b3f8f79b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76759
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0e81c08191f3c5f768bd3cad0e4915d4476c739f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Set GPP_C6(TCHSCR_REPORT_EN) and GPP_C7(TCHSCR_INT_ODL) to NC for
non-touchscreen sku.
BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=build and boot to ChromeOS
Change-Id: Ie062eef24f640c3d6c4a0b4c77792e57ac3a722c
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Uldren will support internal fivr in next phase and using fw_config to
decide the board with internal or external fivr.
BUG=b:287379760
BRANCH=firmware-nissa-15217.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B
2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E
3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP
4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 1 (0001)
H9JCNNNCP3MLYR-N6E 2 (0010)
BUG=b:292461498
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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The patch disables PCH USB2 Phy power gating to fix display flicker
BUG=b:292403156
TEST=Verified on the defeat board
Change-Id: If0c0e655c5d32f39b90635bb3c1d13d8b6993b59
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Update Touchscreen GPIO to use the correct GPIO 90. GPIO 32 was a
copy/paste from dalboz and corresponds to the FP PWR EN on trembyle
platforms.
BUG=b:292656388
TEST=build/boot morphius
Change-Id: Ia6cdbe9195535093e68dbafedaddb70aaf73da88
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76747
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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