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2016-09-14soc/intel/apollolake: initialize GNVS structure to 0Aaron Durbin
The code was not previously initializing the GNVS structure to all 0's in the ACPI write tables path. Fix this and also rearrange the ordering of updating the fields to only handle the chip_info specific bits till last such that most of the structure is filled in prior to bailing out in the case of a bad devicetree. Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16597 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14SeaBIOS: Update stable version to 1.9.3Martin Roth
The SeaBIOS Stable version 1.9.3 was released back in July. This has just 4 fixes over 1.9.1: fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL fw/pci: Add support for mapping Intel IGD via QEMU fw/pci: add Q35 S3 support build: fix .text section address alignment Change-Id: I527df85b5199942706d1188285c6678bf2f726a1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16254 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Omar Pakker Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-13mainboard/google/reef: add MKBP EC event as SCI event.Gwendal Grignou
Add MKBP as a SCI event: the EC is then able to send events coming from the sensors. BUG=b:27849483 TEST=With EC configure to send MKBP events, check sensor information are retrieved by the kernel. Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/16594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13i945.h: fix #include pathAntonello Dettori
Fix the #include path. Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13cpu/amd/family_10h-family_15h: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside cpu/amd/family_10h-family_15h. Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16436 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13lenovo/t60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/t60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16405 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/agesa/hudson: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/agesa/hudson. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16401 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/nehalem: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/nehalem. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16406 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/intel/ibexpeak: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/ibexpeak. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ic569aada9301b37e73196872584e191d553acd86 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16408 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/intel/i82801gx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801gx. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16370 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/intel/i82801ix: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801ix. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ibf20e6c08994b09d2a2e68a1a1d38a7a477493aa Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16403 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/gm45: transation away from device_tFurquan Shaikh
Replace the use of the old device_t definition inside northbridge/intel/gm45. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16402 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/via/vt8237r: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/via/vt8237r. Change-Id: I9c1211e698ef35f56dd71c2c021dea680091c1ee Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16489 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/sis/sis966: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/sis/sis966. Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/nvidia/mcp55: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/nvidia/mcp55. Change-Id: I98ac468940eaf6c456fa95540ec3e718edfe26a7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/nvidia/ck804: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/nvidia/ck801. Change-Id: I43d4d2175f0b6b9e7e2e6fe665ba3d99d792427c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16486 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/sb800: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/sb800. Change-Id: I488cde4504128331106f50b34869905e30f5ab83 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16480 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/sb700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/sb700. Change-Id: I44b0be2070719066dd18bbf2882c417caef5d8b2 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/sb600: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/sb600. Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16478 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/rs780: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/rs780. Change-Id: Ia9929baeec7423e9e2f06324038ddfbec006beb7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16477 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/rs690: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/rs690. Change-Id: Ief43393f62312bfe82e960faf56b1e2ec048f4ff Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16476 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/pi/hudson: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/pi/hudson. Change-Id: I8b22a8d9f0e90afaf0f218c5c0924a78883b7498 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16475 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/cimx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/cimx. Change-Id: Ibe2766b956b0ca02be63621aee9a230b16d9923b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/amd8111: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/amd8111. Change-Id: I76cdc32171b7ce819b53c534b3a5e57e9dd5f3dd Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16473 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdht: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdht. Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16468 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdk8: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdk8. Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16467 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdfam10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdfam10. Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16466 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/bcom/winnetp680: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/bcom/winnetp680. Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/gigabyte/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/gigabyte/*. Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/asus/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/asus/*. Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add DDR driverHakim Giydan
This driver is only a prototype driver, real driver will be integrated at a later time. Testing: booted successfully. Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16554 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add MCU driverHakim Giydan
Testing: booted successfully. Change-Id: I003f6929b00476d46be931773cd35418fe6622a6 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15529 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add WDT driverHakim Giydan
Testing: booted successfully. Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15519 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add NVM driverHakim Giydan
This driver uses BootROM callback to read and write to the nvm using I2C. Testing: booted successfully. Change-Id: I8639af3e004f6631d7e596507c106159835f979f Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add A2BUS driverHakim Giydan
A2BUS is a custom fabric. Testing: booted successfully. Change-Id: If6e61f5aa30217eb601ac460d9306166b8433569 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15523 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add PMIC driverHakim Giydan
Testing: booted successfully. Change-Id: I168206585f403d2259efe424e563982be661df0b Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16149 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add APMU driverHakim Giydan
APMU is the AP power management unit. It is a separate processor that handles enabling individual power rails. This driver handles sending and receiving commands from/to APMU. Testing: booted successfully. Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15518 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add load_validate driverHakim Giydan
Load_validate: it loads and validates images from flash using hash values stored in the BDB. Testing: booted successfully. Change-Id: I0b00e8c60ed76622d03cb232d5c4273b4077aae7 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16148 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add flash driverHakim Giydan
Testing: booted successfully. Change-Id: Iaeff9f01dbfad7f313aa237e8c71c36c4ed1e06f Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15509 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add gpio driverHakim Giydan
Testing: booted successfully. Change-Id: I89dee1bbf8b68460897f64bf673b328533e70cd4 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15508 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13google/rotor: Add support for the Rotor mainboardHakim Giydan
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell: Add stub implementation of MVMAP2315 SOCHakim Giydan
Most things still need to be filled in, but this will allow us to build boards which use this SOC. Nvidia Tegra210 SOC and Rochchip Rk3399 SOC has been used as templates to create this directory. Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15506 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13fsp_broadwell_de: Add Kconfig switch for SERIRQ operation modeWerner Zeh
The serial IRQ (SERIRQ) used by the LPC interface can operate either in continuous or in quiet mode. Add a Kconfig switch to select the desired mode. This switch can now be used on mainboard level to enable the needed mode per mainboard. Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPCWerner Zeh
Since this mainboard provides 4 COM ports on LPC, enable decoding of the corresponding addresses using the generic LPC decode registers. Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12src/arch: Improve code formattingElyes HAOUAS
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16434 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-09-12Makefile.inc: build ifdtool using its own makefileAlexander Couzens
Change-Id: I67c73c101b928d104e231064e05d367bf9584730 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16571 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12ifdtool/Makefile: use static dependenciesAlexander Couzens
The generated dependencies doesn't work when used together with our main build system. Change-Id: I93d26858e961d7e275d586a1b8a26b3d33f3bd41 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12ifdtool: fix one whitespace format errorAlexander Couzens
Change-Id: I5b1846eb3ef8253695066b315e8a105803390579 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16570 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12lenovo/t60: add hda_verb.cArthur Heymans
This creates a config for the Lenovo T60 sound card based on values taken from vendor bios (in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). The sound card configuration on the vendor bios is the same as the one on the Lenovo x60. It improves the default behavior of the sound card: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16529 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
This change adds armv7-r support for all stages. armv7-r is an ARM processor based on the Cortex-R series. Currently, there is support for armv7-a and armv7-m and armv7-a files has been modfied to accommodate armv7-r by adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants to src/include/rules.h. armv7-r exceptions support will added in a later time. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15335 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12kunimitsu: Add initial FSP2.0 supportRizwan Qureshi
Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact. Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12vendorcode/skylake: Add FSP header files without any adaptationsRizwan Qureshi
Add header files as is from FSP build output. Move the FSP header files to new location as in apollolake. Update all the FSP structure references now that they are typedef'd. Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16517 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12driver/fsp2_0: Include stdint header file in api.hNaresh G Solanki
'bool' type is reported undefined due to missing stdint.h inclusion, Fix it by including the same. Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrrRizwan Qureshi
In the current implementation of postcar_frame_add_mtrr, if provided size is bigger than the base address alignment, the alignment is considered as size and covered by the MTRRs ignoring the specified size. In this case the callee has to make sure that the provided size should be smaller or equal to the base address alignment boundary. To simplify this, utilize additonal MTRRs to cover the entire size specified. We reuse the code from cpu/x86/mtrr/mtrr.c. Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16509 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12cpu/x86: Move fls() and fms() to mtrr.hRizwan Qureshi
Move the funtion to find most significant bit set(fms) and function to find least significant bit set(fls) to a common place. And remove the duplicates. Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12arch/x86: Always compile postcar library in romstageRizwan Qureshi
postcar_loader.c has a useful library of funtions for setting up stack and MTRRs. Make it available in romstage irrespective of CONFIG_POSTCAR_STAGE for use in stack setup after Dram init. The final step of moving the used and max MTRRs on to stack is moved to a new function, that can be used outside of postcar phase. Change-Id: I322b12577d74268d03fe42a9744648763693cddd Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Enable lpss s0ixVenkateswarlu Vinjamuri
This setting enables lpss to power gate in S0ix. BUG=chrome-os-partner:53876 Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Disable CLKREQ of unused PCIe root portsVenkateswarlu Vinjamuri
1. Removes PCIe blocker for S0ix. 2. Set the correct PCIe root port for wifi/bt on EVT. 3. Turn off CLKREQs of unused PCIe root ports to power gate the IP. Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12fsp_broadwell_de: Correct access to SIRQ_CNTL registerWerner Zeh
The serial IRQ configuration register is only 8 bit wide so switch the PCI access from 16 bits to 8 bits. Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16534 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-11buildgcc: Quote command substitutionIdwer Vollering
There are shells where the result of a command substitution is subject to word splitting (e.g. dash when assigning a value inside an export statement). Change-Id: I70a5bc124af7ee621da2bdb4777f3eaba8adafbb Signed-off-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/15820 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-09-10southbridge/intel/i82801dx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801dx. Change-Id: Ic08a23f672f8b5e40b837d49a9475d52c728a306 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16485 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/i82801ax: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801ax. Change-Id: I46f0cc92e1034f045988b42df7246f5d0c8d24fc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/i82371eb: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82371eb. Change-Id: Ie15a656c817a2ffe0f44ee3a89659d138a1bf212 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16483 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/i3100: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i3100. Change-Id: Ic9616d5135cfb7206e086e51aaf82eb66540c4bb Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16482 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/fsp_rangeley. Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/x4x: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/x4x. Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16472 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/i5000: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i5000. Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/e7505: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/e7505. Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16469 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09soc/intel/apollolake: Add functions to calculate GPIO addressVaibhav Shankar
Provide iosf and GPIO functions for GPIO address calculation. BUG=chrome-os-partner:55877 Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16349 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-09util/release: Add support for signed tags and releasesPhilipp Deppenwiese
* Add gpg key command-line parameter for signing. * Add username command-line parameter for secure ssh clone. * Tag and releases are signed. * Generates ascii amored signature files. Change-Id: I41347a85145dd0389e3b69939497fb8543db4996 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/16553 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridgeDamien Zammit
Although the goal was to hide the ME device by disabling the PCI bridge, the original comment that this bridge was ME related was a mistake, this bridge is for PEG not for ME. We still need this PCI bridge "on" to enable pci express graphics add-on cards. Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16496 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09northbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/fsp_rangeley. Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16470 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfacesDamien Zammit
Previously the ME PCI interface (HECI) was being reported as present in the DMAR ACPI table even when ME firmware was missing or the PCI device was hidden and HECI would be unresponsive. Now we check via the PCI config space itself to verify if the HECI is present or not. Note that this test could fail if ME firmware is present but HECI is disabled in devicetree, because it would not advertise that the HECI exists even though there is a running ME. Perhaps this behaviour is desirable because in this case you won't see the HECI in the lspci tree anyway. Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16330 Tested-by: build bot (Jenkins) Reviewed-by: Swift Geek <swiftgeek@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08edid: Fix a function signatureNico Huber
Change-Id: Id69cecb5cdd21c2d92aca74658f39c790f7b7b01 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/15211 Tested-by: build bot (Jenkins)
2016-09-08libpayload: Fix strtok_rJeremy Compostella
This patch makes strtok_r: - handle the end of the string - handle string that contains only delimiters - do not set ptr outside of str Change-Id: I49925040d951dffb9c11425334674d8d498821f1 Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com> Reviewed-on: https://review.coreboot.org/16524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08intel/gma: Use defines for registers and values in edid.cSebastian "Swift Geek" Grzywna
This replaces magic values with defines without changing any value. Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/16339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08mainboard/google/reef: move devicetree to baseboardAaron Durbin
Move the current devicetree.cb to be under variants/baseboard. New variants can provide their own devicetree as needed. BUG=chrome-os-partner:56677 Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16510 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-08drivers/i2c/tpm: Fix early TPM probeDuncan Laurie
The early TPM probe was done directly in tis.c ignoring the lower layer that provides appropriate access to the chip. Move this into a tpm_vendor_probe() function so it can use iic_tpm_read() with all of the built-in delays and semantics instead of calling i2c_readb() directly from the wrong layer. This fixes early init failures that were seen with the cr50 i2c tpm on the reef mainboard. Change-Id: I9bb3b820d10f6e2ea24c57b90cf0edc813cdc7e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08lib: Enable hexdump in verstageDuncan Laurie
Enable the hexdump function in verstage as it can be useful there for debugging I2C and TPM transactions. Change-Id: If9dc4bcc30964e18ff5d8a98559f6306c0adec6f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08fsp_broadwell_de: Adjust printed address in SPI debug messagesWerner Zeh
For an unknown reason the printed address in the SPI debug messages is modified before it is printed by subtracting the constant 0xf020 from the passed in address. What I suppose this debug code should do is to print the used register address within the SPI controller while any parts of this address that belongs to the SPI base address should be omitted. To fix that remove the subtraction of 0xf020 and adjust the address mask to 0x3ff so that only the offset to the registers inside the SPI controller will be visible in the debug messages. In addition switch to uint8_t and friends over u8 to sync up with used types in this file. Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16500 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08Kconfig: Add option for microcode filenamesMartin Roth
Hardcoding the microcode filenames into the makefiles is great when the microcode is in the blobs directory. When the microcode isn't posted to the blobs directory, we need some method of supplying the microcode binary into the build. This can of course be done manually after the build has completed, as can be done with everything that we're including in the ROM image. Instead of making life hard for everyone though, let's just add a way to specify where the microcode rom comes from. BUG=chrome-os-partner:53013 Change-Id: I7c5127234809e8515906efa56c04af6005eecf0b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/16386 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07intel/i82801gx 82801ix: Remove OpRegion of SMBus hostKyösti Mälkki
Defining this OpRegion for SMBus controller prevents linux kernel driver i2c-i801 from registering SMBus under sysfs, with following error in dmesg: ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI) Solution taken from intel/bd82x6x. Worth noting we do not define ENABLE_SMBUS_METHODS anywhere currently. Removed remaining reference to HSTS from GETAC P470. Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16266 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07mb/intel/d945gclf: Disable combined mode to fix SATAArthur Heymans
Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4 "mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA" SATA must function in "plain" mode because it does not work in "combined" mode. Tested on d945gclf Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16319 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPIDamien Zammit
With this patch and the previous ones in this set, PCI express graphics is now working. 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218 [GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller]) Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16497 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07src/lib: Fix checkpatch warningsStefan Reinauer
The script checkpatch.pl complains about these files. Fix the warnings. Change-Id: I4271cc35bb101447a316a75273cf8a6e95ed62d5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/16011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07commonlib: move DIV_ROUND macros from nvidia/tegraArthur Heymans
DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other architectures. This patch moves them from soc/nvidia/tegra/types.h to commonlib/include/commonlib/helpers.h . Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16415 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07nb/intel/x4x: Correct typos in interrupt routing for PEGDamien Zammit
Device 1 on secondary bus instead of device 0 was being routed. Change-Id: I4207938038acf7ff941afd692e90a690d2426a05 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07nb/intel/x4x: Turn on PEG graphics in device enableDamien Zammit
Change-Id: I389c4630362af1c1bf6d281c9d2b7fc81bea2d5d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-07nb/intel/x4x: Increase MMIO PCI space to 2GiBDamien Zammit
This is necessary for PCI express graphics card add-ons, otherwise the pci allocator cannot fit the mmio for the add on card into the space it has available and the OS turns off the card. Old value was 1GiB. Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07nb/intel/x4x: Fix DMI initDamien Zammit
No more hang on DMI init when wait for DMI is re-enabled. Previously the virtual channel arbitration table was not being set up in the south/north bridges causing invalid DMI state. This has been tested on GA-G41M-ES2L with patches following. An NVIDIA GT218 card was detected by the OS and displayed using the nouveau driver with no blobs. Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16491 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07include/arch/acpi.h: change IVRS efr field to iommu_feature_infoMartin Roth
The field that was previously named 'efr' is actually the iommu feature info field. The efr field is a 64-bit field that is only present in type 11h or type 40h headers that follows the iommu feature info field. Change-Id: I62c158a258d43bf1912fedd63cc31b80321a27c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16508 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07x86/acpi.c: use #define for IVRS revision fieldMartin Roth
The revision field was correct, but the comment was wrong. The revision 1 means that the IVRS table only uses fixed length device entries. Update the field to use the IVRS revision #define. Change-Id: I4c030b31e3e3f0a402dac36ab69f43d99e131c22 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16507 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07arch/x86/include: Add #defines for IVRS tablesMartin Roth
I/O Virtualization Reporting Structure (IVRS) definitions from: AMD I/O Virtualization Technology (IOMMU) Specification 48882—Rev 2.62—February 2015 Change-Id: I4809856eb922cbd9de4a2707cee78dba603af528 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cbVenkateswarlu Vinjamuri
BUG=chrome-os-partner:56034 Change-Id: Id88d262b32dea468536575117fc34d52076a3096 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07gm45/gma.c: clean up some registersArthur Heymans
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16217 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07mainboard/google/reef: Enable audio clock and power gateVenkateswarlu Vinjamuri
Removes S0ix blocker. Sets audio clock gate and power gate bits when audio not in use. Reduces power in S0. Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07northbridge/amd/lx: remove unused function declarationAntonello Dettori
Remove an unusued function declaration that caused problems while compiling the target. Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07src/ec: Improve code formattingElyes HAOUAS
Change-Id: I93b71ca577c973046d1651d92665168b329eda1b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16503 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Omar Pakker
2016-09-06drivers/i2c/tpm: Fix error handling for tis structure not initializedDuncan Laurie
If the TPM completely fails to respond then the vendor structure may not have assigned handlers yet, so catch that case and return error so the boot can continue to recovery mode instead of asserting over and over. Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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