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2022-07-23mb/system76/tgl-u: Convert galp5 to a variantTim Crawford
Change-Id: I49185352002f6df2f9e9ab9c39d44cc9247b41b5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23mb/system76/tgl-u: Convert darp7 to a variantTim Crawford
Change-Id: I6b3fe8f4acbb5a2f9fca605e07854ebcc3f2a065 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23mb/system76/tgl-u: Convert lemp10 to variant setupTim Crawford
Change-Id: I11f2ebb94b0e9a3e2c18c5b2071ccc3e03c16655 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCHFelix Singer
Set the default value for MAX_CPUS in the SoC config and drop it from the mainboards where it is set to those values. Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23mb/google/skyrim/var/skyrim: Add two supported memory partsAmanda Huang
Add two memory parts and generate the associated DRAM part ID. 1) Hynix H9JCNNNBK3MLYR-N6E 2) Hynix H58G56AK6BX069 BUG=b:228415394 TEST=none Change-Id: I0f5ca291e02e209032e2533f4b2d4241b5e62e42 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-23mb/google/nissa/var/xivu: Disable WFC and pen garage based on fw_configIan Feng
Use fw_config Bit 0 and Bit 1 to control: Bit 0 = 0 --> enable WFC Bit 0 = 1 --> disable WFC Bit 1 = 0 --> enable pen garage wake Bit 1 = 1 --> disable pen garage wake BUG=b:238045498 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-22soc/apollolake: Don't select VBNV_CMOS if VBNV_FLASH is enabledSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If8af4657508f00feff8525b0135c7f73c1959965 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-22mb/starlabs/lite: Simplify the flash layoutSean Rhodes
Remove the sections that coreboot doesn't need to know about. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/var/skolas4es: add WFC definitions to fw_configNick Vaccaro
Reserve bits 15 and 16 in the fw_config to be used to specify WFC population status. Possible values for field WFC bits include: option WFC_ABSENT 0 option_WFC_MIPI_OVTI5675 1 option WFC_MIPI_OVTI8856 2 BUG=b:239613517 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot' and make sure it compiles successfully. Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-22util/kconfig: Add README.md documenting the uprev procedurePatrick Georgi
Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-22mb/google/rex: Add TPM device to Kconfig and devicetreeKapil Porwal
Add TPM device for Rex. Device details: I2C Controller/Bus = 4 I2C Slave Address = 0x50 GPE = GPE0_DW1_03/GPP_E03 BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22Revert "mb/google/brya/var/kinox: Configure TDC current"Dtrain Hsu
This reverts commit 58f68fb0cb8e9824256a115d1ebdc840c281e987. Reason for revert: ODM thermal team request that change IA/GT TDC current back to 20A. BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-07-22mb/google/rex: Enable EC_GOOGLE_CHROMEEC_BOARDID KconfigTarun Tuli
Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read board_id() on rex. TEST=Verified builds succeed and code is linked Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-22mb/google/geralt: Add eMMC and SD card configurationsAndy-ld Lu
Geralt reference design has both eMMC and SD card interfaces, so we configure both in mainboard_init() in ramstage. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I200a065ab96584d824153480e594e19baae97f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65976 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22soc/mediatek/mt8188: Add eMMC and SD card configurationsAndy-ld Lu
Geralt reference design has both eMMC and SD card interfaces, so we have to configure both in ramstage. Implement msdc.c (mass storage device class) to place the eMMC and SD card drivers. This implementation is based on chapter 5.9 in MT8188 Functional Specification. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/geralt: Implement regulator interfaceHui Liu
Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/var/ghost: Split ghost4adl into 3 variantsJack Rosenthal
We plan to make 3 firmwares which differ only by Kconfig options and can share a common variant directory. ghost4adl: Board with an ADL chip. ghost4es: Board near identical but has RPL-ES chip. ghost: Will have final RPL silicon. Since they will only differ by Kconfig options and Intel binary blobs, let's not duplicate the variant directory but instead share it in common. BUG=b:239456576 BRANCH=firmware-brya-14505.B TEST="make menuconfig", verify layout of board selection Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-22mb/google/brask/variants/moli: set customized_leds for RTL8111KRaihow Shi
Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli. BUG=b:218985167 TEST=emerge-brask coreboot and check RTL8111K LED behaviour Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/var/brya0: add WFC definitions to fw_configNick Vaccaro
Reserve bits 15 and 16 in the fw_config to be used to specify WFC population status. Possible values for field WFC bits include: option WFC_ABSENT 0 option_WFC_MIPI_OVTI5675 1 option WFC_MIPI_OVTI8856 2 BUG=b:239613517 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot' and make sure it compiles successfully. Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-22mb/google/kahlee: Increase VRAM from 16 to 32 MiBMatt DeVillier (AMD)
While adequate for ChromeOS, 16MiB VRAM is insufficient for current mainline Linux and Windows amdgpu drivers to operate properly. Under Linux, the driver fails to allocate a framebuffer and causes multiple kernel panics. Under Windows, the driver fails to load due to insufficient resources available. Revert the VRAM allocation to the previous amount of 32MiB. This change reverts commit 87dcd0061af4 ("mainboard/google/kahlee: Reduce VRAM to 16MB") Test: build/boot Linux 5.17.x on google/liara, verify framebuffer allocation succeeds and no kernel panic reported. Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/brya/acpi: Poll more frequently in GPPLTim Wawrzynczak
The full dGPU power-on sequence, when executed from ACPI, is taking roughly 15ms or so, which puts it close to the maximum of 20ms required from the Nvidia spec. Changing the polling period to 100 us instead of 1 ms drastically reduces the time required for this sequence, now taking typically 7 ms or so. This gives a lot more margin during the power on sequence. BUG=b:238466724 TEST=Sequence verified by EE on a scope Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-22herobrine: Create Zoglin variantShelley Chen
Zoglin is like Hoglin, but with a smaller flash size, which requires us to create a new variant. BUG=b:239851866 BRANCH=None TEST=Make sure BOARD_GOOGLE_ZOGLIN builds Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-21mb/google/brya/var/baseboard/skolas: set BOARD_ROMSIZE_KB_32768Nick Vaccaro
Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change sets it. BUG=b:239628052 BRANCH=firmware-brya-14505.B TEST="emerge-brya coreboot" and verify that the following configs are set as: CONFIG_BOARD_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB=32768 CONFIG_ROM_SIZE=0x02000000 Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-21MAINTAINERS: Add myself (Matt DeVillier) as a maintainer for all AMD SoCsMatt DeVillier (AMD)
Change-Id: I16b3a3b01b54c7bb779f13a76bbd45bee1c864f7 Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66029 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21Documentation: Add the coreboot logo in SVG formatSean Rhodes
Add the white hare coreboot logo in Documentation so that it can be used for various things, including the bootsplash for edk2. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia3a1d64cc3bf695f88e163eda96e03b841ad04a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65931 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mb/google: Use boolean type for "enable" argument for regulatorRex-BC Chen
Because 0 and 1 are the only possible values, 1. Change input argument "enable" of mainboard_enable_regulator to bool. 2. Change return value of mainboard_regulator_is_enabled() to bool. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mb/google: Replace some strings in regulator.cRex-BC Chen
From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-21soc/mediatek/mt8188: Add VMCH, VMC support for MT8188Hui Liu
For MT8188, we need to enable and adjust VMCH and VMC to support SD cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mb/google/geralt: Initialize PMICs in romstageBo-Chen Chen
TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I71cc69c74dd618f441140790af351095ead3f6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65759 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21soc/mediatek/mt8188: Add PMIF and PMIC init supportHui Liu
Add PMIF, SPI, SPMI and PMIC init code. These PMIC settings are used by MediaTek internally. We can find these registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and "MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek designers. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-21soc/mediatek: Create a function to check ulposcRex-BC Chen
We will use the same drivers for checking ulposc in MT8188, so we add a new function pmif_ulposc_check() to common. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mg/google/corsola: Enable TI50_FIRMWARE_VERSION_NOT_SUPPORTEDYu-Ping Wu
Ti50 hasn't implemented version reading yet. To avoid the confusing error message Did not recognize Cr50 version format enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this feature is not supported. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-07-21mb/google/rex: Pulling GPIO programming early to get debug msgSubrata Banik
This patch moves the early GPIO programming from `bootblock_mainboard_init` to `bootblock_mainboard_early_init`. It will help to get the early debug prints as below. TEST=Without this CL the initial report platform information was missing as below: [DEBUG]  VBOOT: Loading verstage. [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000. [DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes) [INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414 of 0x2000 bytes [INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in mcache @0xfef84d50 With this CL the complete bootblock serial msg is coming. [NOTE ]  coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022 bootblock starting (log level: 8)... [DEBUG]  CPU: Genuine Intel(R) 0000 @ [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: f0270108 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d14 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG]  IGD: device id 7d55 (rev 00) is MeteorLake-P GT2 [DEBUG]  VBOOT: Loading verstage. [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000. [DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes) [INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414 of 0x2000 bytes [INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in mcache @0xfef84d50 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e092cd749359e54fe518de21671275af4b03062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-07-20mainboard/google/guybrush: Update Wake-On-LAN functionalityRobert Zieba
The generic wifi driver currently contains a lot of intel specific functionality that results in it not working properly on AMD platforms. This commit updates the base device tree to use the generic PCIe driver instead. BUG=none TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20mainboard/google/skyrim/baseboard: Enable Wake-On-LAN functionalityRobert Zieba
The generic wifi driver currently contains a lot of intel-specific functionality that interferes with enabling wake-on-lan. This commit changes the device tree to use the generic PCIe driver which better supports this functionality. BUG=b:237682766 TEST=Booted on skyrim device and verified that wake on LAN works Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20drivers/pci/generic: Add support for `_PRW`Robert Zieba
This commit adds support for `_PRW` in this driver. BUG=b:237682766 TEST=Built and booted on Skyrim device, dumped SSDT Change-Id: Ife4ba48994cbf993bc88df8354576336438e4258 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65799 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20drivers/pcie/generic: Add support for custom ACPI nameRobert Zieba
This commit adds code to allow the driver to use an ACPI device name that is set in the device tree. BUG=b:237682766 TEST=Boot changes on Skyrim device, dumped SSDT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ie40a335e35b8ac83658e67d7cfba0750dd4784ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65798 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20drivers/pcie/generic: Clean up driverRobert Zieba
This removes unneeded and unused functionality in the driver as part of an effort to make the driver more generic and useful. The things that have been removed are: `DmaProperty` and its associated `is_untrusted` config, `_DSD` generation, and the companion device functionality. This driver isn't currently used anywhere so there won't be any issues from removing the above functionality. BUG=b:237682766 TEST=Built and booted coreboot on Skyrim device Change-Id: I0abd9148ab66ea9426069102ecc8c2fa77fea98e Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65797 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command writeFred Reitberger
The SPI_RESTRICTED_CMD register is not a PCI configuration register. It is memory mapped from the SPI bar. Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243 rev 1.50 TEST=Compile tested only Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20mb/google/brya/var/agah: Adjust I2C speedTony Huang
Adjust I2C speed for codec, TPM, touchpad. BUG=b:237691531 TEST=Built and verified adjusted I2C speed < 400KHz Change-Id: I203d137d61019235ddf38ef74607427db2a7e975 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-20Documentation: Fix broken linkLijian Zhao
Link to Linux kernel coding style changed, fix it. Change-Id: I9792d360d301b93c255306488c90375c6cc882c4 Signed-off-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-07-20arch/x86/*.ld: Don't use CPP to include linker scriptsArthur Heymans
This makes inspection of linker scripts in the build dir a little easier. Change-Id: I509faa4cee2c9f066f4e20f6038349e1165a619a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20arch/arm64,arm: Prepare for !SEPARATE_ROMSTAGEArthur Heymans
Prepare platforms for linking romstage code in the bootblock. Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-20mb/prodrive/atlas: Swtich from EC UART to LPSS UARTLean Sheng Tan
Switch x86 uart output from EC to LPSS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20google/herobrine: Add Evoker variantSheng-Liang Pan
BUG=b:238571507 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: Ie596e5c4b72de84d16571043db4291bbd0825c78 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org>
2022-07-20soc/amd/sabrina: Fix boot region address passed to PSPKarthikeyan Ramasubramanian
PSP expects PSP L2 directory address relative to the start of the SPI ROM. Also PSP does not expect BIOS L2 directory address since it is an entry in PSP L2 directory. Update the configuration such that PSP verstage passes the right address to PSP. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the address as expected by PSP. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20soc/amd/common/psp_verstage: Fix update_boot_regionKarthikeyan Ramasubramanian
On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory address relative to the start of the SPI ROM. Unfortunately there is nothing in the EFS2 header to help identify such SoCs. Hence add a config item to statically identify such SoCs. Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in the PSP L2 directory. Hence the address of BIOS L2 directory is not part of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory itself and does not expect PSP verstage to pass the address. Modify PSP verstage to handle these updates. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP L2 directory as expected. Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20soc/amd/sabrina: Do not dump CBMEM pre-bootblock contents to consoleKarthikeyan Ramasubramanian
PSP supports mapping FCH UART and verstage logs are visible in console. Hence pre-bootblock cbmem contents do not have to be dumped to console. BUG=b:238937687 TEST=Build Skyrim BIOS image. Ensure that PSP verstage logs in CBMEM are not dumped to console again during bootblock. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8336e372b894d8b2f9bbfb21ab15a78527dcc4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20soc/amd/sabrina, mb/google/skyrim: Call espi_switch_to_spi1_padsKarthikeyan Ramasubramanian
Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in verstage. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP verstage. Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-20vc/amd/fsp/sabrin/bl_uapp_header: Add SoC FW ID at the right offsetKarthikeyan Ramasubramanian
SoC FW ID needs to be populated at offset 0x58 and 0x59 in the PSP header. BUG=b:217414563 TEST=Build Skyrim BIOS image and ensure that PSP verstage is getting loaded. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibe7b26aea0567e5337ee3e6e9447aa3944c55f5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20treewide: Remove unused <cpu/x86/mtrr.h>Elyes Haouas
Change-Id: Ib852d0b2cf4d3cbdf7475bd5493bf2e585a5894a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-20treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas
Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-20mb/google/skyrim: Regenerate SPD part IDsKarthikeyan Ramasubramanian
Now that the speed is limited to 5500 Mbps for all memory parts used in Skyrim, regenerate the part IDs. Remove any custom generated part IDs and the associated SPDs. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6d8326208580a971e781887a7ec83355bb085c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65709 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20soc/apollolake: Add CSE Firmware Status RegistersSean Rhodes
Add the CSE, General Status and Miscellaneous registers and print information from them accordingly. All values were taken from Intel document number 571993. Tested on the StarLite Mk III and the correct values are shown: [DEBUG] CSE: Working State : 2 [DEBUG] CSE: Manufacturing Mode : NO [DEBUG] CSE: Operation State : 1 [DEBUG] CSE: FW Init Complete : NO [DEBUG] CSE: Error Code : 3 [DEBUG] CSE: Operation Mode : 0 [DEBUG] CSE: FPF status : unknown Please note, the values shown are in an error state. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1a5548132dadbb188a33a7ae30a0a1fa144d130f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-20soc/intel/alderlake/fsp_params.c: Set DdrSpeedControl UPDFranklin Lin
When override "max_dram_speed_mts", set the DdrSpeedControl to manual. (0:Auto, 1:Manual) BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com> Change-Id: Iffbbee8082fb1a41e0ed1db3f4ea9ec4709c9ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65877 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20Update vboot submodule to upstream mainSelma Bensaid
Updating from commit id 61971455: vboot_ref/Makefile: Expose symbols irregardless of USE_FLASHROM to commit id a975eed3: 2kernel.c: check display request in vb2api_kernel_phase2 This brings in 20 new commits. BUG=b:172339016 TEST=builds with vboot_ref uprev. Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: I8f9339f169c4c16216a9f380a7ca00a36098d7f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-20mb/google/brya/acpi: Add support for D Notify event from the Chrome ECTim Wawrzynczak
The agah EC code includes a driver to keep track of the current D Notify level that the GPU should be at. When it changes, it will send a host event to the ACPI FW, which will then pass that Notify on to the kernel driver. This patch adds support for that feature, which is described in the Nvidia Software Design Guide. BUG=b:229405562 TEST=add Printf() calls to the ACPI, and work through the various scenarios on the EC that will cause D Notify levels to change; this will cause the Printfs() to show up in the kernel log. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-20soc/intel/cmn/pch/lockdown: Guard gpmr_lockdown_cfgSean Rhodes
Guard gpmr_lockdown_cfg with SOC_INTEL_COMMON_BLOCK_GPMR so it doesn't run on platforms that don't select this. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iab5bbd399c3a654dcb95eaa8fce683a50c7322f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65227 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-19vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3257_00_40Bora Guvendik
The headers added are generated as per FSP v3257_00_40. In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:238791453 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-19payloads/tianocore: Increase default timeout for SD MMC init to 10msSean Rhodes
Firstly, change the unit of `μs` to `ms` so it's easier to read. This patch changes the default amount of time allowed to initialise SD Card Readers and eMMC drives from 1ms to 10ms. Having a timeout too short will stop certain devices from booting, which was seen on google/akemi; it throws an exception when attempting to boot from the internal eMMC drive. This new value is still lower than upstream edk2's value of 1s. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id1f66d5d50f889f07a34836ab2932b28ef7fb245 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-19mb/google/nissa/var/craask: Change craask to use 16M SPI flashTyler Wang
BUG=b:236175568 TEST=Build and test on MB, system can boot to OS. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I779355dcc69eed08703bcb8bb943dcfeeb1fdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-19mb/google/brya/var/skolas: fix comment for I2C connectionsEran Mitrani
For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-19cpu/amd: Reformat codeElyes Haouas
Most of these changes are suggested by clang-format(13.0-54) tool on Debian testing. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie4fe0e872e94f38079945970848fefd153ab7cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19mb/google/dedede/var/beadrix: Update memory part and generate DRAM IDTeddy Shih
This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:236750116 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I3f29609d9fe5143b0bfe4b78279d0780cd7e5097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-19util/spd_tools: Limit memory speed to 5500 Mbps for SabrinaKarthikeyan Ramasubramanian
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the SPD generation tool to limit to that speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-19soc/intel/apollolake: Call heci_init in romstageSean Rhodes
Call heci_init to initialise all Heci devices and bring them to d0. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id2865b649331846fc119da7c4be56cc1fed56b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-19mb/google/rex: Refactor baseboard/variant gpio pad configurationSubrata Banik
This patch tries to simplify the baseboard/variant GPIO programming starting with Google/Rex. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting with Google/Rex) TEST=Able to build and boot the Google/Rex board. AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being configured from the `rex0` variant. gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020] gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021] gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000] Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-19mb/google/brask/variants/moli: correct USB3 port2 tx_de_empRaihow Shi
Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX failed. BUG=b:236661824 TEST=emerge-brask coreboot and check USB3 port2 RX pass Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-19lint/checkpatch: Add check for used comma where semicolon could beElyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d3a49378008bad61b2a18bd8cb28be952a18006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Add a check for use of self-assignmentsElyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If47a7826ee67a2be25a4caa2a447484e5f11411b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Add a check for existence of a commit logElyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e3b98140d900c5717f4badde71c7be88fd1e23a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'Check patch "separator" and "signoff"'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id3d7375216af5bf75ed7ce61fa8ea2dfebe8ac77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for unwanted Gerrit info'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I856bfa0f0d39fda549671b1029cccdc39f831bab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'uncoalesced string fragments'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I21b2a0d87cbf610fc48e273ed78ab779ad4a6932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'concatenated string without spaces between elements'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I04e58aca4a30e82f3da0cda08403d0daf3b5fb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check indentation of a line with a break'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I79170a45cd8184ebc816b4f16656a3cfdc257f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for logical continuations'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I222e3378ded4cd73d0141cd1e38ac3282d311cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for adding lines without a newline'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bd68e9a6609a3dfa7dc856f24e4b616714d9990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for assignments on the start of a line'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia7d4b0176bad849e79f037f74c3d99ce9eb061c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19Doc/*/gerrit_guidelines.md: Expand fast-track ruleAngel Pons
Commits that fix a recently-introduced regression can be submitted early to minimise the impact of said regression. However, it is important that the commit message properly reflects what is being fixed and what commit introduced the issue. Change-Id: Ifd49582ae1cbcfe6ee3816e0658dbd0432801161 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63780 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-19soc/amd/sabrina/fsp_m_params: add UPD pointer parameter to mb callbackFelix Held
This allows the mainboard code to change FSP-M parameters depending on parameters that are only known at run time and not at build time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-18google/herobrine: Support hardware watchdog loggingKshitiz Godara
Add support for hardware watchdog event logging BUG=b:221393157 TEST=Validated on qualcomm sc7280 development board by manually triggering watchdog event and event was logged at next bootup. Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: I94971ab583f49c8a5ac232833215dbdad3a4d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65528 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/qualcomm/sc7280: Support hardware watchdog compilationKshitiz Godara
Add watchdog file compilation and watchdog space memory for sc7280. BUG=b:221393157 TEST=None Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: I6a5c4e55964aa8b4de5a641ca162355591c38fc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-07-18soc/intel/meteorlake: Allow possible options for MP InitSubrata Banik
Ported back from commit ceaf9d116949da68aa9c ("soc/intel/alderlake: Allow possible options for MP Init") This patch creates choice that lists all possible options to perform MP Init as below for Intel Meteor Lake platform: 1. MTL_USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. MTL_USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. Additionally, added `FIXME` comment to ensure Intel MTL FSP can bring back SkipMpInit UPD in MTL to let coreboot override this UPD and ensure independent MP Init flow. BUG=b:219053812 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic917e4e03e24d73190cfc72c6ed8e59af427bedf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65743 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/intel/meteorlake: Choose coreboot doing MP Init over FSPSubrata Banik
This patch enables coreboot doing Multiprocessor Initialization (MP) for Meteor Lake CPU using the native coreboot drivers and passes the MP PPI data structure to let FSP to perform CPU feature programming (anything that is restricted) as part of FSP-S. Additionally, modify the kconfig inclusion order alphabetically. BUG=b:219061518, b:219053812 TEST=Able to bring all APs from reset by coreboot and successfully able to perform all CPU feature programming using MP PPI services. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic2781ee0b39e42aa579b72d3d4ee6586d5a89a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/intel/meteorlake: Enable `DEFAULT_X2APIC_LATE_WORKAROUND`Subrata Banik
This patch ensures Intel Meteor Lake can enable the X2APIC feature. While debugging Intel Meteor Lake (MTL) based platforms it seems like enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to bring the application processors (APs) from reset using X2APIC mode. [INFO ] LAPIC 0x10 switched to X2APIC mode. ... [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [ERROR] Not all APs checked in: 0/3. [DEBUG] 0/3 eventually checked in? [ERROR] MP initialization failure. [ERROR] MP initialization failure. Note: The AP bring up flow between XAPIC and X2APIC are the same except the way to access those LAPIC registers. X2APIC expects to access all LAPIC registers using MSR (base with 0x800). The correct flow to enable X2APIC on MTL would be as follows: 1. Let BSP bring all APs in XAPIC mode. [INFO ] LAPIC 0x10 in XAPIC mode. ... [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x11 in XAPIC mode. [INFO ] LAPIC 0x0 in XAPIC mode. [INFO ] LAPIC 0x80 in XAPIC mode. 2. Call enable_x2apic() function on all CPUs (BSP and APs) And at the end of #2 above, all cores will now switch to X2APIC from XAPIC. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device a06a0 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x10 switched to X2APIC mode. ... [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device a06a0 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x11 switched to X2APIC mode. Note: Intel MTL FSP also follow the same steps for x2APIC enablement while coreboot selects USE_INTEL_FSP_MP_INIT config instead MP_SERVICES_PPI_V2. BUG=b:219061518, b:219053812 TEST=Able to perform coreboot doing AP init with DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into any hang issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18vc/intel/edk2/edk2-stable202111: Add `MpServices2.h` fileSubrata Banik
This patch fixes a missing header file compilation issue when coreboot selects MP_SERVICES_PPI_V2 config from MTL SoC. The `MpServices2.h` file doesn't exist in the upstreamed EDK2 repo (integrated with `edk2-stable202111` stable tag). Currently MpServices2.h file is being copied from the `edk2_stable202005` stable tag. BUG=b:237960384 ([Intel FSP][EDK2011] MpServices2.h header is missing in upstream EDKII git) TEST=Able to fix the compilation issue on Google/Rex (Meteor Lake) when MP_SERVICES_PPI_V2 kconfig is enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib7c406ff51439c93c6d15f3a69808b4d1590cfa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65624 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18cpu/x86: Allow SoC to select the `X2APIC_LATE_WORKAROUND`Subrata Banik
Intel Meteor Lake SoC expects to select late x2APIC enablement where AP bring up will use xAPIC and later x2APIC gets enabled using CPU init. This patch provides an option where SoC code choose the correct LAPIC access mode using choice selection. BUG=b:219061518, b:219053812 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b50a0f5e39a95c25cd2c72219d2b402550a6fad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65786 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18arch/x86: Add X2APIC_LATE_WORKAROUNDSubrata Banik
Add option to do AP bringup with LAPICs in XAPIC mode and switch to X2APIC later in CPU init. Change-Id: I94c9daa3bc7173628f84094a3d5ca59e699ad334 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65766 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/intel/meteorlake: Account for GSPI2 everywhereAngel Pons
Commit e54a8fd43247d767f16a37f3e3150b2915d809bc (soc/intel/meteorlake: Add entry for GSPI2 device) added an entry for the GSPI2 device in the devicetree, but did not add any other entries. Ensure that the rest of the code is aware of the GSPI2 device to avoid any problems. Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0 Found-by: Coverity CID 1490681 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-18treewide: Don't add bitsElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18mb/amd/*/BiosCallOuts.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I37ed13e1fa318ca0f8381f5b1b409bf80fa4da11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-18sb/amd/cimx/sb800: Remove unused and unsafe macroAngel Pons
The `IMAGE_ALIGN` macro is unsafe because its value is compound and is not enclosed in parentheses, which can cause operation order problems. However, as this macro is unused, remove it instead of fixing it. Change-Id: I099c291f44d5a2c9d32c9ff071374016ed27eee8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-18sb/amd/cimx: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba81be8ec48fa744f3263e340267a56158656a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17Makefile: Add util/kconfig/Makefile.real to nocompile listMartin Roth
Messages shown with the '$(info ...)' Make command could be shown twice because the entire Makefile stack was evaluated twice at MAKELEVEL 0. The first time was to generate the build/util/kconfig/Makefile.real file. The second time was to do the rest of the build. Adding the kconfig Makefile.real file to the nocompile list prevents all the rest of the coreboot makefiles from being read in during that first step, which prevents the messages from being printed twice. You can see this behavior by running "make clean; make -d" and searching for the text: "Successfully remade target file 'build/util/kconfig/Makefile.real'." This breaks when the build target is 'tools', so add an exception for just that target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If29c3a84c7c82ea099ef9610f4ecaa599f0d8649 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17soc/amd: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibe20d48bdd8c776f9658620a13814f96e564dabc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/common: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I04951bf142fc4061960f42ad7ae702a70215e658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/pi: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I90278683bc22d87364453f316c05afe4cd96b383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/agesa: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1497c7589570b8ff3873149a0fb212bad96ad432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 18:56:06 +0000