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2023-08-05mb/google/nissa/var/craaskov: Add DPTF parametersVan Chen
The DPTF parameters were verified by the thermal team. Based on thermal table in 290705146#comment11. Set "tcc_offset" = "8" BUG=b:290705146 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/glados: use acpi_is_wakeup_s3() vs FSP UPDMatt DeVillier
To be consistent with other boards setting the keyboard backlight at boot. Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/eve: Use keyboard backlight for proof-of-life at bootMatt DeVillier
This feature was originally present and then dropped, but turns out that users prefer it. Set the backlight to 50% in romstage, back to zero in ramstage; skip enabling on the S3 resume path. TEST=build/boot google/eve, verify keyboard backlight turns on/off as expected. Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-05mb/google/rambi: Fix built-in audio under WindowsMatt DeVillier
Move the jack detect GpioInt resources under the codec (where they belong), but also leave a copy under LPEA for since the Linux drivers (incorrectly) require them there. Add pin list for Windows' SST driver. Adapted from the Intel ValleyView edk2 ACPI reference code. TEST=build/boot Win11, Linux on google/swanky; verify audio functional OOTB under Linux, under Windows with coolstar's drivers. Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-08-05mb/google/cyan: Adjust ACPI for Maxim audioMatt DeVillier
- add HRV and GpioIO for coolstar's windows drivers - fix interrupt type for TI jack detect switch TEST=build/boot Win11, Linux on google/cyan; verify audio working OOTB under Linux, under Windows with coolstar's audio drivers. Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-08-05sb/intel/lynxpoint/Kconfig: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
Remove dummy SOUTH_BRIDGE_OPTIONS. Change-Id: Ic2f10ef03844ff55addfa27035b54971ac41dbc9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-05sb/intel/ibexpeak/Kconfig: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
Remove dummy SOUTH_BRIDGE_OPTIONS. Change-Id: Ifce7965040d96486ee8de2fba2ead9c54ee9a9f9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76948 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04mb/hp: Add EliteBook 820 G2Iru Cai
Most of the components of this laptop are tested to work, which is listed in the documentation. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04coreboot-jenkins-node/Dockerfile: Upgrade lua5 from lua5.3 to lua5.4Elyes Haouas
Change-Id: Ic1450f0fa8eb69273aa907dea2eba8f7e7131ef1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/docker/coreboot-sdk: add mrc extraction packagesTom Hiller
Add packages required to extract the `mrc.bin` from a ChromeOS firmware image as per the instructions provided in https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html Change-Id: I81ed4ef55f0ba745a8a0a0cc85c2b00360f59297 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67160 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/docker: refactor out and fix docker cache dir testMartin Roth
The test for the docker cache directory was used by two different targets, so turn it into its own target. Add missing $ for whoami commands. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic5e1d28110097eb502959e81bafe77faa0fc7fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/76707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/docker: Update coreboot-sdk-test to coreboot-jenkins-testMartin Roth
The coreboot-jenkins-test docker image takes the coreboot-jenkins-node docker image and runs a series of tests to verify that things build properly. This was original created to test the coreboot-sdk, but build functions like the documentation have been moved from the sdk image into the jenkins node, so the test needs to be renamed. Add the makefile target to the help and phony target list at the same time. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0e6282bbb163064f177c8e68e7180ba2bdc101f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04bootsplash: Add ImageMagick voodooNico Huber
The JPEG decoder, that was added many years ago to display a boot- splash in coreboot, has a few quirks. People used to do some voodoo with GIMP to convert images to the right format, but we can also achieve the same with ImageMagick's `convert`. The currently known constraints are: * The framebuffer's color format is ignored, * only YCC 4:2:0 color sampling is supported, and * width and height have to be a multiple of 16 pixels. Beside that, we can only display the bootsplash if it completely fits into the framebuffer. As the latter's size is often decided at runtime, we can't do much more than offering an option to set a specific size. Change-Id: I564e0d89fb46503ff4c11e095726616700009968 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04mb/amd/birman/port_descriptors_phoenix.c: Disable ASPMFred Reitberger
Disable ASPM on ethernet, sd card, wwan, wlan, and ssd0 PCI devices. This reduces kernel error logs such as: [ 15.172613] r8169 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04soc/amd/phoenix: Makefile change to include split hash tableKarthikeyan Ramasubramanian
Include multiple hash tables into relevant CBFS. BUG=b:277292697 TEST=Ensure that all multiple hash tables are part of Myst BIOS image with PSP verstage enabled. Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian
On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/psp_verstage: Support multiple hash tablesKarthikeyan Ramasubramanian
Currently PSP verstage updates PSP bootloader with one unified hash table containing hashes for all the signed PSP binaries to be validated. With growing number of PSP binaries to validate and memory constraints in PSP, there is a requirement to split and update the hash table into multiple smaller chunks. Hence change the update_psp_fw_hash_table() signature such that the hash tables are updated in a chipset specific way. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the Skyrim BIOS image and confirm that the hash table is identical before and after this change. Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04util/amdfwtool: Introduce support for Hash Table v2Karthikeyan Ramasubramanian
Some stages in bootflow prefer to use 16 bytes UUID instead of traditional 2 bytes FWID to identify the firmware components they verify/validate. Hence add version 2 of hash table which identifies firmware components using UUID. Other than UUID and a reserved field for alignment reasons, the format of the hash table is very similar to hash table v1. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP Verstage enabled. Ensure that the hash table v2 is built and installed into BIOS image for the components that are configured in amdfw.cfg file. Ensure that the validation by PSP is successful for all the relevant components during the boot flow. Change-Id: I2899154086cf8e90c3327178157b07ead034b16e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76586 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04util/amdfwtool: Support multiple firmware identifier typesKarthikeyan Ramasubramanian
Currently this tool generates a hash table to verify signed binaries, with a 2 byte FWID as the only kind of identifier. Going forward some binaries are going to adopt 16 byte UUID identifiers and more binaries will follow in the future SoCs. Hence add support for handling multiple firmware identifier types. While at this remove the unused fwid from the PSP FW table. BUG=b:277292697 TEST=Build BIOS image and boot to OS in Myst & Skyrim. Change-Id: I5180dc0fe812b174b1d40fea9f00a85d6ef00f2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04mb/google/skyrim: Select ACPI_S1_NOT_SUPPORTEDTim Van Patten
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby. The wake issue either needs to be fixed, or S1 should not be advertised as a capability in the ACPI table. Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not supported on Skyrim devices. This results in 'standby' being removed from /sys/power/state. BUG=b:263981434 TEST=suspend_stress_test TEST=frostflow-rev2 ~ # cat /sys/power/state freeze mem Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04mb/google/{rex,ovis}: Disable C1-state auto demotion for rex & ovisSukumar Ghorai
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter PC2 and lower state in camera preview case and save platform power. Note: C1 demotion heuristics used EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits than expected (similar to AC mode) and losing power respectively. BUG=b:286328295 TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also verified PC residency improvement ~10% in camera preview case. Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_enFelix Held
Since all indirect data fabric register accesses will be non-broadcast accesses that target a specific data fabric instance, the cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set since that makes the indirect access target only a specific data fabric instance. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-04soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotionSukumar Ghorai
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree. BUG=b:286328295 TEST=Check code compiles & boot google/rex, and correct value has been passed to FSP. Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-04soc/intel/mtl: Change default for debug consent from 3 to 6Kane Chen
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/sifive/fu540/Kconfig: Fix opensbi platformMaximilian Brune
commit 9a7a677 from opensbi project moved the fu540 platform to generic code and commit 26998f3 from opensbi removed the old non generic platform. Therefore opensbi platform needs to change to generic. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04ec/google/chromeec: move TBMC ACPI device under CRECMatt DeVillier
Tablet motion control is a function of the EC, and under Windows, the TBMC device needs to be initialized after CREC, or driver init will fail. The only way to ensure this happens is for TBMC to be a child device under CREC. TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers loaded and orientation switching functional under both OSes. Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/intel/common: Return CB_ERR when cse_data_clear_request() failsKrishna Prasad Bhat
cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04soc/intel/meteorlake: Generate new TME key on each warm bootPratikkumar Prajapati
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor Lake SOCs. This config allows Intel FSP to programs TME engine to generate a new key for each warm boot and exclude CBMEM region from being encrypted by TME. Bug=b:276120526 TEST= Boot up the system, generate kernel crash using following commands: $ echo 1 > /proc/sys/kernel/sysrq $ echo "c" > /proc/sysrq-trigger System performs warm boot automatically. Once it is booted, execute following commands in linux console of the DUT and confirm ramoops can be read. $ cat /sys/fs/pstore/console-ramoops-0 S0ix also tested and found working. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-04mb/google/rex/var/screebo: Add fw_config probe for GL9750 and RTS5227SKun Liu
Add support for SD card reader GL9750 and RTS5227S BUG=b:284273384 TEST=emerge-rex coreboot Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-04mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCLDaniel_Peng
Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:294151054 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \ src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04cpu: Get rid of CPU_SPECIFIC_OPTIONSElyes Haouas
Remove dummy CPU_SPECIFIC_OPTIONS. Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03docker/coreboot-sdk/Dockerfile: Remove old workaroundElyes Haouas
Remove old workaround for automake and aclocal. Change-Id: Ifc00a479fd08d9ee4d97df6da8762bae2d097827 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03util/docker: Remove manual symlink python3 to pythonElyes Haouas
Debian sid symlinks already python3 to python. Change-Id: Ibc3b2b047df7e1066624d4dd8aa9664ab1869222 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03drivers/intel/gma/Kconfig: Remove unused INTEL_GMA_OPREGION_2_0Elyes Haouas
Change-Id: I9241d713fb8cc26c768746c8e442b46292036d20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76694 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common/block/cse/Kconfig: Remove unused symbolsElyes Haouas
Change-Id: I35742721e049102a3e153b857824073a5d257cc3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHNElyes Haouas
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/ibm/sbp1/Kconfig: Remove unused MAX_SOCKET_UPDElyes Haouas
Change-Id: I5d9133f2255a96c8367f69dcbb198a1a142cdb82 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVERElyes Haouas
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUTElyes Haouas
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03Makefile.inc: Fix typo in commentJeremy Compostella
Replace FILANAME with FILENAME. Change-Id: I96388245df406e6b4cb1cd3418f6a32d5b23499f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76890 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03linux_trampoline: Handle 64-bit framebuffer addressesNico Huber
To support full 64-bit addresses, there is a new field `ext_lfb_base` since Linux 4.1. It is unclear, however, how a loader is supposed to know if the kernel is compatible with this. Filling these previously reserved bits doesn't hurt, but an old kernel would probably ignore them and not know that it's handling a clipped, invalid address. So we play safe, and only allow 64-bit addresses for kernels after the 2.15 version bump of the boot protocol. Change-Id: Ib20184cf207f092062a91ac3e6aa819b956efd33 Signed-off-by: Nico Huber <nico.h@gmx.de> Co-authored-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76479 Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03util/abuild: Add per-build statistics tarfileKyösti Mälkki
Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75803 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-03mb/google/nissa/var/pirrha: Generate SPD ID for supported memory partSeunghwan Kim
Add pirrha supported memory parts in mem_parts_used.txt, generate SPD IDs for them. 1. K3KL8L80CM-MGCT (Samsung) 2. K3KL6L60GM-MGCT (Samsung) BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/meteorlake: Set UPDs for TME exclusion range and new key genPratikkumar Prajapati
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs are programmed only when INTEL_TME is enabled. Bug=b:276120526 TEST=Able to build REX platform. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common: Merge TME new key gen and exclusion range configsPratikkumar Prajapati
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option named TME_KEY_REGENERATION_ON_WARM_BOOT. Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. If a new key is generated on warm boot, DRAM contents from previous warm boot will not get decrypted. This creates issue in accessing CBMEM region from previous warm boot. To mitigate the issue coreboot also programs exclusion range. Intel TME does not encrypt physical memory range set in exclusion range. Current coreboot implementation programs TME to exclude CBMEM region. When this config option is enabled, coreboot instructs Intel FSP to program TME to generate a new key on every warm boot and also exclude CBMEM region from being encrypted by TME. BUG=b:276120526 TEST=Able to build rex. Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/google: Add more comment on GFX devices for the future referenceWon Chung
Add more details to instruct future boards/models implementers regarding how GFX devices should be added. If HDMI and DP connectors are enumerated by the kernel in /sys/class/drm/ then corresponding GFX device should be added to ACPI. It is possible that some connectors do not have dedicated ports, but still enumerated. The order of GFX devices is DDIA -> DDIB -> TCPX. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-03mb/google/nissa/var/craaskov: Add overridetreeRex Chou
Add override devicetree based on schematics(ver. 20230714). BUG=b:290248526 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski
Build issue introduced by patch CB:76418 (commit hash 01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbolMichał Żygowski
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected by board with RPL-S PCH. For now only the IoT variant of RPL-S FSP is available for use with 700 series chipsets. Boards with 600 series chipsets can still use RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU support. Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPOMichał Żygowski
Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-08-03MAINTAINERS: Add a maintainer for soc/intel/meteorlake and mb/google/rexEran Mitrani
Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I7f01ee979036071ce7574254101e25b908f8e788 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-03acpi.c: Find FACS using 64bit address fieldsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-03acpi.c: Swap XSDT and RSDT for adding/finding tablesArthur Heymans
If ACPI is above 4G it's not possible to have a valid RSDT pointer in RSDP, therefore swap RSDT and XSDT. Both are always generated on x86. On other architectures RSDT is often skipped, e.g. aarch64. On top of that the OS looks at XSDT first. So unconditionally using XSDT and not RSDT is fine. This also deal with the ACPI pointer being above 4G. This currently never happens with x86 platforms. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6588676186faa896b6076f871d7f8f633db21e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-02mb/google/rex/variants/ovis: Use and configure RT8168 driverStefan Reinauer
This makes sure google/ovis don't get a random mac address on boot. Additionally, program the LAN WAKE GPIO properly as per the Ovis schematics dated July'23. BUG=b:293905992 TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles. Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-02acpi/acpi.c: Move setting FADT SCI INT to arch specific codeArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic1533cb520a057b29fc8f926db38338cd3401b18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76295 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-08-02acpi/acpi.c: Add and use acpi_arch_fill_madt()Arthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76070 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-02acpi/acpi.h: Add MADT GIC structuresArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I9e6544c956cb3d516d2e5900357af9ae8976cc8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76131 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-02acpi.c: Add FACS and DSDT to debug hex printingArthur Heymans
TESTED acpixtract -a is able to extract all the dumped tables including FACS and DSDT. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-02arch/arm64: Hook up FADTArthur Heymans
Arm needs very little of FADT. Just a HW reduced model bit and low power idle bit set. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76180 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-02acpi.c: Fill in >4G FADT entries correctlyArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-02mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AB-MGCLtongjian
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for Samsung K4U6E3S4AB-MGCL. BUG=b:293240969 TEST=emerge-dedede coreboot Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-02mb/google/nissa/var/craaskov: Configure GPIOs according to schematicsRex Chou
Configure GPIOs based on schematics and confirm with EE. BUG=b:290248526 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-02mb/google/nissa/var/joxer: support DPTF oem_variablesMark Hsieh
1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable. 2. Update passive policy and critical policy. BUG=b:285477026, b:293540179 TEST=emerge-nissa coreboot and check the OEM variable. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-08-02acpi.c: Guard FACS generationArthur Heymans
It's not expected that non-x86 arch implement x86 style sleep states and resume. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76178 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-023rdparty/libgfxinit: Uprev to avoid new GCC 13 warningNico Huber
This pulls just one commit: * commit a4be8a21b0e2 (Avoid warning '"Pos32" is already use-visible') Change-Id: I908d5f2b98e2251a09c587d82b3e7fab55b338a2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76868 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-023rdparty/libhwbase: Uprev to avoid new GCC 13 warningNico Huber
This pulls just one commit: * commit 584629b9f477 (Avoid warning '"Pos64" is already use-visible') Change-Id: I816f915d991d3d436d0468ca411037b1dc6d0e56 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76867 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01Revert "util/amdfwtool: Add some PSP entries to both levels"Matt DeVillier
This reverts commit 91f5da477677cc6a7a7d5cdc50f5d2bf71981e44. Commit breaks booting on MDN (and likely others). Boot hangs on: [NOTE ]  MRC: no data in 'RW_MRC_CACHE' Change-Id: Id8042690af2764d6e46fe01287be598091b1a239 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76718 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-01soc/amd/mendocino: select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSRMatt DeVillier
Select this Kconfig to ensure the PSP_ADD_MSR is properly programmed across all cores. This resolves a Windows BSOD "CRYPTO_LIBRARY_INTERNAL_ERROR." BUG=b:293571109 BRANCH=skyrim TEST=build/boot google/skyrim, use rdmsr to verify MSR value identical across all cores. Change-Id: I67391b49496d767912f5d81c1758a52a70fca6f6 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76809 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01nb/sandybridge: Remove redundant include of "ddr3.c"Elyes Haouas
It is already selected here device/dram/Makefile.inc Change-Id: I32a1ecc4e0f90725f9356158ce2978502b590d5c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76390 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01drivers/usb/ehci.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01linux_trampoline: Handle coreboot framebufferNico Huber
Translate the coreboot framebuffer info from coreboot tables to the Linux zero page. Tested in QEMU/Q35 with a kernel w/ efifb enabled. Change-Id: I2447b2366df8dd8ffe741c943de544d8b4d02dff Signed-off-by: Nico Huber <nico.h@gmx.de> Co-authored-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76431 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
2023-08-01drivers/mipi: sta_ili9882t: Change TReset-CMD from 1.1 ms to 20 msRuihai Zhou
In the datasheet of ILI9882T [1] section 3.11 Power On/Off Sequence, the TReset-CMD (Reset to First Command in Display Sleep In Mode) should be larger than 10ms, but it's 1.1ms now. This may cause abnormal display as some commands may be lost during power on. Fix this and leave some margins by increasing TReset-CMD to 20ms. Also, to align with the kernel driver structure starry_ili9882t_init_cmd, add 20ms delay at the end of command. [1] ILI9882T_Datasheet_20220428.pdf BUG=b:293380212 TEST=Boot and display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76766 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-01lib/gcov-io.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iad9cbe16a2d1881d74edcc702be843168df8a4ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01commonlib/tpm_log_serialized.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01vendorcode/google: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01include/acpi: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I3d5838b825c6ac2a2959388381004993024081c3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76813 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01soc/intel/broadwell/include/soc/me.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01soc/intel/common/mma: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id19193b960935eeffca8e8db60073321592368fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76836 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01util: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I6b87680ec9f501945ae266ae4e4927efd2399d56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76815 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01src/drivers/vpd/vpd.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iab55c57ee5cac60911c9fe4cee8d86a252bde372 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76839 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01security/intel/stm/StmApi.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I3ab3538b276fee5ed135bb4e88d9ef2cd6a00bb9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76843 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01security/tpm/tpm{1,2}_log_serialized.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I79e4b34fe682f5f21415cb93cf65394881173b34 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76842 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01payloads/coreinfo: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I17811256b04a17539d3ed77f406892ae77e97515 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76848 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01libpayload/drivers/cbmem_console: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I3fd3f068ff731e1d9fed7c38ba6815e1eed86450 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01commonlib/timestamp_serialized.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ibd1e4bc96a2f5eea746328a09d123629c20b272c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01payloads/libpayload/include/coreboot_tables: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76851 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01soc/amd/common: Redefine EFS_OFFSETZheng Bao
The EFS_OFFSET is the relative address to flash base. We can not assume the flash size is 16M. The change will affect only Gardenia and Pademelon whose flash size are 8M. Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01mb/google/rex/var/screebo: Enable RTD3 for SSDKapil Porwal
Currently, S0iX test is failing because S0i2 susbstate is blocked. Enable RTD3 for SSD to unblock S0i2.2 substate residency. BUG=none TEST=Screebo can enter into S0iX. S0iX substate residency w/o this CL - ``` Substate Residency S0i2.0 0 S0i2.1 38451594 S0i2.2 0 ``` S0iX substate residency w/ this CL - ``` Substate Residency S0i2.0 0 S0i2.1 12108 S0i2.2 33878424 ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-01mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controllerKapil Porwal
Restrict ASPM to L1 for SD controller to avoid AERs. BUG=b:288830220 TEST=No PCIE AER on SD controller on Screebo. w/o this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- ~ # dmesg | grep -i -e "pci.*error" [ 0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 0.735258] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 1.548894] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0 ``` w/ this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # dmesg | grep -i -e "pci.*error" ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01mb/google/dedede/var/cret: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. H54G56CYRBX247 2. H9HCNNNCPMMLXR-NEE 3. MT53E1G32D2NP-046 WT:B 4. K4UBE3D4AB-MGCL 5. K4UBE3D4AA-MGCR BUG=b:290811418 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-31soc/amd/common/cpu: Add Kconfig to program the PSP_ADDR MSRMatt DeVillier
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always propagated to the other cores/APs. Add a hook to run a function which will read the MSR value from the BSP, and program it into the APs, guarded by a Kconfig. SoCs which wish to utilize this feature can select the Kconfig. BUG=b:293571109 BRANCH=skyrim TEST=tested with rest of patch train Change-Id: I14af1a092965254979df404d8d7d9a28a15b44b8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31mb/google/rex: Allow to show early splash screen using GFX PEIMSubrata Banik
This patch chooses to show the early splash screen which is an OEM feature. The current implementation is relying on the Intel FSP GFX PEIM to perform the display initialization. Having this feature allows the platform to show the user notification with 500ms since boot compared to traditional scenarios where first user notification is coming from kernel (typically ~3sec+ after cpu reset). Eventually this feature will help to improve the user experience while booting Intel SoC platform based chromeos devices. BUG=b:284799726 TEST=Able to see the early splash screen on google/rex. Change-Id: I399ddb6618e774302200e8a87629647ba070d080 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/cyan: Disable unused devices in devicetreeMatt DeVillier
These devices are not present/used on CYAN boards. Change-Id: I012b49562c2b932822823537032e2265901ddc81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31ec/google/chromeec: Unhide ChromeEC PD ACPI deviceMatt DeVillier
Set the ACPI status (_STA) for the PD device enabled+visible, to allow coolstar's Windows drivers for USB4/Thunderbolt to attach. TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify USB4/TB ports are functional for PD and data at USB4 speeds. Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-07-31ec/google/chromeec: Unhide GOOG0004 ACPI deviceMatt DeVillier
Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow coolstar's Windows drivers for the EC and keyboard backlight to attach. TEST=build/boot Win11 on google/samus, install EC/kblight drivers, verify keyboard backlight control functional. Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-31soc/intel/apl: Hide PMC/IPC ACPI device from WindowsMatt DeVillier
No drivers are needed/available, so hide the device to prevent an unknown device from showing under Device Manager. Linux does not use the ACPI _STA so no effect there. Change-Id: I02efb64a845edc6e4fc559e7e99a7825abf4c2aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 17:44:35 +0000