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Abuild tested with -C.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Removed c2 HT Phy 520a/530a reserved bit.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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updating the passed value to the next link offset even when it was on the
requested link (cap_count).
Maximilian also found a bug where the linktype was still getting attributes
even when it wasn't initialized.
This should fix the HT problems for Fam10 C2. There are still issues with the
microcode which need to be resolved.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ways superior to v3, while lacking its completeness. But, one nice
thing: no more included .S or .c files. It's all separate compilation.
That should allow our Makefiles to work much better.
Note that the current non-CAR implementation is the default and
continues to work (tested FILO boot to Linux on both CAR and non-CAR).
Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
depend on this variable are grouped in one if, and the other parts
(romcc etc.) are in the else. This change is a model of how we should be
able to do other motherboards.
Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options.
Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file.
Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3.
Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem.
Index: src/pc80/serial.c
make uart_init non-static.
Index: src/pc80/Config.lb
add initobject
Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.
Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init.
Index: src/arch/i386/init/car.S
generic i386 car code from v3.
Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section.
Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well
get all the debugging we can.
Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds.
Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ioannis Barkas <tripl3fault@yahoo.com>
Signed-off-by: Nikos Barkas <levelwol@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Abuild tested and boot tested on s2895 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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gets us through config, but it fails during build because the original patch
duplicated some files for VIA systems.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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if it is already in its correct location.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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for users a bit.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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cbfs files at fixed addresses.
I call this transitional as the approach I am taking is to add
capability to cbfstool but not change code in a way that will break
existing usages. Later, once we're sure nothing has broken, we can start to
smooth the edges.
Right now, fixed address file are only supported via the add command.
There is one additional command syntax, so, example:
cbfstool add rom romstrap optionrom 0xffffd000
Will add the file to that fix location for a romstrap.
The assumption is that the ROM is based at the end of a 32-bit address
space. As you can see from the code, that assumption can easily be
over-ridden, if we ever need to, with a command option.
Here is one example output result.
rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print
x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0
Alignment: 16 bytes
Name Offset Type Size
h 0x0 optionrom 251
0x130 free 917120
h3 0xdffe0 optionrom 251
0xe0110 free 97960
The way this is implemented is pretty simple. I introduce a new
operator, split, that splits an unallocated area into two unallocated
areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits:
0 split -- the free area is the exact fit
1 splits -- need to split some off the front or back
2 splits -- need to split off BOTH the front and back
I think you'll be able to see what I've done. I call this transitional
because, in the end state, we only need one allocate function; for now
I've left two in, to make sure I don't break compatibilty.
Why I like this better than ldscript approach: I like having the
ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes
romstrap visible as a first class object. I think I would have latched
onto a problem I was having much more quickly had I remembered the
ROMSTRAP. It gets lost in the linker scripts.
At this point, we should be able to start removing special ROMSTRAP location
code from linker scripts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Make get_dsdt script executable.
- Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.
- Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
is correct.
- Fix broken or incorrect #include names to increase likelyhood of a
successful compile.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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EPIA-M700 target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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files for targets without failover:
src/config/nofailovercalculation.lb (64 kB XIP)
src/config/nofailovercalculation128.lb (128 kB XIP)
Targets with other XIP sizes were ignored.
This patch moves XIP size back into mainboard code.
Benefits from this patch:
- src/config/nofailovercalculation128.lb is no longer needed
- Targets with XIP sizes besides 64k and 128k benefit from refactoring
- Conceptually, this makes the include files pure calculation files
without settings.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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same. The errata need some extra room in failover.
Trivial and abuild tested
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Compared to posted patch, there are whitespace fixes
(request by Uwe), and a guard to run the erratum only
on AMD_RB_C2 (request by Marc).
Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.
This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.
Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
as it's done everywhere else
- change the default config of abuild to not
provide ROM_IMAGE_SIZE values for the images
in a CBFS configuration
- change abuild's crosscompile autodetection to
not try to use "i386-elf-i386-elf-gcc" (which
is bogus)
Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS
The changes in util/abuild/abuild are trivial and
abuild tested.
As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Change all printk_raminit to printk_spew.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The patch has been submitted by bari <bari@onelabs.com> and written
by OLPC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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them a bit more verbose and hopefully more understandable.
Old messages for my machine with 5 GB:
RAM: 0x00400000 kB
Ram3
[...]
Initializing memory: done
RAM: 0x00500000 kB
New messages:
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram3
[...]
Initializing memory: done
Handling memory hole at 0x00300000 (default)
RAM end at 0x00500000 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x00500000 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x00300000 kB
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Any endless loop after die() can be eliminated.
Dereferencing a NULL pointer is bad. die() instead.
Replace endless loops with die().
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.
Tested on dbm690t.
Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.
http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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function based on test results with many different DIMMs.
Tested by Uwe Hermann <uwe@hermann-uwe.de> on hardware.
Might need a small increase of ROM_IMAGE_SIZE for some boards, we'll see.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code, specifically the difference between pre_f and f code.
The only functional changes are in printk statements. The rest is white space.
1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks. All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code
There is much more that could be done, but it's a start.
Abuild tested and boot tested on s2892 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
(1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
In rpr 5.10.2, step 2, step 2.1 & step 2.6
(2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
instead of PCIEIND_P: 0x20.
In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec.
Stepan pointed out that 's' means string, and that therefor strings do exist.
Marking this as reserved breaks some payloads.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices".
The changes to the cmos code no longer allow usage of values larger than
32bits. Since this option was completely unused, mark it as reserved.
Fixes build after the get_option change (r4332)..
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.
get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.
The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.
build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Programming.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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http://www.coreboot.org/Coreboot_Options (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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with an error code now.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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directory just with one common file.
Changes to FADT: move to rev4, fix the generic register descriptors, detect additional VT8237S features.
Change the compiler to CORE , its revision to 42.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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out. Fix the libgcc dependency on abort() due to nested functions.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CONFIG_PCI_OPTION_ROM_RUN_REALMODE.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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version that has all assembler in a .S file and all C code in a .c
file. Also, remove requirement to move around between GDTs.
This version includes the suggestions from Peter to clean up CR0 manipulation
and to guard critical code paths by cli/sti. Tested and working on my hardware.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Last commit broke it due to leftover "void" from prototype.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This code brings a rather complete set of VGA IO routines for whoever wants it.
These consist of the by now familiar read/write/mask sets. Due to the crazy
nature of VGA, an ancient standard with bits all over the place, it makes no
sense to define individual registers. You need a vga register spec at hand if
you want to do anything anyway. These IO routines are always exposed.
It also provides code to natively set up a 640x400 VGA textmode with an 8x16
font. The native VGA mode code is behind the OPTION_VGA option, as the font
really adds to the size of the compiled/compressed rom. The font is the one
also present in the linux kernel, but this file is unlicensed. Another copy of
this is also present in coreboot in the deprecated console/btext code.
The vga console code has been cleaned up, but it still has some TODO's left
open, but that's for when i finally have found the remaining issue with the
epia-m. Right now, it is important to get parts of my work out already and to
make the remainder managable again.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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enabled or not.
CONFIG_COMPRESSED_PAYLOAD_LZMA is set only if the lzma utility is found
on the system - at least when using abuild. CBFS doesn't use this tool
for compression.
The result was a failed build if lzma (the tool) wasn't found, or
failed runtime (if src/lib/cbfs.c disables lzma decompression based on
CONFIG_COMPRESSED_PAYLOAD_LZMA)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(dev->resources-i) bytes in compact_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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for other chipsets, as suggested on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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#ifdef CONFIG_foo
is a bad idea with our build system
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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reduce the size of the bootblock (done for kontron/986lcd-m)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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our coding guidelines (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It's untested, but a good starting point for everyone.
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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on a given alignment for the RSDP and RSDT - look
it up instead.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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FILO does not use lpgcc (yet)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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effects in the arguments (eg. a pci config read, or variable increment)
"vanish" with the message, and the behaviour changes.
Some of these effects might be unwanted, but at least they are consistent now.
To reduce the memory footprint slightly, the formatted strings are discarded.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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simple and trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* fix copyright messages
* remove all HAVE_HIGH_TABLES and HAVE_LOW_TABLES preprocessor hackery
and instead use high_tables_base to find out if high tables should be used.
The code path with high tables disabled and high tables not available for
another reason should be the same.
* put MP-table into Fseg instead of 0x10. This allows us to drop an huge and ugly
portion of code. And it will make some ugly Linux warnings go away.
* use ALIGN macro instead of hand crafted aligning.
* renumber post codes in this piece of code (don't jump ahead and
back anymore)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why
the Solaris version behaves differently, but CURDIR is a safe
choice on gnu make (and we require gnu make already)
- Use tail -1 instead of tail -n1 in a file that already relies on
tail -1 support in another place
- Use tail -1 as alternative to tail -n1 in another place
- Use #define for ulong_t in romcc, as that name is used on Solaris
- Avoid fprinting a null pointer. The standard doesn't mandate that
this is a special case, and Solaris doesn't implement it that way.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the only selfboot user in CBFS.
This way, CBFS can be used without importing selfboot.c, as long as
no payloads are loaded.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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out in the mainboard config file. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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patch, just removes the warnings like
coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c:73: warning: initialization discards qualifiers from pointer target type
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* remove some dead code
* fix indentation
* comment in some destructors and fix some other warnings
* use HOSTCC instead of CC (not all the way cosmetic, but very simple)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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parameters. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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header template, as people keep forgetting them.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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tree it was copied from.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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process.
The PPC support is still stubbed, with commented out x86 code as guide
line for an implementor.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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type field contains e820 type ids, which are used by coreboot
and multiboot (the two source formats), so they can be used
as-is.
The MEMMAP_RAM_ONLY define is a way to allow a payload to opt
for only having CB_MEM_RAM type fields, which might be helpful
to support older payloads easily (just add the define, and it
won't encounter "weird" fields)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It makes the write part of flashrom dramatically faster with small
payloads like filo; and it also eliminates unnecessary wear on flash
by not writing zeros (it's unlikely this really matters; let me know
next time you flash a BIOS flash 100,000 times!).
More importantly, it allows for future partial flash upgrades with cbfs.
Note that uninitialized_flash_value is a global that can, if we ever need it,
be set by an argument in main. Assuming we ever see a flash where the
"erased" value is 0, not 0xff.
At the same time, "erased" value has been "1" on every EEPROM or
FLASH I've used for some time now.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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changing the default ROM size to 1M to accommodate this and future changes. I tested on SimNow family10h_1p.bsd and it POSTs OK.
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Vincent Lim (vincent.lim@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Vincent Lim <vincent.lim@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores.
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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> -------------------------------------+--------------------------------------
> Reporter: silicium@… | Owner: somebody
> Type: defect | Status: new
> Priority: major | Milestone:
> Component: coreboot | Version: v2
> Keywords: | Dependencies:
> Patchstatus: patch needs review |
> -------------------------------------+--------------------------------------
Fix use of uninitialized pointers. To help in future, move
the declaration to the same scope as the use.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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type 'deleted'.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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image.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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command.
Make use of it in config.g (Myles)
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Use that to fix selfboot with compressed payloads.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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bogus RSDT pointer due to a wrong order of commands.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It is nearly trivial.
Signed-off-by: Myles Watson<mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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RM4100 instead of using the ones in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I would like to remind you that this firmware enables the hardware
virtualization on the AMD cpu's on the machine. That feature was
explicitly disabled by the factory BIOS.
Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS)
than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read
config space of a device that is actually not present.
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
./cbfstool coreboot.rom add-payload filo.elf img/FILO
Signed-off-by: Samuel Verstraete <samuel.verstraete@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Tested to booting linux with qemu.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson<mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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other systems too.
So, check for svg2pdf, convert, and inkscape and use the first one that is
found to convert the SVG files to PDF.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the build server.
Add Config-abuild.lb to fix s2892 & s2891.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c
It also adds a driver for the ISA device that is found when using
0.9.1 If you look in a log without this patch you won't find the RTC
init lines.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by; Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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A manual build was yielding section overlaps, so increase
ROM_IMAGE_SIZE to the same size the Config-abuild.lb is using.
Build-tested by me using a manual build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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because it was not working anyway (it was hardcoded) and because it allows me to
fix the XIP base to something sane (and use generic computation and approach)
This board is bit tricky because until now it required the VGA BIOS on the flash
start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
aligned too to 64KB.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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critical, since unless it is fixed this tool creates empty tables that cause
coreboot to (in some cases, e.g. on qemu) triple fault and die.
For the record, an empty option_table is not allowed. The table must,
at least, have 3 32-bit entries in this order:
type -- should be 200, 0r 0xc8, i.e. 0xc8, 0, 0, 0
size of table in LE order, 4 bytes
size of header in LE order, which is always 12,0,0,0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Change sizes from unsigned int to int.
Clean up some usage and parameter checking.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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src/lib/ code in coreboot. I.e. the tool changes but the coreboot code
does not.
Currently, as cbfstool manages the ROM, there are files and empty
space. To allocate files, the code does, first, a walk of the headers
and, if that fails, does a brute-force search of the rest of the
space.
We all agree that the brute-force search has lots of problems from a
performance and correctness standpoint.
I've made a slight change. Instead of an "empty space" area with no
valid headers, I've made a header for the empty space.
So cbfs creation looks like this:
- set up the boot block
- create a file, of type CBFS_COMPONENT_NULL, that contains the empty
space. CBFS_COMPONENT_NULL was already defined in cbfs.h
Here's an example:
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs create 1048576 2048
(cbfstool) E: Unable to open (null): Bad address
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
Alignment: 16 bytes
Name Offset Type Size
0x0 0xffffffff 1046456
So how do we create a new file?
It's easy: walk the files and find a file of type CBFS_COMPONENT_NULL,
which is as large
or larger than the file you are trying to create. Then you use that file.
- if the file is the same size as the NULL file, then it's easy: take it
- if the file is smaller than the NULL file, you split the NULL file
into two parts.
note that this works in the base case: the base case is that the whole
storage is CBFS_COMPONENT_NULL.
Here's an example of adding a file.
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed t
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
Alignment: 16 bytes
Name Offset Type Size
t 0x0 stage 23176
0x5ab0 0xffffffff 1023240
Note that the NULL split and got smaller. But the entire ROM is still
contained by the two files. To walk this entire rom will require two
FLASH accesses.
Add another file:
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed tt
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
Alignment: 16 bytes
Name Offset Type Size
t 0x0 stage 23176
tt 0x5ab0 stage 23176
0xb560 0xffffffff 1000024
[rminnich@xcpu2 cbfstool]$
So, taking current ROMs as an example, I can reduce FLASH accesses for
cbfs from (potentially) thousands to (typically) less than 10.
Index: fs.c
Changes for readability and cleanliness. Move common blobs of code to functions.
New function: rom_alloc,which allocates files by finding NULL files and using/splitting.
Other changes as needed to support this usage.
Index: util.c
Creating a cbfs archive now requires creation of a NULL file covering the file system space.
Index: cbfs.h
Add a DELETED file type with value 0. Any file can be marked deleted by zero its type; this is a
FLASH-friendly definition for all known FLASH types.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
I think it is a step in the right direction. Could you add the
function prototype to cbfstool.h?
Acked-by: Myles Watson <mylesgw@gmail.com>
(I added the prototype)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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