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2020-10-22soc/intel/xeon_sp: Move ACPI prototypes from chip.hMarc Jones
Prepare for common ACPI. Move the soc ACPI function prototypes from cpx and skx chip.h to include/soc/acpi.h. Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22src/soc/intel/xeon_sp/skx: Update get_iiostack_info()Marc Jones
Add Pci64BitResourceAllocation return value to get_iiostack_info(). This matches cpx function and is used in future de-duplication. Change-Id: I939c0101c751d9afced4ab33487958b93e59924c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22sec/intel/txt: Split MTRR setup ASM code into a macroAngel Pons
If necessary, SCLEAN needs to run in early romstage, where DRAM is not working yet. In fact, that the DRAM isn't working is the reason to run SCLEAN in the first place. Before running GETSEC, CAR needs to be torn down, as MTRRs have to be reprogrammed to cache the BIOS ACM. Further, running SCLEAN leaves the system in an undefined state, where the only sane thing to do is reset the platform. Thus, invoking SCLEAN requires specific assembly prologue and epilogue sections before and after MTRR setup, and neither DRAM nor CAR may be relied upon for the MTRR setup. In order to handle this without duplicating the MTRR setup code, place it in a macro on a separate file. This needs to be a macro because the call and return instructions rely on the stack being usable, and it is not the case for SCLEAN. The MTRR code clobbers many registers, but no other choice remains when the registers cannot be saved anywhere else. Tested on Asrock B85M Pro4, BIOS ACM can still be launched. Change-Id: I2f5e82f57b458ca1637790ddc1ddc14bba68ac49 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46603 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22sec/intel/txt: Add `enable_getsec_or_reset` functionAngel Pons
This can be used to enable GETSEC/SMX in the IA32_FEATURE_CONTROL MSR, and will be put to use on Haswell in subsequent commits. Change-Id: I5a82e515c6352b6ebbc361c6a53ff528c4b6cdba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22sec/intel/txt: Extract BIOS ACM loading into a functionAngel Pons
Tested on Asrock B85M Pro4, still boots with TXT enabled. Change-Id: I0b04955b341848ea8627a9c3ffd6a68cd49c3858 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22nb/intel/haswell: Add HASWELL_HIDE_PEG_FROM_MRC optionAngel Pons
The MRC will perform PCI enumeration, and if it detects a VGA device in a PEG slot, it will disable the IGD and not reserve any memory for it. Since the memory map is locked by the time MRC finishes, the IGD can not be enabled afterwards. Changing this behavior requires patching the MRC. Hiding the PEG devices from MRC allows the IGD to be used even when a dedicated graphics card is present. However, MRC will not program the PEG AFE settings as it should, which can cause stability problems at higher PCIe link speeds. Thus, restrict this workaround to only run when the HASWELL_HIDE_PEG_FROM_MRC option is enabled. This allows the IGD to be disabled and the PEG AFE settings to be programmed when a dedicated graphics card is to be enabled, which results in increased stability. The most ideal way to fix this problem for good is to implement native platform init. Native init is necessary to make Nvidia Optimus usable. Tested on Asrock B85M Pro4, using the PEG slot with a dedicated graphics card as well as without. Graphics in both situations function properly. Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45534 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22sec/intel/txt: Only run LockConfig for LT-SXAngel Pons
LockConfig only exists on Intel TXT for Servers. Check whether this is supported using GETSEC[PARAMETERS]. This eliminates a spurious error for Client TXT platforms such as Haswell, and is a no-op on TXT for Servers. Change-Id: Ibb7b0eeba1489dc522d06ab27eafcaa0248b7083 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22sec/intel/txt: Always run SCHECK on regular bootsAngel Pons
When Boot Guard is disabled or not available, the IBB might not even exist. This is the case on traditional (non-ULT) Haswell, for example. Leave the S3 resume check as-is for now. Skylake and newer may need to run SCHECK on resume as well, but I lack the hardware to test this on. Change-Id: I70231f60d4d4c5bc8ee0fcbb0651896256fdd391 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22sec/intel/txt: Allow skipping ACM NOP functionAngel Pons
This is merely used to test whether the BIOS ACM calling code is working properly. There's no need to do this on production platforms. Testing on Haswell showed that running this NOP function breaks S3 resume with TXT. Add a Kconfig bool to control whether the NOP function is to be invoked. Change-Id: Ibf461c18a96f1add7867e1320726fadec65b7184 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22sec/intel/txt/ramstage.c: Do not init the heap on S3 resumeAngel Pons
It causes problems on Haswell: SINIT detects that the heap tables differ in size, and then issues a Class Code 9, Major Error Code 1 TXT reset. Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22sec/intel/txt/ramstage.c: Extract heap init into a functionAngel Pons
Heap initialization is self-contained, so place it into a separate function. Also, do it after the MSEG registers have been written, so that all register writes are grouped together. This has no impact. Change-Id: Id108f4cfcd2896d881d9ba267888f7ed5dd984fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22sec/intel/txt: Add and fill in BIOS Specification infoAngel Pons
This is not critical to function, but is nice to have. Change-Id: Ieb5f41f3e4c5644a31606434916c35542d35617a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46493 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22sec/intel/txt/common.c: Only log ACM error on failureAngel Pons
The TXT_BIOSACM_ERRORCODE register is only valid if TXT_SPAD bit 62 is set, or if CBnT is supported and bit 61 is set. Moreover, this is only applicable to LT-SX (i.e. platforms supporting Intel TXT for Servers). This allows TXT to work on client platforms, where these registers are regular scratchpads and are not necessarily written to by the BIOS ACM. Change-Id: If047ad79f12de5e0f34227198ee742b9e2b5eb54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46492 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22sec/intel/txt: Move DPR size to KconfigAngel Pons
Instead of hardcoding the size in code, expose it as a Kconfig symbol. This allows platform code to program the size in the MCH DPR register. Change-Id: I9b9bcfc7ceefea6882f8133a6c3755da2e64a80c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22configs: Add TXT-enabled config for Asrock B85M Pro4Angel Pons
This config selects the necessary options to enable Intel TXT on the Asrock B85M Pro4, and allows the code to be build-tested. Note that the current TXT code will not work, as it was written for Broadwell-DE. Subsequent commits will adapt the code as necessary to work on Haswell. Compatible BIOS and SINIT ACMs can be retrieved from a firmware update for the Supermicro X10SLH. As they are not in the blobs repository, use the STM binary as a placeholder so as to allow build-testing the code. Change-Id: Ibf8db5fdfac5b527520023277c6370f6efa71717 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46489 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp/skx/: Clean up soc_util.cMarc Jones
Remove unused c_util.c helper functions and clean up soc_util.h in preparation for merging common code with cpx/. Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.cMarc Jones
De-duplicate and prepare for common ACPI. Move common northbridge ACPI code to nb_acpi.c. There are a few differences between the skx and cpx defined FSP hob names and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)). Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()Marc Jones
Prepare for common ACPI code. Make acpi_fill_fadt() match intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt() to set cpx fadt->flags. Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph
SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22dedede: Create metaknight variantTim Chen
Create the metaknight variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:169813211 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_METAKNIGHT Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22security/vboot: Remove all tpm 1.2 functions for mrc hash in the tpmShelley Chen
Since MRC_SAVE_HASH_IN_TPM depends on TPM2, we can now remove the tpm 1.2 versions of functions that deal with mrc hash in the tpm as it will not be used by tpm 1.2 boards. Also move all antirollback functions that deal with mrc hash in the tpm under CONFIG(TPM2). BUG=b:150502246 BRANCH=None TEST=make sure boards are still compiling on coreboot Jenkins Change-Id: I446dde36ce2233fc40687892da1fb515ce35b82b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-22mb/google/asurada: Add Chrome OS GPIOsHung-Te Lin
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs. BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22mb/google/asurada: enable SPI devicesNicolas Boichat
Configure and initialize EC and TPM on Asurada. BUG=none TEST=boot asurada Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWAREIkjoon Jang
BRANCH=none BUG=b:159079785 TEST=1. Checkout https://review.trustedfirmware.org/c/4334 2. emerge-asurada coreboot chromeos-bootimage 3. boot asurada Change-Id: Ieb93073beff7ec95eb5406eecbfba8192f91edce Signed-off-by: Ikjoon Jang <ikjn@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46382 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/mediatek/mt8192: Add board-specific regulator APIsYidi Lin
To enable DVFS, DRAM driver needs to access four different regulators that SoC can't access directly and need board-specific implementations. To support that we need to define the getter and setter APIs for those regulators. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I0c2d471a7f8628735af90c5b5a5ab3012831e442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46405 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Make acpigen_write_opregion() argument constDuncan Laurie
This structure is not modified so it can be made const and allow the calling function to also declare it as a const structure. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46258 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Make gpio set/get arguments constDuncan Laurie
The 'struct acpi_gpio' arguments passed to acpigen functions are not modified so they can be made const, which allows drivers to also use a const pointer. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db Reviewed-on: https://review.coreboot.org/c/coreboot/+/46257 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Add ShiftLeft function helperDuncan Laurie
Provide a helper function for the ACPI shift left operator that uses the same operator for the source and result. ShiftLeft (OP, count, OP) Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46256 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Add helpers for common Store operationsDuncan Laurie
Add helpers for some store operations: Store(INTEGER, NAME) ex: Store (100, SAVE) Store(INTEGER, OP) ex: Store (100, Local0) Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46255 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Add option for reserved bits in FieldDuncan Laurie
Add an option for unused/reserved bits in a Field definition, allowing for declarations that do not start at bit 0: Field (UART, AnyAcc, NoLock, Preserve) { , 7, /* RESERVED */ BITF, /* Used bit */ } These just use byte 0 instead of a name. Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21drivers/intel/gma: Increase vbt_data sizeSrinidhi N Kaushik
With TGL FSP v3373 onwards vbt binary size changed from 8KiB to 9KiB. Due to which cbfsf_decompression_info check failed when trying to load vbt binary from cbfs because vbt decompressed_size was greater than vbt_data size. This caused Graphics init and fw screen issues. Increase the vbt_data to 9KiB to accommodate new vbt binary. BUG=b:170656067 BRANCH=none TEST=build and boot delbin and verify fw screen is loaded Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: If6ffce028f9e8bc14596bbc0a3f1476843a9334e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-21cpu/intel/common: Fix regressionPatrick Rudolph
Fix the logic introduced in CB:46276 "cpu/intel/common: only lock AES-NI when supported" which needs to be negated. Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46634 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel/common: Fix/clean up USB4 PCIe virtual/generic driverDuncan Laurie
This driver is for the root port device and needs to reference the parent device for its ACPI scope. Similarly for the debug output it needs to use the parent device, and fall back to the chip name if config->desc is not provided in the devicetree. The UID property is removed. This value is not the same as the port number; according to some docs it should be unique but it is not fully clear what it should be tied to. Regardless, it is not used by the Thunderbolt driver in the kernel. I also renamed some functions/structures to be clear that this is just an ACPI driver for the PCIe root port and not a driver for the root port itself. As part of this I removed the PCI based resource operations and the scan bus function since this device does not have children itself. Finally I added a detailed comment with an example describing what the driver is for and what properties it generates. TEST=boot on volteer and ensure the USB4 root port device and properties are added to the SSDT as described by the comment in chip.h. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel/common: Fix ACPI device name for USB4 DMA deviceDuncan Laurie
The USB4 host interface (DMA) devices need to use SA_DEVFN_* instead of SA_DEV_* when determining the ACPI name. The matching names are removed from the SOC-level ACPI name handler since they are provided by this driver now. TEST=boot on volteer and ensure TDM0 device is in the SSDT. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: If778bda82b80593452a590962dbffef6eff6484a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21device: Allow virtual/generic devices under PCI in devicetreeDuncan Laurie
This change allows a generic device to be described in the devicetree under a PCI device, such as a root port. Previously any device under a PCI device was expected to also be a PCI device and that does not allow for a virtual/generic device to be present, for example to provide ACPI properties for a root port. The changes are: - Ignore non-PCI devices found under a PCI device when scanning and do not print an error for each devfn scanned. - Don't treat non-PCI devices as leftover and remove them, instead enable them as a static device. - Don't attempt to configure a static device in the tree that is not a PCIe device type. With these changes it is now possible to have a generic device under a PCI device, for example in a USB4/TBT root port (PCIe hotplug device) this generic device will add ACPI properties for the PCIe tunnel routed to the external port: device pci 07.0 on chip soc/intel/common/block/pcie device generic 0 on end end end TEST=boot on volteer with the USB4 root port devices in chipset.cb and ensure they are enabled properly and there are no errors printed in the coreboot log, and that the device properties are created in the SSDT. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I56a491808067dc862a7adfd46852f0bd6b41cd95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46542 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21device: Export enable_static_device() functionDuncan Laurie
The work done by enable_static_devices() and scan_generic_bus() is common and can be used by other device handlers to enable a single static device. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ibfde9c4eb794714ebd9800e52b91169ceba15266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/offNico Huber
The 0x30 register is eventually controlled by coreboot's pnp_enable_resources() based on the on/off setting. Other register settings were grouped with their respective "virtual" LDN, where possible. Note, this temporarily breaks LDN 8 settings, as coreboot will ignore configuration for disabled devices. Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registersNico Huber
The `io` statement will prepare a 16-bit write, hence use `irq` for miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge 0x61 writes into 0x60). Note, using `irq` is still just a hack as these are neither I/O nor IRQs, but it's common practice in coreboot. Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/asus/f2a85-m_pro: Enable keyboard controller in devicetreePaul Menzel
The mainboard has a PS/2 port, so enable the keyboard controller in the devicetree. The PS/2 keyboard now works in SeaBIOS payload, but not in GNU/Linux, probably as ACPI code still needs to be added. Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-213rdparty/amd_blobs: update submodule pointerFelix Held
This now tracks a recently created upstream repository located at https://github.com/amd/firmware_binaries BUG=b:166107781 Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21mb/google/zork: update USB 2.0 controller Lane Parameter for morphiusKevin Chiu
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level" and "Disconnect Threshold Adjustment". COMPDISTUNE0: 0x3->0x7 TXVREFTUNE0: 0x6->0xf BUG=b:162614573 BRANCH=zork TEST=1. emerge-zork coreboot 2. check U2 registers are set correctly 3. test with servo v4 type-c, it's working expectedly. 4. U2 SI pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21mb/google/zork: Update telemetry settings for morphiusKevin Chiu
Correct the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. BUG=b:168265881 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21mb/google/dedede: drop obsolete ISST workaroundMichael Niewöhner
Early JSL silicon hang while booting Linux with ISST enabled. The malfunctioning silicon revisions have been used only for development purposes and have been phased out. Thus, drop the ISST workaround. Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21{cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner
Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21mb/asus/f2a85-m_pro: Enable UART A in Super I/OPaul Menzel
Currently, the serial console does not work. With the serial port enabled in the vendor firmware, `superiotool` outputs the global control register values below. Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`. This changes the default value 0xc0 to 0x40. Note, due configuring the system as legacy free with `HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in `FchInitResetLpcProgram()`. coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31 APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET `AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only when coreboot enables the LPC controller again in ramstage, serial output continues. PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 […] done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms Initializing devices... CPU_CLUSTER: 0 init […] Note, due to incorrect Super I/O configuration in the devicetree, the boot hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This will be fixed in follow-up commits. TEST=Receive (some) coreboot log messages over the serial console. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/supermicro/x11-lga1151-series: Follow up GPIO macro changesPatrick Georgi
Following commit f50ea988b a couple of symbols are gone, so follow up that change for this board as well. Change-Id: I09fd3a107447eb45bb46b7f0f821377943f140b2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel/common: add Kconfig for PM Timer emulation supportMichael Niewöhner
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21mb/google/dedede/variants/drawcia: update PL1 max and min power valuesSumeet R Pawnikar
Update PL1 max and min power values BUG=None BRANCH=None TEST=build and verify on dralat system Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mrc_cache: Remove unnecessary data checksum calculationShelley Chen
When MRC_SAVE_HASH_IN_TPM is selected, we can just use the TPM hash to verify the MRC_CACHE data. Thus, we don't need to calculate the checksum anymore in this case. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I1db4469da49755805b541f50c7ef2f9cdb749425 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20mrc_cache: Add tpm_hash_index field to cache_region structShelley Chen
Pull selection of tpm hash index logic into cache_region struct. This CL also enables the storing of the MRC hash into the TPM NVRAM space for both recovery and non-recovery cases. This will affect all platforms with TPM2 enabled and use the MRC_CACHE driver. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami and lazor Change-Id: I1a744d6f40f062ca3aab6157b3747e6c1f6977f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20security/vboot: Add new TPM NVRAM index MRC_RW_HASH_NV_INDEXShelley Chen
Add new index for MRC_CACHE data in RW. Also update antirollback functions to handle this new index where necessary. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I2de3c23aa56d3b576ca54dbd85c75e5b80199560 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20security/vboot: Make mrc_cache hash functions genericShelley Chen
We need to extend the functionality of the mrc_cache hash functions to work for both recovery and normal mrc_cache data. Updating the API of these functions to pass in an index to identify the hash indices for recovery and normal mode. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I9c0bb25eafc731ca9c7a95113ab940f55997fc0f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driverShelley Chen
This CL would remove these calls from fsp 2.0. Platforms that select MRC_STASH_TO_CBMEM, updating the TPM NVRAM space is moved from romstage (when data stashed to CBMEM) to ramstage (when data is written back to SPI flash. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I3088ca6927c7dbc65386c13e868afa0462086937 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-20mrc_cache: Add config MRC_SAVE_HASH_IN_TPMShelley Chen
Use this config to specify whether we want to save a hash of the MRC_CACHE in the TPM NVRAM space. Replace all uses of FSP2_0_USES_TPM_MRC_HASH with MRC_SAVE_HASH_IN_TPM and remove the FSP2_0_USES_TPM_MRC_HASH config. Note that TPM1 platforms will not select MRC_SAVE_HASH_IN_TPM as none of them use FSP2.0 and have recovery MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic5ffcdba27cb1f09c39c3835029c8d9cc3453af1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20acpi: Skip writing references for disabled devices in Type-C configTim Wawrzynczak
When emitting ACPI tables for the Type-C connector class, skip writing out a device reference if it is to a disabled device. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/45877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()Felix Singer
Clean up ahci_initialize() by using pci_dev struct. Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20cpu/x86/mtrr: add support for address space higher than 16TiBJonathan Zhang
On DeltaLake server, there are following entry in MTRR address space: 0x0000201000000000 - 0x0000201000400000 size 0x00400000 type 0 In this case, the base address (with 4k granularity) cannot be held in uint32_t. This results incorrect MTRR register setup. As the consequence UEFI forum FWTS reports following critical error: Memory range 0x100000000 to 0x183fffffff (System RAM) has incorrect attribute Uncached. Change appropriate variables' data type from uint32_t to uint64_t. Add fls64() to find least significant bit set in a 64-bit word. Add fms64() to find most significant bit set in a 64-bit word. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-10-20libpayload/storage/ahci: Use pacc pointer to read device classFelix Singer
The PCI bus gets already scanned while gathering system information. Therefore, use the pacc pointer from sysinfo_t to read the device class of PCI devices instead of rescanning the bus. Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20libpayload/arch/x86: Introduce pacc pointer in sysinfo_t structFelix Singer
Currently, the PCI bus gets scanned multiple times for various reasons (e.g. to read the device class). Therefore, and in preparation to CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan the PCI bus while gathering system information. Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20payloads/coreinfo: Rename pci_scan_bus()Felix Singer
Rename pci_scan_bus() since the name is already used in libpayload. Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20mb/google/volteer/var/terrador: Configure board specific DPTF parametersDavid Wu
Configure board specific DPTF parameters for terrador and todor BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-20mb/google/volteer/variants/lillipup: add generic SPDsNick Vaccaro
Add generic LPDDR4x SPD support for the following three memory parts: • K4U6E3S4AA-MGCR • H9HCNNNBKMMLXR-NEE • MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-203rdparty/blobs: advance submodule pointerFelix Held
The 3 commits commits from the blob repository this patch pulls in remove executable flags from files in the repo that shouldn't have those flags set: * pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit * Remove execute permission from all binaries * Remove execute permission from plaintext files Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-20cpu/intel/model_{2065x,206ax}: fix AES-NI lockingMichael Niewöhner
MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped, not package-scoped. Thus, move locking from SMM to core init, where the code gets executed once per core. Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20soc/amd/picasso: Use readelf to find bootblock size and locationZheng Bao
The Picasso build describes the DRAM region where the PSP places our bootblock. Rather than relying on Kconfig values, make the build more robust by using the actual size and target base address from the boot block's ELF file. Sample output of "readelf -l bootblock.elf" is: ------------------ Elf file type is EXEC (Executable file) Entry point 0x203fff0 There is 1 program header, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000 Section to Segment mapping: Segment Sections... 00 .text .data .bss .reset ------------------ We can extract the information from here. BUG=b:154957411 TEST=Build & boot on mandolin Change-Id: I5a26047726f897c57325387cb304fddbc73f6504 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20sb/intel/ibexpeak: Align to coreboot's coding styleAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/google/dedede: Add P-sensor for Botenalec.wang
Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/google/dedede: add PEN for Botenalec.wang
Update devicetree of boten that enable stylus BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFSAngel Pons
I often find myself having to increase the CBFS size so that TianoCore fits. Raise the default CBFS size to 2 MiB to alleviate this issue. Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variantBill XIE
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20mb/google/asurada: Init dram in romstageHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20soc/mediatek/mt8192: Do dram fast calibrationHuayang Duan
Load params from flash and use those params to do dram fast calibration. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-20ec/google/chromeec: Add wrappers to get/set the voltageYidi Lin
Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-19soc/intel/cnl: lock AES-NI feature if selectedMichael Niewöhner
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of AES-NI enablement as precaution, as suggested in Intel document 325384-070US. Locking is enabled by default (as already done in SKL and Arrandale) and may be disabled by the newly introduced Kconfig in the parent change. Tested by checking the MSR. Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: add a Kconfig to control AES-NI lockingMichael Niewöhner
Add a Kconfig to be able to disable locking of AES-NI for e.g debugging, testing, ... Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: only lock AES-NI when supportedMichael Niewöhner
Add a check to only lock AES-NI when AES is supported. Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: rework AES-NI lockingMichael Niewöhner
Simplify the AES-NI code by using msr_set and correct the comment. Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu codeMichael Niewöhner
Copy the AES-NI locking function to common cpu code to be able to reuse it. This change only copies the code and adds the MSR header file. Any further rework and later deduplication on the platforms code is done in the follow-up changes. Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19libpayload/storage: Enable STORAGE_64BIT_LBAFelix Singer
32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB capacity. Therefore, enable the 64-bit support. Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19libpayload/storage: Enable all AHCI controllers by defaultFelix Singer
Since the list of tested controllers is not actively maintained, enable all AHCI controllers by default. Also, improve the readability of its help text by adding a comma to it. Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19soc/amd/picasso: Skip SmmInfo to PSP on S3 resumeMarshall Dawson
The PSP does not accept the SmmInfo command during a resume so remove the call. BUG=b:163017485 TEST=Run SST on trembyle, verify error message goes away BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19soc/amd/picasso: Fix typo in SMU argument baseMarshall Dawson
Correct the base address. This should have no noticeable effect, as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The argument writes were not getting to any target. BUG=b:171037051 TEST=Run SST on morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-19mb/siemens/chili: Add Chili variantNico Huber
This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Factsheets/englisch/SINA_Workstation_H_Client_V_Factsheet_EN_Web.pdf Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19soc/rockchip/rk3288/include/soc/display.h: Add missing includesElyes HAOUAS
Change-Id: I3e4824722d3add989a352122b365c2a73f3f703b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macrosElyes HAOUAS
Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19src/soc/samsung: Move common headers to "common/include/soc"Elyes HAOUAS
Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19mb/siemens/chili: Add new mainboardThomas Heijligen
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up. Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19mb/google/octopus/variants/ampton: Add G2Touch touchscreen supportJames Chao
BUG=b:170703029 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-10-19soc/intel/*: drop useless XTAL shutdown qualification codeMichael Niewöhner
The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is ↵Michael Niewöhner
disabled" This reverts commit e5269a8fd975fa0cba0655cd41f7f8cc99a1feb8. Reason for revert: BIOS spec says, it's recommended to always enable emulation (regardless of the OS version). Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19util/abuild/abuild: Do not check out submodulesAngel Pons
This force-downloads the qc_blobs repository, whose license is then automatically accepted. This may also cause race conditions with git. Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45607 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19Documentation: Fix spelling of *assumptions*Paul Menzel
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19sb/intel/ibexpeak: Use ARRAY_SIZE macroAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46529 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19superio/nuvoton: Factor out equivalent Kconfig optionAngel Pons
There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19superio/nuvoton: Correct NCT6791D COM A mux toggleAngel Pons
Bit 6 of global CR 0x2a toggles the mux for COM B. Bit 7 works just like on the other two Nuvoton Super I/Os, so fold the conditionals together. Change-Id: I8cebe35587ae68cac93ed392342662678621efd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19util/supermicro: Always include commonlib/bsd/compiler.hNico Huber
We rely on `compiler.h` for definitions like `__packed`. Without it, `smcbiosinfo.c` simply declared a global struct with that name, but nothing was packed. Found-by: reproducibility test Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19volteer+vendorcode: Retrieve Cr50 version only via SPIJes Klinke
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.hShelley Chen
As ongoing work for generalizing mrc_cache to be used by all platforms, we are pulling it out from fsp 2.0 and renaming it as mrc_cache_hash_tpm.h in security/vboot. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 00:51:47 +0000