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2016-02-18southbridge/intel/bd82x6x/acpi: Fix IRQ warningsPatrick Rudolph
The PCIe slot uses Message Signaled Interrupts (MSI) as the IGD does and doesn't use hardware INT lines. Adding the IRQ entry for PEG slot fixes a warning showing up in GNU/Linux dmesg. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I5ac40e7bea9a659c6c89262aac4552bc8177a9e5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13612 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18cpu/amd: Add socket FM2Damien Zammit
Change-Id: I397c908867fef7583063c8cad7b83ce53482529b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18crossgcc: Change 'tar balls' to 'tarballs'Martin Roth
Change-Id: I8665724c381c204af5bc8bb06117c8af9c32be8a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-18lib: Add Kconfig to toggle boot state debuggingLee Leahy
Add the DEBUG_BOOT_STATE Kconfig value to enable boot state debugging. Update include/bootstate.h and lib/hardwaremain.c to honor this value. Add a dashed line which displays between the states. Testing on Galileo: * select DEBUG_BOOT_STATE in mainboard/intel/galileo/Kconfig * Build and run on Galileo Change-Id: I6e8a0085aa33c8a1394f31c030e67ab3d5bf7299 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13716 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-17power8: try to fix toolchain.inc for power8.Ronald G. Minnich
Change-Id: Ic249ee89d8683b9ecc020d1ec6934019ae5ae1b6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/13724 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-17mainboard/intel/galileo: Enable PCIe root port 0Lee Leahy
Enable PCIe root port 0 Testing on Galileo: * Add a 802.11 wireless card in the mini-PCIe slot * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * After PCI 00:17.0, memory addresses are assigned to the 802.11 wireless card on PCI 01:00.0 during BS_DEV_RESOURCES state Change-Id: I68ea25b8e594480fe5146ffad75e293e346e9517 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13723 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-17mainboard/intel/galileo: Disable the remaining PCI devicesLee Leahy
Add additional lines to the devicetree.cb file to disable the PCI devices in the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-17payloads/external/GRUB2: Add a possibility to add custom modules.Vladimir Serbinenko
Change-Id: I3004eac248561b0cd4e44bcef90fc66fae5d77ca Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13727 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-02-17arch/x86: Add option to disable default mmap_boot implementationAlexandru Gagniuc
On certain platforms, the boot media is either not memory-mapped, or not mapped at the top of 4G. This makes the default mmap_boot implementation unsuitable. Add an option to allow such platforms to define their own mapping implementation. Change-Id: I8293126fd9cc1fd3d75072f7811e659765348e4a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
It looks like the falling timing was missing the shift offset. Not sure if this was intentional, I guess not. Tested on my hardware and produced no regressions. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Please test on real hardware ! Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13682 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-16lint: Make sure site-local isn't committed to coreboot repoMartin Roth
Change-Id: I1dc9469e3d001fe0d5b0517d45679b056586b5b3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-16soc/intel/apollolake: bootblock: implement platform_prog_run()Andrey Petrov
Once bootblock copied romstage into CAR it may not jump into it right away. This is because we are in NEM mode, there is no backing store and a miss in L1 may cause L1D line snoop that gets written back. The solution is to flush L1D to L2 so snoop guaranteed to hit L2. Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-16device/pci_rom: Rename missleading ON_DEVICE_ROM_RUNPatrick Rudolph
The Kconfig option "ON_DEVICE_ROM_RUN" suggests that PCI Option ROMs are run, but in fact it only controls the loading of PCI based Option ROMs. At the moment coreboot only executes Option ROMs if they are VGA Options ROMs and the VGA Option ROM execution flag is enabled. Setting ON_DEVICE_ROM_RUN with VGA Option ROM execution disabled has no effect. Clarify that this flag controls the loading behaviour and not the execution behaviour. Change-Id: Ie3e503cb145f9b7ce613755e60ac0f6c00f2bcdb Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-16southbridge/intel/common: Add common gpio.cPatrick Rudolph
Add a common southbridge gpio code to reduce existing duplicated code. By adding it to ram-stage, GPIOs can be changed any time, without the need of direct register access. The files are based on bd82x6x and lynxpoint gpio.c. Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-15Fix a build problem with power 8: use --with-system-zlibRonald G. Minnich
Power 8 was once again having build issues. Adding --with-system-zlib fixes them. It seems the builtin one is only needed when you are going to build programs, and it falls apart in other cases. Searching --with-system-zlib reveals this to be a very popular topic. This has not broken other toolchain builds (for me); it should not for anyone else. Then again, this is gcc, about which I need say no more. Change-Id: Ica9d057d88982543b5dda471cc949c31fe15932f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/13700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-15skylake: Finalize SMM in corebootDuncan Laurie
Once we lock down the SPI BAR we need to tell SMM to re-init its SPI driver or it will be unable to write ELOG events via SMI. This SMI is also sent at the end of depthcharge so there was just a window where SMI events could get lost. BUG=chrome-os-partner:50076 BRANCH=glados TEST=enable DEBUG_SMI, boot to dev screen, press power button and see elog events get added without without transaction errors. Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326861 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13697 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15skylake: Check for power failure when WAK_STS is not setDuncan Laurie
The PCH does not set PM1_STS[WAK_STS] bit when waking from a G3 state, which is triggered by hibernate now on chell when we do a PMIC shutdown. This means the checks for S5 wake are not done and instead it is logged as a wake from S0. BUG=chrome-os-partner:50076 BRANCH=glados TEST=pass firmware_EventLog test on chell Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783 Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326888 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13696 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15skylake: Enable DDI-A 4-lane support if GOP does not executeDuncan Laurie
This change will allow the kernel to use 4-lane eDP connections if the GOP driver does not execute and set this bit. If GOP has executed (everyone but Chrome OS verified mode) the link will already be up and this will do nothing. BUG=chrome-os-partner:50197 BRANCH=glados TEST=boot on chell and ensure 4 Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844 Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/327251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13690 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15skylake: acpi: Make GRXS method serializedDuncan Laurie
This method creates a named object and should be serialized to avoid a compiler warning from recent iasl releases. BUG=chrome-os-partner:40635 BRANCH=glados TEST=emerge-chell coreboot with no iasl warnings Change-Id: If54df4eca8849a8d278816712164b30a775a41ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9aa8c5627276be08bf0dc3d0f4b9b7bd3f40c227 Original-Change-Id: Ieb05525503bf61c9922677484aba5479856a3f35 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326843 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13689 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15kconfig: make oldconfig work "non-strict"Patrick Georgi
oldconfig is regularly used to clean up templates that sometimes contain duplicates or old symbols. Since it cleans up the config, it doesn't need to fail on issues. Change-Id: Ife0e9e3b9bfdde1eb6be0e2e38e81b9042cb7950 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-14Intel common: add microcode loading to romstage before fspmemoryinitrobbie zhang
The intend is to seek upgraded microcode in RW section and load it before Fsp memoryinit, to ensure any goodness in the microcode update, especially related to memory configuration, can be applied earlier. BUG=chrome-os-partner:50132 BRANCH=glados TEST=Built and boot on kunimintus. Verified microcode gets reloaded. Boot time impact is very minor. CQ-DEPEND=CL:327170 Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086 Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327193 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13688 Tested-by: build bot (Jenkins) Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-02-14cpu/amd: Update/Add license headersDamien Roth
These license headers were either not compliant with the coreboot standard or were missing completely. Change-Id: I0c46ad9ba7f3d950b3eff96ee6e9c36acbf1a3a5 Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13288 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14CPU/intel: Add missing license headersDamien Roth
Add missing license headers to files that have no coreboot header. Change-Id: Iaaa04b5dcbd446a2064ac68d501ae8e860486e36 Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13289 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13FMAP: Clean up debug outputDuncan Laurie
Reduce the debug output from FMAP lookups. When we had one or two FMAP lookups in a boot this was not a big deal, but now that we do many lookups it is a lot of unnecessary output duplication. This change reduces these 3 lines: FMAP: area VBLOCK_A found FMAP: offset: 200000 FMAP: size: 65536 bytes To just one line: FMAP: area VBLOCK_A found @ 200000 (65536 bytes) And makes the header output only print once: FMAP: Found "FMAP" version 1.0 at c10000. FMAP: base = 0 size = 1000000 #areas = 29 BUG=chrome-os-partner:40635 BRANCH=glados TEST=boot on chell and enjoy non-truncated memconsole Change-Id: Ib5862b8bfad113a700faae89089557094aa6d499 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6890f36536d4ae6fc4988fc8191b0cff4e33e2e6 Original-Change-Id: Ifefee1ab26e6ee406de552880fbbd5b7916fcadd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326887 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13695 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13cpu/allwinner: Update license headersDamien Roth
These licence headers were not compliant with the coreboot standard. Change-Id: I85bb5f971ab1f8ac3e9589f712370fbf09716b67 Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13287 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13crossgcc: Use acpica-unix2 over acpica-unixPatrick Georgi
Apparently acpica-unix is shipped under "A non-open source license (the 'Intel license')" while acpica-unix2 comes under GPLv2/BSD dual license. (see https://acpica.org/Licensing) So go with unix2. Change-Id: I412812187bbf488eb4ad6d7fb8d2840f2f5e06d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13686 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
Otherwise the image is simply unusable. Change-Id: I1e2562ba17279d14dc73b05e4f8fa493e06fbcd2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13699 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-13soc/intel/apollolake: add assert for pad constraintsAaron Durbin
Ensure the pads passed into the gpio functions are within range. Change-Id: Ic523cbfaf60a46709080347af3a36d6330f9a07c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13694 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13soc/intel/apollolake: pre-evaluate gpio number valuesAaron Durbin
To allow sharing macros in ASL as well as C the macros can't have complex expression because the ASL compiler does not evaluate those expressions. To that end, just pre-calculate the values. Lastly, add N_OFFSET and utilize it for symmetry. Change-Id: I546d71008e776b27ce8bcd24d2cbd2ee1b2d8020 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13693 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13soc/intel/apollolake: limit bootblock size to 32KiBAaron Durbin
The CSE places the bootblock (IBBL in Intel parlance) below 4GiB at top of the address space. However, it's size is limited to 32KiB. For now, just limit all of bootblock to 32KiB. Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13692 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13x86: make bootblock size for C_ENVIRONMENT_BOOTBLOCK configurableAaron Durbin
Certain platforms may need to limit their bootblock size to within a given size because specific constraints. Allow the size to be provided by the mainboard or chipset by way of the arch Kconfig being processed after those. Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13691 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-12ktqm77: Support native raminitVladimir Serbinenko
Change-Id: Ic90d3aa714e5681c5021e2b05275d57dce428de0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13664 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12lzma: Port size-checking ulzman() version to corebootJulius Werner
We've had a second version of ulzma() that would check the input and output buffer sizes in libpayload for a while now. Since it's generally never a bad idea to double-check for overruns, let's port it to coreboot and use it where applicable. (This requires a small fix in the four byte at a time read optimization we only have in coreboot, since it made the stream counter hit the end a little earlier than the algorithm liked and could trigger an assertion.) BRANCH=None BUG=None TEST=Booted Oak, Jerry and Falco. Change-Id: Id566b31dfa896ea1b991badf5a6ad9d075aef987 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-12tegra132/pistachio: Increase romstage size in memlayout.ldJulius Werner
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from Tegra210, because why not? Keeps things simple.) BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara. Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12tegra132/210: Remove memlayout_vboot2.ldJulius Werner
Having two separate memlayouts is an unnecessary complication. Contributors need to make sure that their code fits into the vboot one (with smaller stage sizes) either way, and the Tegras have plenty of SRAM anyway. Let's just make the vboot layout the default (as it was done on other SoCs) to keep things easier to maintain. The empty SRAM holes on non-vboot systems where the verstage and work buffer would've been won't hurt them. BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and Smaug. Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION KconfigJulius Werner
This patch generalizes the approach previously used for ARM32 TTB_SUBTABLES to "auto-detect" whether a certain region was defined in memlayout.ld. This allows us to get rid of the explicit Kconfig for the TIMESTAMP region, reducing configuration redundancy and avoiding confusion when setting up future boards. (Removing armv4/bootblock_simple.c because it references this Kconfig and it is a dead file that I just forgot to remove in CL:12076.) BRANCH=None BUG=None TEST=Booted Oak and confirmed that all pre-RAM timestamps are still there. Built Nyan and Falco. Change-Id: I557a4b263018511d17baa4177963130a97ea310a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-12samsung/*umpy: fix Kconfig formattingPatrick Georgi
Some spaces crept in where there should be tabs. Change-Id: Ie70469f5a16e8a2d5933ac632d13551b19761064 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13698 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-12util/cbfstool: Improve heuristic for cbfs header pointer protectionPatrick Georgi
cbfstool has a routine to deal with old images that may encourage it to overwrite the master header. That routine is triggered for "cbfstool add-master-header" prepared images even though these are not at risk, and - worse - destroys the chain structure (through a negative file length), so avoid touching such images. Change-Id: I9d0bbe3e6300b9b9f3e50347737d1850f83ddad8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13672 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12lumpy: Support native raminitVladimir Serbinenko
Change-Id: Id695fb6e759b90cd91bb9760bb4fe2a459480b21 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13663 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12stumpy: Add native raminit supportVladimir Serbinenko
Change-Id: Ibbb056ae209a16533757af925c8c833c94803834 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13662 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12link: Support native raminitVladimir Serbinenko
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13665 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12emeraldlake2: Support native raminit.Vladimir Serbinenko
Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13666 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-12butterfly: Make configurable MRC vs non-MRC.Vladimir Serbinenko
Change-Id: I7b1e046d5895750d350dfa851a6f51c3a3a1613f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13659 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-02-12stout: Support native raminitVladimir Serbinenko
Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13660 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12util/kconfig: Ignore extra symbols in configs instead of failingMartin Roth
When updating an old .config file that has a symbol that has been removed from the current Kconfig tree, kconfig will generate a warning and fail to save the updated file. This is incredibly annoying, and not the goal when trying to eliminate Kconfig warnings. Instead of generating a warning, just print a message that it's being ignored. This will remove the offending symbol, while allowing the updated config file to be saved. Split the change from 1 line to 3 lines to keep it at 80 characters. Change-Id: I09d5775c9ed14bde80077b51b862a7f41bee098a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12mainboards: Drop remaining references to vboot indexesPatrick Georgi
Those aren't used anymore. Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13685 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12Fix butterfly usb map.Vladimir Serbinenko
This was copied from mrc structure despite them having fields in different order. Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13661 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12bimgtool: Fix printf warning for off_tStefan Reinauer
off_t wants to be printed with %zd, not %d. Change-Id: I3f6e1988bb306f4a7738f1f3ccb2093518e4ceb3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13655 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12bimgtool: Match CRC code guardsStefan Reinauer
Make sure that the statically defined CRC functions are enabled by the same conditionals as the code using them. Change-Id: Ic24e2ed1a80b8e5f6623881b08d86f7b608a206e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13654 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12bimgtool: Drop unused targets and variables from MakefileStefan Reinauer
dep has not been defined (and will hence break the build) LDFLAGS is not used. Change-Id: I4f91e1e7a176367aa4e1a1c63a2afc0b3186767e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13653 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12Move gpio.h to gpio.c on sandy and ivy.Vladimir Serbinenko
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13657 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11arches: lib: add main_decl.h for main() declarationAaron Durbin
It is silly to have a single header to declare the main() symbol, however some of the arches provided it while lib/bootblock.c relied on the arch headers to declare it. Just move the declaration into its own header file and utilize it. Change-Id: I743b4c286956ae047c17fe46241b699feca73628 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13681 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-11arch/{arm64,riscv}: remove jmp_to_elf_entry() declarationAaron Durbin
jmp_to_elf_entry() is not defined anywhere. Remove it. Change-Id: I68f996a735f2ef3dd60cf69f9b72c3f1481cbb55 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11lib/prog_loaders.c: remove arch/stages.h includeAaron Durbin
There's no delcaration used. Remove the include. Change-Id: I6fa7de6362ca0e92f0d5a7d07f3a224b9f77f709 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11arch: remove stage_exit()Aaron Durbin
It's no longer used. Remove it. Change-Id: Id6f4084ab9d671e94f0eee76bf36fad9a174ef14 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11timestamp: Bump CBMEM timestamp count, make full use of pre-RAM regionsJulius Werner
Since we're reaching the timestamp limit on certain platforms (both for the pre-RAM cache and the final CBMEM region), this patch increases the amount of space for both. In the pre-RAM case, it achieves this by always utilizing the full size of the TIMESTAMP() region allocated in memlayout.ld, rather than arbitrarily limiting it to some constant. BRANCH=None BUG=None TEST=Booted Oak and confirmed that I can once again see all pre-RAM timestamps after picking in the LZ4 patch series. Change-Id: Iabb075a48d8d1e3e1811afeaad5ab47e7846c972 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13651 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLEAndrey Petrov
Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add minimal GPIO driverAndrey Petrov
This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-11mainboard/intel: Add skeleton for Apollolake RVP board familyAlexandru Gagniuc
RVP1 board comes with DDR3 SODIMMs and discrete VRs. RVP2 board uses LPDDR3 and PMIC. Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11soc/apollolake: Add initial cache-as-ram setup for bootblockAlexandru Gagniuc
This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11git modules: rename git submodules to avoid hierarchiesPatrick Georgi
Having a git module named "3rdparty" and another one in "3rdparty/chrome-ec" led to git failures when the latter was initialized before the former (because of git being stupid, but then it says so on the box, right?) Rename modules so there's no such hierarchy (3rdparty -> 3rdparty/blobs). While at it, also rename the culprit to match the path name (3rdparty/chrome-ec to 3rdparty/chromeec). git will resolve this on the next git submodule update invocation (eg. the next coreboot build). Change-Id: Ief79074d73abeefff36a47b2e58ac6b1c047e3a7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/13675 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-02-113rdparty/chromeec: fix build with paths containing "@"Patrick Georgi
Move submodule forward to a newer upstream master to fix the build on paths containing "@", as can happen on jenkins. Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13673 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11cpu/x86/tsc: Compile delay_tsc.c for the bootblock as wellAlexandru Gagniuc
This is needed in a follow-on patch to enable udelay() handling on apollolake, which is a dependency for the console code. Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11util/marvell: Add Marvell doimage utility and dependency in relevant MakefileRuilin Hao
- Add the doimage sources in util/marvell - Add dependency in root makefile - Add dependency in makefile for armada38x soc BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9 Original-Signed-off-by: Kefei Yao <kfyao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/318046 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-11arch/x86: Change how BOOTBLOCK_CUSTOM is selected by defaultAndrey Petrov
Currently x86s select BOOTBLOCK_CUSTOM by default. With this change BOOTBLOCK_CUSTOM is selected only if C bootblock isn't. Change-Id: I218f3b4044175b89697790c82c384b0f85a27ade Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13642 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11arch/x86: Allow bootblock code to use CAR_GLOBAL variablesAndrey Petrov
Since cbmem is not initialized in bootblock, CAR_GLOBAL variables can only be accessed directly similar to verstage. Change-Id: Ifc705016290807c49dc8c49b581864cac2ad3f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11arch/x86: Reserve space for stack in CAR layoutAndrey Petrov
Some platforms may want to use C code in bootblock so they need writable memory and CAR can be used for it. This change reserves memory in CAR that can be used by bootblock and other CAR stages. Change-Id: I8dec768cf8763dbe235f0ba1339079ebc49cbd9a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
The previous usage of the intel microcode support supported using the library under ROMCC and ramstage. Allow for microcode support to be used in normal C-based romstage as well by: 1. Only using walkcbfs when ROMCC is defined. 2. Only using spinlocks if !__PRE_RAM__ The header file now unconditionally exposes the declarations of the supporting functions. Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10kconfig_lint: update kconfig lint shell scriptsMartin Roth
- Add lint-stable script with just error checking - Enable warnings in addition to errors in non-stable test. - Use git grep if the code is in a git repo now that exclusions are working. - Check for perl, and ask the user to install it if it isn't available. Change-Id: Ie60d21f4ef8a61d879f116eb2056eb805b0a55f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13542 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-10chromeos/Kconfig: Remove dependency on GBB_HAVE_BMPFVMartin Roth
This symbol is not defined. Change-Id: I2b0a3fca82d85962fc882f237b70702cab0400db Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/13647 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
We want the question for CBFS size to be next to the rom size in the mainboard directory, but that doesn't seem to work for how people want to set the defaults. Instead of having the list of exceptions to the size, just set the defaults at the end of kconfig. - Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into the chipset Kconfigs (gm45, nehalem, sandybridge, x4x) - Override the default for HAVE_INTEL_FIRMWARE on skylake. - Move the HAVE_INTEL_FIRMWARE default setting into the firmware Kconfig file - Move the location of the default CBFS_SIZE=ROM_SIZE to the end of the top level kconfig file, while leaving the question where it is. Test=rebuild Kconfig files before and after the change, verify that they are how they were intended to be. Note: the Skylake boards actually changed value, because they were picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the 0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after the HAVE_INTEL_FIRMWARE default. Affected boards were: Google chell, glados, & lars and Intel kunimitsu. Change-Id: I2963a7a7eab037955558d401f5573533674a664f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10intel/fsp1_0: Allow the MRC cache to live in a FMAP regionBen Gardner
The new option CONFIG_MRC_CACHE_FMAP will cause fastboot_cache.c to look in the FMAP for a region named "RW_MRC_CACHE" and prevents adding a CBFS file named "mrc.cache". Tested on a fsp_baytail-based board. Change-Id: I248f469c7e3447ac4ec7be32229fbb5584cfd2ed Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10google/veyron_speedy: remove extraneous filePatrick Georgi
veyron_speedy was deduplicated as sub-board into google/veyron, so the addition of chromeos.fmd (identical btw) wasn't useful. Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10google/chromeos: backup -> back upPatrick Georgi
See discussion on https://review.coreboot.org/13600 and https://review.coreboot.org/13601 Change-Id: Ia8274b0b296d6b398f75c0d91a6fded4c5f57e10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13643 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10gitconfig: Fix make gitconfig if USE_BLOBS is disabledPatrick Georgi
We tested for the presence of .git/modules/3rdparty, which always exists now because of .git/modules/3rdparty/chrome-ec. Test for .../hooks instead since that's the actual location for the later activities. Change-Id: Id5de9f850413c2bc3525faa6cc549641304c3d47 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/13650 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10buildgcc: enable multilib for gccPatrick Georgi
Make the gcc build system create multiple libgcc.a instances for different ABIs. Change-Id: I1c888bf751bf43566da8927ed0aedb53857363bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13625 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10arch/arm64: Use correct SPSR.DAIF mask for BL31 and payloadJulius Werner
The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts and Fast interrupts are usually best left unset: under normal circumstances none of those exceptions should occur in firmware, and if they do it's better to get a crash close to the code that caused it (rather than much later when the kernel first unmasks them). For this reason arm64_cpu_init unmasks them right after boot. However, the EL2 payload was still running with all mask bits set, which this patch fixes. BL31, on the other hand, explicitly wants to be entered with all masks set (see calling convention in docs/firmware-design.md), which we had previously not been doing. It doesn't seem to make a difference at the moment, but since it's explicitly specified we should probably comply. BRANCH=None BUG=None TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask bits are now cleared. Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8 Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/325056 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10arch/arm64: mmu: Spot check TTB memory attributesJulius Werner
On ARM64, the memory type for accessing page table descriptors during address translation is governed by the Translation Control Register (TCR). When the MMU code accesses the same descriptors to change page mappings, it uses the standard memory type rules (defined by the page table descriptor for the page that contains that table, or 'device' if the MMU is off). Accessing the same memory with different memory types can lead to all kinds of fun and hard to debug effects. In particular, if the TCR says "cacheable" and the page tables say "uncacheable", page table walks will pull stale entries into the cache and later mmu_config_range() calls will write directly to memory, bypassing those cache lines. This means the translations will not get updated even after a TLB flush, and later cache flushes/evictions may write the stale entries back to memory. Since page table configuration is currently always done from SoC code, we can't generally ensure that the TTB is always mapped as cacheable. We can however save developers of future SoCs a lot of headaches and time by spot checking the attributes when the MMU gets enabled, as this patch does. BRANCH=None BUG=None TEST=Booted Oak. Manually tested get_pte() with a few addresses. Change-Id: I3afd29dece848c4b5f759ce2f00ca2b7433374da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f3947f4bb0abf4466006d5e3a962bbcb8919b12d Original-Change-Id: I1008883e5ed4cc37d30cae5777a60287d3d01af0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323862 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13595 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10soc/intel/quark: Report CPU infoLee Leahy
Decode the CPU variants and display the CPU info. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Successful if Quark X1000 is displayed Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13605 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/intel/quark: Call FSP SiliconInitLee Leahy
Optionally relocate FSP into DRAM and then call FSP SiliconInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_FSP_ENTRY_POINTS" * Add "select DISPLAY_HOBS" * Optionally add "select RELOCATE_FSP_INTO_DRAM" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * FSP entry points are displayed and * The message "FspSiliconInit returned 0x00000000" is displayed and * The HOBs are displayed correctly and * The message "ERROR - Missing one or more required FSP HOBs!" is not displayed Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13631 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10soc/intel/quark: MTRR supportLee Leahy
Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/fsp_baytrail: Add support for FSP MR 005Ben Gardner
Baytrail FSP MR 005 adds two new fields: AutoSelfRefreshEnable APTaskTimeoutCnt Add the device tree definitions. Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12973 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10soc/intel/quark: FSP MemoryInit SupportLee Leahy
Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13447 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09ASL: Remove unused modulo recipient.Vladimir Serbinenko
Change-Id: I4b0a3073815ec8d98c2d23cd745f027517b6fa42 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13619 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09stout: Add native gfx initVladimir Serbinenko
Tested during FOSDEM. Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13532 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
In the same time remove few native gfx options which were improperly set and only added dead code to the binary. Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13649 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-09SeaBIOS: Disable serial console if serial is memory mappedMartin Roth
SeaBIOS only supports standard IO based serial ports. If the serial port being used by coreboot isn't a standard IO serial port, disable the serial console in the SeaBIOS build. Change-Id: I386b46625fca0bd0a5416ed9831f8370c294ed74 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13617 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09libpayload: use 32bit access when accessing 4byte wide uart registersPatrick Georgi
This fixes serial on rk3288. Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13636 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-09rockchip/rk3288: UART uses 32bit wide registersPatrick Georgi
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13635 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09kconfig_lint: demote 'always defined' errors to warningsMartin Roth
To be able to run this as a lint-stable test, demote these to warnings for now. After the current CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL issues get fixed, these can be promoted again. Change-Id: I1432980eb0c871fc61c12dcc351f8d46513a7965 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13541 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09vboot2: Store depthcharge graphic assets only in ROPatrick Georgi
These files aren't updated (or updatable), and as such don't need to be copied to the RW sections. Change-Id: Ie78936792ad651fbf8500fc7e34f0899e33a904c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09kconfig_lint: Check for IS_ENABLED used on symbols without CONFIG_Martin Roth
This looks at the coreboot codebase for the IS_ENABLED macro, and gives an error if there is a symbol used without the CONFIG_ prefix. This only works for symbols of type bool. A future check will be added for all symbols, but that will take a significant amount of time to run, because each symbol will need to be searched for individually. Change-Id: I92f2de2d231610d1a788da965f21966d89c2f25c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13538 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
This is needed for stout EC init. Change-Id: I5c73499c17763229840152a473a2d820802ee2f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13535 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09superio/nuvoton/nct5572d: Add PS/2 presence detectPaul Menzel
On certain Super I/O devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse presence detect). Update the Nuvoton NCT5572D driver to flag the auxiliary channel as disabled if no device was detected. The code is copied from the Winbond W83667HG-A driver. Note, the ACPI changes are not part of this commit. TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this change, a PS/2 keyboard works fine in SeaBIOS, GRUB in MBR, and Debian GNU/Linux Sid/unstable with Linux 3.19. ``` [ 1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly. [ 1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.189970] mousedev: PS/2 mouse device common for all mice ``` Change-Id: I7f9be348d295e70437bef089d4c2173169f38459 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/13618 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09Kconfig: Move payloads section to payloads/KconfigMartin Roth
Move the payloads section of the kconfig tree out of the top level kconfig file and into a separate Kconfig just for payloads before it starts to get added to. Change-Id: I4f52818f862bf1aeba538c1c6ed93211a78b9853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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