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2021-03-18cpu/x86/mp_init.c: Calculate perm_smbase from ramstage dataArthur Heymans
The data needed to compute the permanent smbase for a core, when relocating, is present in the ramstage data which the stub located at DEFAULT_SMBASE (0x30000) calls back to. There is no need to fetch this from via the stub params. Change-Id: I3894c39ec8cae3ecc46b469a0fdddcad2a8f26c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/smm: Move apic_id_to_cpu map to smm_stub paramsArthur Heymans
This is only consumed by the stub and not by the relocation handler or the permanent handler, so move it out of the runtime struct. Change-Id: I01ed0a412c23c8a82d88408be058a27e55d0dc4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-18cpu/x86/smm_stub.S: Drop unused module_handler parameterArthur Heymans
Change-Id: I15b433483c36cce04816e8895789997d91702484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-18cpu/x86/smm: Move relocatable stub paramsArthur Heymans
These stub params need to be synced with the code in smm_stub.S and are consumed by both the smmloader and smmloader_v2. So it is better to have the definition located in one place. Change-Id: Ide3e0cb6dea3359fa9ae660eab627499832817c9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50761 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/qemu-x86: Add an option to use the smmloader v2Arthur Heymans
The idea is to get rid of having 2 different smmloaders so add this option only to qemu/q35 to get it buildtested. Change-Id: Id4901784c4044e945b7f258b3acdc8d549665f3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51525 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP initArthur Heymans
Tested with and without -enable-kvm, with -smp 1 2 and 32. Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48262 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18soc/intel/block/cpu/mp_init.c: Remove weak functionsArthur Heymans
All platforms implement those and using a no-op function is not expected, so it is better to fail the build if the soc specific code is not implemented. Change-Id: Id946f5b279dcfa6946381b9a67faba6b8c1ca332 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51522 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridgesRaul E Rangel
We are currently writing invalid ACPI tables. We are missing the GPP ACPI names. There is an assert in acpi_device_write_pci_dev that checks to see if we have a scope, but by default asserts don't halt, so we were writing a NULL scope. BUG=b:171234996 TEST=Boot majolica and dump ACPI tables Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6a861ad1b9259ac3b79af76e18a9354997b0491e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-17Documentation: Describe the site-local hook in our config/build systemPatrick Georgi
Change-Id: Ia682b784540fa82e1f216f76d87d59a4f0b94486 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51546 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()Julius Werner
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17amd: refcode_loader: Switch to new CBFS APIJulius Werner
This patch rewrites some parts of the Agesa refcode loader to eliminate the passing of raw rdevs between functions, so that we can get rid of cbfs_boot_locate() in favor of more high-level APIs. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2a6e1158ed7425c69c214462bc52e8694a69997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Move stage header into a CBFS attributeJulius Werner
The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17program_loading: Replace prog_rdev() with raw start pointer and sizeJulius Werner
Since prog_locate() was eliminated, prog_rdev() only ever represents the loaded program in memory now. Using the rdev API for this is unnecessary if we know that the "device" is always just memory. This patch changes it to be represented by a simple pointer and size. Since some code still really wants this to be an rdev, introduce a prog_chain_rdev() helper to translate back to that if necessary. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17Makefile.inc: Don't compile bare structs with asan-global=1Arthur Heymans
This messes up the bare structs. Change-Id: I5a13bd9f4b11530a6dd5f572059fed851db44757 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-17mb/google/kukui: Add new config 'cozmo'Lucas Chen
New board 'cozmo'. BUG=b:181144502 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-17mb/google/dedede/var/sasukette: Enable ALC1015 AMP (Auto Mode) driverwuweimin
Enable gpio mode driver for ALC1015 AMP Auto Mode. BUG=b:176956779 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: Iaa5650e120362e81fa36530f6a207c9c07e1139a Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17ipmi/ocp: Remove duplicate IPMI OEM command set processor informationJingleHsuWiwynn
IPMI OEM command set processor information has already been implemented in u-root payload: https://github.com/u-root/u-root/commit/efdc3a30ecca53e8b50b863969173969127fa384 Also this command has a higher chance to see BMC KCS timeout issue when coreboot log level is 4, which can be avoided if this command is run at a later stage such as LinuxBoot. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: If0081e5195cbd605e062723c197ac74343f79a13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51276 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstageSridhar Siricilla
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync() must be called after DRAM initialization. Test=Verified on Alderlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17mb/google/dedede/var/lantis: Update DPTF parametersTony Huang
DPTF paramerters from thermal team. 1. PL2 =15W 2. Add TSR sensor charger, 5V regulator BUG=b:177249297 BRANCH=dedede TEST=build image and verified by thermal team. Change-Id: Ia5f6cc2a4564bb5558cbaca8daf31ee70145019f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17mb/intel/shadowmountain: Update HDMI audio mode to 8TSugnan Prabhu S
This patch sets the HDMI audio mode to 8T as required by the latest FSP version v2081_02 TEST: HDMI audio codecs detection is failing without this change. Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17mb/intel/shadowmountain: Disable xDCISugnan Prabhu S
This patch disables the xDCI which is causing PC8 to PC10 state transitions during sleep. TEST: Confirmed that the transition is happening with this change. Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-17Documentation: Add deprecation notice for SAR support in VPDFurquan Shaikh
This change updates the release notes for coreboot-4.14 to add deprecation notice for SAR support in VPD for Chrome OS platforms. BUG=b:173465272 Change-Id: If6d511a22a3a2a31671dac91e57e801134d4ecf8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51486 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17sar: Fix semantics of `get_wifi_sar_cbfs_filename()`Furquan Shaikh
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then `get_wifi_sar_limits()` assumes that the default filename is used for CBFS SAR file. This prevents a board from supporting different models using the same firmware -- some which require SAR support and some which don't. This change updates the logic in `get_wifi_sar_limits()` to return early if filename is not provided by the mainboard. In order to maintain the same logic as before, current mainboards are updated to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default case. Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17drivers/wifi, mb/google: Drop config `WIFI_SAR_CBFS`Furquan Shaikh
Now that SAR support in VPD is deprecated in coreboot, there is no need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS` from drivers/wifi/generic/Kconfig and its selection in mb/google/.../Kconfig. wifi_sar_defaults.hex is added to CBFS only if CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards do not provide a default SAR file in coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a default value of "". BUG=b:173465272 Cq-Depend: chromium:2757781 Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17vc/google/chromeos: Deprecate support for SAR tables in VPDFurquan Shaikh
SAR table in VPD has been deprecated for Chrome OS platforms for > 1 year now. All new Chrome OS platforms have switched to using SAR tables from CBFS. This change drops the support for SAR table in VPD from coreboot to align with the factory changes. `get_wifi_sar_limits()` is thus updated to look for SAR file in CBFS only. Anyone building ToT coreboot for an already released Chrome OS platform with SAR table in VPD will have to extract the "wifi_sar" key from VPD and add it as a file to CBFS using following steps: - On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar` - In coreboot repo, generate CBFS SAR file using: `echo ${SAR_STRING} > site-local/${BOARD}-sar.hex` - Add to site-local/Kconfig: ``` config WIFI_SAR_CBFS_FILEPATH string default "site-local/${BOARD}-sar.hex" ``` BUG=b:173465272 Change-Id: I21d190dcc9f3554fab6e21b4498e7588a32bb1f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17vendorcode/mt8192: devapc: fix register offset for PCIe domainNina Wu
Correct the wrong offset for setting PCIe domain. Change-Id: I9de2bdf5a0a4fb5b34985b11976fd50b397e97ba Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51512 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17prog_loaders: Remove prog_locate()Julius Werner
This patch rewrites the last few users of prog_locate() to access CBFS APIs directly and removes the call. This eliminates the double-meaning of prog_rdev() (referring to both the boot medium where the program is stored before loading, and the memory area where it is loaded after) and makes sure that programs are always located and loaded in a single operation. This makes CBFS verification easier to implement and secure because it avoids leaking a raw rdev of unverified data outside the CBFS core code. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7a5525f66e1d5f3a632e8f6f0ed9e116e3cebfcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/49337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Remove prog_locate() for payloads (SELF and FIT)Julius Werner
This patch removes the prog_locate() call for all instances of loading payload formats (SELF and FIT), as the previous patch did for stages. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I582b37f36fe6f9f26975490a823e85b130ba49a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16cbfstool: Move alignment/baseaddress handling into cbfs_add_component()Julius Werner
The --alignment flag is currently only handled by cbfstool add, but there seems little reason to not handle it for all file-adding commands (the help text actually mentions it for add-stage as well but it doesn't currently work there). This patch moves the related code (and the related baseaddress handling) into cbfs_add_component(). As a nice side effect this allows us to rearrange cbfs_add_component() such that we can conclusively determine whether we need a hash attribute before trying to align the file, allowing that code to correctly infer the final header size even when a hash attribute was implicitly added (for an image built with CBFS verification enabled). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idc6d68b2c7f30e5d136433adb3aec5a87053f992 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47823 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Drop invalid MP table filesKyösti Mälkki
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Move IRQ table programmingKyösti Mälkki
IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16util/cbfstool/ifittool: Remove dead codeArthur Heymans
The 'x' option is not set up in the getopt options. Change-Id: Ib4aa10b0ea2a3f97e8d2439152b708613bcf43db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-16mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I4d5160ff23d2bd386cb33164b580e6d6f3bf30fd Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16vendorcode/mt8192: change to short log macro namesXi Chen
Originally, log macro names are too long, and they use double parentheses style: ((...)), which causes compile or runtime error easily. Now, change them to single parenthesis mode (...), and use shorter name. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2959dc1ba0dd40a8fb954406072f31cf14c26667 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"Daolong Zhu
The i2c actiming with the default reg setting cannot meet spec, so we need to set some regs. 1. adjust the ratio of SCL high and low level, to adjust "tLOW". 2. modify ext_conf reg to adjust "tSU,STO". BUG=b:179000159 TEST=Test on asurada (MT8192), boot pass, timing pass. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16Update chromeec submodule to upstream masterMartin Roth
Updating from commit id a2390f3c5: 2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set) to commit id 1e800ac83: 2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD) This brings in 188 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c276d7839e0bdbf14ac56f16c231d75a6ea4c3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-16Update arm-trusted-firmware submodule to upstream masterMartin Roth
Updating from commit id a4c979ade: 2020-08-26 14:59:05 +0000 - (Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration) to commit id 7ad39818b: 2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration) This brings in 222 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id186df36d90563f94f17cc210a6f634adc4ec61e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-16mb/google/dedede/var/blipper: Add camera supportZanxi Chen
Add camera support in devicetree and associated GPIO configuration. BUG=b:181729304 BRANCH=dedede TEST=built blipper firmware and verified camera function is OK Change-Id: I806ec207a454d4383aca093159553b7e618e16b2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add codec and speaker amplifier supportZanxi Chen
Add audio codec and speaker amplifier support into devicetree BUG=b:181732574 BRANCH=dedede TEST=built blipper firmware and verified audio function is OK Change-Id: Id4633649b5e0595ed99a40ae35eb54b005154604 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Enable touchscreen for blipperZanxi Chen
Add G2 and ELAN touchscreen into devicetree for blipper. BUG=b:181098785 BRANCH=dedede TEST=built blipper firmware and verified touchscreen function is ok Change-Id: Ie0bfc2972fc1a33a6f02495d3976b816209e956b Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGHSeunghwan Kim
Configuring GPP_B7 as GPO_HIGH. Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module and is kept high so that the LTE module uses the default emission power. BUG=b:180492044 BRANCH=firmware-dedede-13606.B TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16vendorcode/mt8192: fix fast-k gating PI P1 initializationXi Chen
In RX Gating flow, PI P1 delay is missing, so re-add the initialization. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16vendorcode/mt8192: limit fast-k frequency count from 7 to 3Xi Chen
For bootup faster, fast-k elapsed time is improved by ~400ms. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ifa945012aa66df4433fe63aab75a1e785d343d9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51406 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/asurada: fix boot failure when reading SKU IDHung-Te Lin
The SKU IDs also need mapping table when reading voltages. BUG=None BRANCH=asurada TEST=emerge-asurada coreboot Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/magolor: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in magolor. With the format the DPTF policies are defined in magolor, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/google/dedede/var/madoo: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in madoo. With the format the DPTF policies are defined in madoo, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=b:182513022 BRANCH=dedede TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-FAlexander Couzens
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORTPatrick Rudolph
Already selected by SoC. Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-15mb/google/dedede/var/sasukette: Add USB2 PHY parametersTao Xia
This change adds fine-tuned USB2 PHY parameters for sasukette. BUG=180753635 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15soc/intel/alderlake: Drop 100ms delay and do not poll Link ActiveJohn Zhao
Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with ↵Kevin Chang
wrong date code MB Disable SA GV, because factory used Samsung memory with wrong date code. So we need to use board version to identify build MB phase to disable SA GV. Disable SA GV when board version equal one. BUG=b:179747696 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15vc/intel/fsp/fsp2_0/cooperlake_sp: Update memory map hob for WW06 FSPJohnny Lin
Change-Id: Id534e1b73e73bbb9d944c988d1ef66bc1f463eff Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50867 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/tglrvp: Enable RTD3 for WWANBora Guvendik
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 4 and provide the reset GPIO / src clk pin. BUG=none TEST=Boot to OS, verify the link is in L2 state during S0ix. Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15mb/google/dedede/var/storo: Support LTE modulechenzanxi
Add LTE module support into devicetree and associated GPIO configuartion. BUG=b:177955524 BRANCH=dedede TEST=LTE function is OK Change-Id: I9aff9608e08eae00ab5ac8547f63bc83b62fea78 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15mb/google/dedede/var/storo:Add P-sensor for storochenzanxi
Add P-sensor into devicetree for storo according to configuration information provided by the vendor. BUG=b:177392203 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Iced4ab7d94b38ef8b1807955cbb887454accb1e8 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-15mb/google/dedede/var/storo: Add codec and speaker amplifier supportchenzanxi
Add audio codec and speaker amplifier support into devicetree BUG=b:179057895 BRANCH=dedede TEST=audio function is OK Change-Id: Ia864ac47223adb80463966209f6ff3640b715378 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51003 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/storo: Add camera supportchenzanxi
To support mipi camera. 1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM1 into devicetree To support usb camera. add camera support in devicetree and associated GPIO configuration. BUG=b:177393430, b:177388006 TEST=Build and boot to OS. Camera function is OK. Change-Id: I98d5708d1955406c2e46db972903057bb3d12dcc Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50995 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/lenovo/t440p: update VBT to version 2179Da Lao
Update T440p's VBT from version 1215 to version 2179. Extracted using VBiosFinder (https://github.com/coderobe/VBiosFinder) from the latest bios update file: https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso The new version solves the problem that DP output was broken under Windows. Test: boot t440p with both SeaBIOS and Tianocore payloads, verify dp output and backlight control all works under both Linux and Windows. Signed-off-by: Da Lao <dalao@tutanota.com> Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen>
2021-03-15security/intel/stm/Makefile.inc: Fix typoBenjamin Doron
In both the Kconfig and Makefile in this directory, "STM_TTYS0_BASE" is used. Therefore, fix the typo. Change-Id: Ie83ec31c7bb0f6805c0225ee7405e137a666a5d3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51206 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang
There is no PCI host interface for this version of CNVi BT. CNVi BT on Tigerlake is an USB device. Change-Id: Ib71a827c36dfac55c3e5ce586b00a26fc6264464 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50900 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT ↵Cliff Huang
flag Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/hatch: Update DPTF parameters for genesisKenneth Chan
update the DPTF parameters received from the thermal team. BUG=b:181627614 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joe Tessler <jrt@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang
There is no PCI host interface for Cnvi BT in Alderlake. CNVi BT on Alderlake is an USB device. Change-Id: I3e08c6d6f00e81267dc28c9b37b2dfff5cd75db1 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51352 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/brya: Remove BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi Bt PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
This change adds the corresponding CNVi BT Core enabling flag. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: Iecc10c8946a450350adb34b984cf48ad988097ca Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
FSP has added the Cnvi BT Core enabling in addition to the existing CnviMode. This change adds the flag at the soc config side (i.e. soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host interface for BT. Therefore, BT core should not use the pci port status to turn on/off. TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make sure BT is turned on. Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15sc7180: make symbols common accross multiple targets.Ravi Kumar Bokka
making the symbols common accross targets to avoid duplicates for each soc. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-03-15drivers/generic/alc1015: Change HID name for driverEric Lai
From ALSA reviewer suggest to change the name to RTL1015. Details in below threads: https://www.spinics.net/lists/alsa-devel/msg123395.html BUG=b:177971830 TEST=: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2762852bdc3164346e3618c373aa4d3336415653 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-15drivers/generic/alc1015: Fix missing _DSD and correct property nameEric Lai
Missing acpi_dp_write and correct the name from sdb to sdb-gpios for driver. BUG=b:177971830 TEST: ALC1015P driver can get sdb-gpio properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2728a7dad695d5c97e85c5d86b1effea1595da65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51379 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/ocp/deltalake: Override uart base address via VPD variableBryant Ou
Use VPD of "coreboot_uart_io" to select uart io if OVERRIDE_UART_FOR_CONSOLE is selected. Tested=On OCP Delta Lake, console messages correctly output to uart port which is defined in VPD. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15mb/google/volteer: Create collis variantFrankChu
Create the collis variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:182227204 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COLLIS Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUsMeera Ravindranath
Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/ocp/deltalake: Override SMBIOS type 2 feature flagsTim Chu
Override SMBIOS type 2 board feature flags. For Delta Lake, board is replaceable and is a hosting board. Tested=Execute "dmidecode -t 2" to check info is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15mb/google/mancomb: Configure non-native function GPIOsEric Lai
Follow 20210308 schematic. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib259f3defc606c373f5ccac5f022d93e9a5c1469 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/google/mancomb: First pass GPIO configurationEric Lai
Follow 20210308 schematic. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1720ea8fec004d3ed3b3faaffa3b37dfcd710241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15rammus: get cbfs sar table name based on the sku idZhuohao Lee
This patch overrides the get_wifi_sar_cbfs_filename() to return different sar table according to the sku id. BUG=b:173465272 TEST=checked bios log and the correct sar table was loaded. Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15tests: Add lib/memrange-test test caseJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If30a238d32326ffd1d6719470deedc77f176ac72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENHhao_chou
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:175519097 BRANCH=firmware-volteer-13672.B TEST=build and verify on a Copano Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/shadowmountain: Add ACPI entry for BT reset GPIOAamir Bohra
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15mb/google/volteer: Add WiFi SAR table support for Lindar/LillipupKevin Chang
Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:178302811 BRANCH=volteer TEST=build and test no lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-03-15mb/google/volteer/var/lindar: Add FW_CONFIG WIFI_SAR_ID fields in devicetreeKevin Chang
Add FW_CONFIG WIFI_SAR_ID fields in devicetree. BUG=b:178302811 BRANCH=volteer TEST=build and test on lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/octopus/var/fleex: Add RTL5682 supportEric Lai
Fleex will use SSFC to support RTL5682. BUG=b:178653122 TEST=abuild Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-03-15mb/google/dedede/var/sasuke: Update LTE GPIO configurationSeunghwan Kim
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence specification. - FCPO (GPP_A10) should not turned off during warm reset. BUG=b:177177967 BRANCH=dedede TEST=Verified LTE power signal waveforms during powering on and off Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15pciexp_device: Rewrite LTR configurationNico Huber
I was bugged by spurious "Failed to enable LTR" messages for years. Looking at the the current algorithm, it is flawed in multiple ways: * It looks like the author didn't know they implemented a recursive algorithm (pciexp_enable_ltr()) inside another recursive algorithm (pciexp_scan_bridge()). Thus, at every tree level, everything is run again for the whole sub- tree. * LTR is enabled no matter if `.set_ltr_max_latencies` is implemented or not. Leaving the endpoints' LTR settings at 0: They are told to always report zero tolerance. In theory, depending on the root-complex implementation, this may result in higher power consumption than without LTR messages. * `.set_ltr_max_latencies` is only considered for the direct parent of a device. Thus, even with it implemented, an endpoint below a (non-root) bridge may suffer from the 0 settings as described above. * Due to the double-recursive nature, LTR is enabled starting with the endpoints, then moving up the tree, while the PCIe spec tells us to do it in the exact opposite order. With the current implementation of pciexp_scan_bridge(), it is hard to hook anything in that runs for each device from top to bottom. So the proposed solution still adds some redundancy: First, for every device that uses pciexp_scan_bus(), we enable LTR if possible (see below). Then, when returning from the bus- scanning recursion, we enable LTR for every device and configure the maximum latencies (if supported). The latter runs again on all bridges, because it's hard to know if pciexp_scan_bus() was used for them. When to enable LTR: * For all devices that implement `.set_ltr_max_latencies`. * For all devices below a bridge that has it enabled already. Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/kahlee: remove get_gpe_tableFelix Held
Since no board overrides the weak get_gpe_table function, gpe_configure_sci wasn't called for any variant, so drop the function. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCESTim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the adlrvp mainboard. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0Tim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the brya0 mainboard. TEST=snippet from dmesg logs shows the correct resources being allocated: PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24 PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20 PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24 PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20 PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24 PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resourcesTim Wawrzynczak
The Intel ADL BIOS specification #627270 recommends reserving the following resources for each PCIe TBT root port: - 42 buses - 192 MiB Non-prefetchable memory - 448 MiB Prefetchable memory Add a mainboard Kconfig which will auto-select these recommended values, in addition to PCIEXP_HOTPLUG. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Remove _DSD from tcss_pciexp ASL fileTim Wawrzynczak
The _DSD is generated at runtime using the Intel common pcie driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iee25a77bf5cc6636f46a5c32f3eeabe8524e0a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51454 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Remove _DSD from tcss_dma ASL fileTim Wawrzynczak
The _DSD is generated at runtime using the Intel common USB4 driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/blipper: Enable touchpad supportZanxi Chen
Add touchpad into devicetree for blipper. BUG=b:172787208 BRANCH=dedede TEST=built blipper firmware and verified touchpad function the kernel log: found RMI device, manufacturer: Synaptics Change-Id: I2c9b61ba9d282f994e2f756bafe4af1091d4d617 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons
Done for consistency with other platforms. This also drops redundant S3 resume logging, as `southbridge_detect_s3_resume` already prints it. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead. Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15Revert "mb/google/zork: restore stamp_boost parameter to 2500 for dirinboz"Kevin Chiu
This reverts commit 87a1bd696d47f80101e46132efae8cad8cfe5c7e. Reason for revert: skin temperature is overheating due to boost time is too long BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 22:13:59 +0000