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2021-07-08mb/intel/tglrvp: Update Power Limit2 minimum valueSumeet Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on tglrvp system Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08soc/intel/alderlake: Avoid NULL pointer deferenceJohn Zhao
Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08IMOK: Add IMOK method support for DPTFSumeet Pawnikar
Add IMOK method support for DPTF BRANCH=None BUG=b:187797417 TEST=Built and tested on dedede board Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-07mb/google/dedede/var/boten: Modify Wifi-SAR sku conditionstanley.wu
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR detect condition for boten/botenflex sku. BUG=b:186174768 TEST=build and test on boten/botenflex Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/sasukette: Configure I2C times for touchpadTao Xia
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390.4 kHz BUG=b:192601250 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmapWerner Zeh
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and provide a flashmap for partitioning. Select the used flashmap on variant level to allow different layouts for different variants. Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07mb/siemens/mc_ehl: Clean up KconfigWerner Zeh
Remove Kconfig switches that are not needed for mc_ehl based mainboards. Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07util/ifdtool: Add sklkbl to IFDv2 platformsJan Tatje
Currently ifdtool breaks the descriptor because it treats it as IFDv1. This change adds it to the list of IFDv2 platforms. Fixes boot for X11SSH-LN4F. Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07arch/x86: Save resume vector to stack in x86_64 modeIru Cai
In x86_64, the first function parameter is passed in rdi register, and the 32-bit code after exiting long mode reads the resume vector in 4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp). Also note that the function attribute "regparm" only works on x86-32 targets according to the GCC manual, so "asmlinkage" doesn't change the ABI of an x86_64 function. Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64 mode after this change. Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55947 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07Makefile.inc: Drop the cbfs master header from non-X86Arthur Heymans
The pointer to the header has a x86 top mmaped address even though the boot medium is not mapped that way. If no pointer is used to find the header FMAP is needed. If FMAP is used anyway there is no need for a cbfs master header. Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07Makefile.inc: Fix IFITTOOL dependenciesArthur Heymans
Add IFITTOOL as a dependency where needed and remove where it is unneeded. Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07Makefile.inc: Remove explicit ramstage dependency for coreboot.romArthur Heymans
This is already handled in $(prebuild-files). Change-Id: I648f97198772d30d6d267ab9d6f7fa8d1d5d0e91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stabilityRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07vc/mediatek/mt8195: Improve settings of duty calibrationRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07soc/mediatek/mt8195: Add dramc_param.hRyan Chuang
The dramc_param.h defines the header version, structure and APIs for the DRAM calibration parameters stored on the flash, and should be platform independent. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07soc/mediatek/mt8195: Enable DCMGarmin Chang
Enable DCM settings on the MT8195 platform. DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Signed-off-by: Garmin Chang <garmin.chang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30595 -> 30400 VDD Offset: 77 -> 317 SOC Slope : 24063 -> 23789 SOC Offset: 105 -> 94 BUG=b:190338440 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2021-07-07cpu/intel/car/core2/cache_as_ram: Add x86_64 supportPatrick Rudolph
Tested on Lenovo T500 with additional patches. Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-07ironlake: Add support for x86_64Patrick Rudolph
Allow to compile the experimental x86_64 code. Tested on Lenovo Thinkpad T410. Hangs in SMM relocation. When skipped boots into GNU/Linux. Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-07-07configs: Explicitly specify vendor and mainboardAngel Pons
Relying on the implicit defaults for these settings can cause issues in the future. For example, commit 8cc4c5a1e76c0c8aee3a14618c15d38e3bd2bd61 (config.dell_optiplex_9010_sff: Specify board model) was done to prevent a build failure when adding support for other Dell mainboards which make the default board change. Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56079 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06soc/amd/picasso: Allow end range entry for max device ID in IVRSAamir Bohra
Allow hot plug devices to subscribe to IOMMU services. Currently the IOMMU end range is limited to device B:0 D:1f F:6. This prevents the devices on bus 1 and higher to subscribe to IOMMU services. As per AMD IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined, whether the device ID is actually populated or not. Device entries are used to report ranges when hot-plug and SR-IOV devices are possible. With this change the hot plug devices can now bind to IOMMU services (as tested on kernel v5.4), and below errors are not seen in dmesg. AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000] TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen. The hot plug devices can successfully bind to IOMMU services in kernel. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06configs/config.foxconn_g41m: Build test with X86_64Arthur Heymans
Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56042 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06nb/intel/x4x: Expose x86_64 supportArthur Heymans
TESTED on foxconn g41m. Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56022 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06cpu/intel/car/p4: Add x86_64 supportArthur Heymans
Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-06arch/x86: Use ENV_X86_64 instead of _x86_64_Patrick Rudolph
Tested on Intel Sandybridge x86_64 and x86_32. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-05configs: Build test x86_64 on Sandy BridgePatrick Rudolph
Add defconfig to build test x86_64 code on Sandy Bridge. Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrik Tesarik <depate@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-05mb/siemens/mc_ehl: Provide a proper scheme for variantsWerner Zeh
There will be more variants of this mainboard so prepare the scheme for Kconfig to handle the variants properly. Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crbWerner Zeh
Add a new mainboard called mc_ehl which is based on Intel's 'elkhartlake_crb'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05device: Reflow strings in printk statementsAngel Pons
To ease finding some log messages, reflow their strings to use one line. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-05mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for ↵Varshit B Pandya
camera ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ↵Varshit B Pandya
ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Compared SSDT with this patch against DSDT without this patch, they are same Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05util/board_status: Do not display grep messagePaul Menzel
Redirect stdout and stderr from grep to check for unknown timestamps, when no timestamps are stored, which is already logged earlier. Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring Getting remote dmesg grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-05mb/google/dedede: Fix the pointer/address used in memcpyKarthikeyan Ramasubramanian
The caller is already passing the address to the required LTE reset and enable GPIO. During memcpy, the address to that pointer is used which will lead to copying undefined data. Fix the pointer/address used in memcpy. BUG=None BRANCH=dedede TEST=Build Kracko, Drawcia and Metaknight mainboards which use this function. Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Found-by: Coverity CID 1458053, 1458054. Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05timestamp,vc/google/chromeos/cr50: Add timestamp for enable updateRaul E Rangel
cr50_enable_update takes a non-trivial amount of time. TEST=Boot guybrush and dump timestamps 553:started TPM enable update 3,615,156 (444) 554:finished TPM enable update 3,632,810 (17,654) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I522d0638a4a6ae9624965e49b47bca8743c3206c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05device/resource_allocator_v4: Only highlight log message with ===Paul Menzel
Currently, four instead of three = are used in one log message. Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === As the ending mark is `===` change it to `===` in the beginning. Done reading resources. === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56045 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05sb/intel/i82801gx: Prepare for x86_64Arthur Heymans
Do the usual int conversions. TESTED: BUILD_TIMELESS=1 produces identical image on foxconn/g41m. Change-Id: Idebfe4669854b307bee653df6d93e46ae3f39dec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56020 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05nb/intel/x4x: Use write32p and read32pArthur Heymans
This removes the need for type conversions all over the place. Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05nb/intel/x4x: Prepare for x86_64 supportArthur Heymans
Do the usual type conversions TESTED: Same image with BUILD_TIMELESS=1 Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05cpu/intel/car/p4-netburst: Prepare for x86_64Arthur Heymans
Use proper car symbols. Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56018 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/intel/adlrvp: Update the FIVR configurationsV Sowmya
This patch sets the optimized FIVR configuration for adlrvp cutomized based on the pnp measurements to achieve the better power savings in sleep states. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 states. * Update the supported voltage states. * Set the ICC max to 500mA for v1p05 and vnn. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-05soc/intel/alderlake: Add support to update the FIVR configsV Sowmya
This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/google/brya/brya0: Enable CrashlogTim Wawrzynczak
brya0 is a reference and development platform, therefore it would be helpful to have Crashlog enabled. Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-05mb/google/brya: Add HANG_DETECT host event to EC S0ix wake maskTim Wawrzynczak
The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-05mb/google/dedede/var/cret: Disable SDCard controllerDtrain Hsu
Cret doesn't support SDCard. Disable SDCard contorller for Cret. BUG=b:191232222 TEST=Build and boot to check lspci Cq-Depend: chromium:2993724 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya
Correct Bus and Device for THC0 and THC1 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-04supermicro/x11: enable COMB via LPCAlexander Couzens
Allow to use the 2nd COM port of the AST2400 which can be also used via IPMI/serial-over-lan. Change-Id: I6f9c85b1f5428d3c3acf7a2f20296134c4611b1e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-02util/cbfstool: Allow setting alignment for payloadRaul E Rangel
The -a flag was already implemented, it just wasn't exposed for the add-payload command. Setting the alignment of the payload will enable using the SPI DMA controller to read the payload on AMD devices. BUG=b:179699789 TEST=cbfstool foo.bin add-payload -a 64 ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/espi: Fix debug message log levelRaul E Rangel
BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02drivers/intel/fsp2: Change FSPS returned message to INFORaul E Rangel
This message is not an error, but just informational. BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI readsRaul E Rangel
We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02soc/amd/cezanne: Enable SPI DMA supportRaul E Rangel
Start using the custom boot device. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/lpc: Add custom SPI DMA boot deviceRaul E Rangel
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it was easier to review. The next patches will add support for the SPI DMA controller. This will provide a minor speed up vs using mmap reads. It will also provide the facilities to perform asynchronous SPI loading. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02arch/x86: Add X86_CUSTOM_BOOTMEDIARaul E Rangel
In order to disable X86_TOP4G_BOOTMEDIA_MAP it requires the definition to be overridden. This makes it a little less ergonomic to use. Instead introduce the inverse option that can be selected. I chose to leave X86_TOP4G_BOOTMEDIA_MAP since it keeps the Makefiles simple. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02cpu/qemu-x86: Increase heap sizeAngel Pons
On x86_64, the default heap size is too small when using 32 CPUs. Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02src: Consolidate x86_64 support KconfigAngel Pons
Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations of the same functionality with the newly-added Kconfig options. Update documentation and the config file for QEMU accordingly. Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02mb/google/dedede/var/magolor: Enable G2 touchscreen for magmaTyler Wang
Add G2 touchscreen support for magma. BUG=b:189852808 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3e032bff7f3e97f54f3e544035e862058ea0dbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2021-07-02soc/intel/common/block/cse: Add ME EOP timestampsTim Wawrzynczak
BUG=b:191362590 TEST=on brya, cbmem -t: 942:before sending EOP to ME 2,628,446 (5,879) 943:after sending EOP to ME 2,631,177 (2,730) Change-Id: I0376610c5cbae7df1bf1a927b3bc99b1022de4cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-02mb/google/volteer/variants/eldrid: Include SPD for MT40A512M16TB-062E:RMark Hsieh
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R. Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated with MT40A512M16TB-062E:R DDR4 memory parts. BUG=b:192380070 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02util/intelp2m: use import once for all included modulesMaxim Polyakov
There is no need to repeat "import" for each module in GoLang. Use this keyword only once in each file for code cleanliness. Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02soc/intel/alderlake: Add USB TCSS enablementBernardo Perez Priego
In order to detect USB Type C device port as Super Speed, we need to set corresponding bit in UPD UsbTcPortEn. This patch will use device path to determine which port should be enabled. BUG=b:184324979 Test=Boot board, USB Type C must be functional and operate at Super Speed. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I7da63f21d51889a888699540f780cb26b480c26d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-02selfboot: Add support for selfload in romstageShelley Chen
Since bootmem is not available in romstage, calls to bootmem APIs need to be compile-time eliminated in order to avoid linker error: undefined reference to `bootmem_region_targets_type BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B cherry-picked on top of CB:49392 and verified successful compilation. Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55865 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01drivers/intel/gma: Move extended VBT just below opregionMaulik V Vaghela
Currently the flow for opregion init is as below: 1. Allocate memory for opregion first (cbmem_add(opregion)) 2. Check if VBT size > 6 KiB (this requires extended VBT support) 3. In case of extended VBT requirement, we allocate another chunk of memory which is equal to size of VBT (cbmem_add(extended_vbt)) 4. Pass physical address pointer to OS via RVDA We can optimize the above flow to allocate single chunk of memory by checking VBT size in earlier step. The new optimized flow for opregion init is as below: 1. Check if VBT size > 6 KiB (this requires extended VBT support) 2. In case of extended VBT requirement, total memory to be allocated is calculated as sizeof(opregion) + sizeof (extended_vbt) In case where VBT size is < 6 KiB, total memory requirement would be equal to sizeof(opregion) 3. Based on above calculation, allocate single chunk of memory based on total size. This will also be helpful for the case of virtualization where guest users don't have access to physical address and when it needs relative address of VBT compared to absolute address. In case of opregion 2.1 spec, we need to pass relative address of VBT from opregion base in RVDA. This optimization will help in meeting this requirement since relative address of extended VBT is easy to get. This change will ensure that it meets opregion specification requirement and will be compatible with future versions as well. BUG=b:190019970 BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()Arthur Heymans
The dereferced parameter is never updated so passing a copy would work too. Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01mb/google/hatch/scout: update gpios and device treeJeff Chase
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/brya: Swap P-sensor IRQEric Lai
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct P-sensor. BUG=b:192331122,b:181555900 TEST=check P-sensor driver can be probed without error. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01soc/intel/alderlake: Enable energy efficiency turbo modeV Sowmya
This patch enables the energy efficiency turbo mode. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2d76c948bdc9c208f5728e305b3034fcede6f4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55705 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01soc/intel: Refactor `xdci_can_enable()` functionAngel Pons
The same pattern appears on all `xdci_can_enable()` call sites. Move the logic inside the function and take the xDCI devfn as parameter. Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01drivers/intel/dptf: Add OEM variables supportSumeet R Pawnikar
This adds OEM variables feature under DPTF as per BWG doc #541817. Using this, platform vendors can expose an array of OEM-specific values as OEM variables to be used in determining DPTF policy. These are obtained via the ODVP method, and then simply exposed under sysfs. In addition, these gets updated when a notification is received or when the DPTF policy is changed by userspace. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01device: Clean up resource utility function signaturesKyösti Mälkki
Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGSIru Cai
This fixes building with libgfxinit in x86_64 mode, which can generates unsupported R_X86_64_32S relocations without -mcmodel=large. Change-Id: If5162fae475f3e70c856d9664a8cfc6a89d82283 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01QEMU: Only call `pci_assign_irqs` with non-NULL devAngel Pons
Do not call `pci_assign_irqs` with a NULL device pointer. Change-Id: Ide9ae38dedd881ed673ba1838a1e29529b306937 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-01mb/emulation/qemu-i440fx: Tidy up PAM register writesAngel Pons
Tidy up the code that programs the PAM (Programmable Attribute Map) registers. Introduce the `D0F0_PAM` macro and use it to replace the magic `0x59` and `0x5a` values in the code. Adjust the range of the for-loop to work with the `D0F0_PAM` macro, and properly indent the loop's body. Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-01mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X seriesBill XIE
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-01mb/prodrive/hermes: Implement smbios_mainboard_versionPatrick Rudolph
Return the HSI version read from BMC in smbios_mainboard_version. Change-Id: If907d598c9e05d35f8898d294678f61d075f935a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-01mb/google/dedede: Create cappy2 variantSunway
Create the cappy2 variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192035460 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY2 Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/brya/variants/primus: Update mainboard properties for BB retimer ↵Casper Chang
upgrade This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:55348 BUG=b:191897776 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-01mb/google/dedede/var/drawcia: Add LTE modem support for drawperKevin Chiu
Add LTE modem to devicetree. Configure GPIO control for LTE modem by fw_config. Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:186393848 TEST=Build image and check with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/dedede/var/kracko: Update LTE USB port configurationTony Huang
Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:178092096 BRANCH=dedede TEST=Build and boot to OS to check LTE by modem status Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01device/pci_device.c: Reuse `irq` variableAngel Pons
The `irq` variable has the same value as `pIntAtoD[line - 1]`. Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-01soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION configSubrata Banik
By enabling the flag alderlake platform will use hardware sha instruction instead of software implementation for sha256. This will speed up firmware verification especially on low-performance device. Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01vboot: add VBOOT_X86_SHA256_ACCELERATION configSubrata Banik
Add Kconfig option for VBOOT_X86_SHA256_ACCELERATION, which will use x86-sha extension for SHA256 instead of software implementation. TEST=Able to call vb2ex_hwcrypto_digest_init() and perform SHA using HW crypto engine. Change-Id: Idc8be8711c69f4ebc489cd37cc3749c0b257c610 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-01Update vboot submodule to upstream mainSubrata Banik
Updating from commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted to commit id ccc56f4: vboot: add x86 SHA256 ext support Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-01SMBIOS: Drop now-unnecessary unionsAngel Pons
Now that the refactoring is complete, the unions for the table header are no longer needed. Therefore, drop them. Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/emulation/qemu-i440fx/fw_cfg.c: Use `smbios_header`Angel Pons
Replace uses of `smbios_type0` with `smbios_header` for correctness. Change-Id: I2479984f5322f0fb474ff1707c1dd1f5885f30e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_full_table_len` functionAngel Pons
Introduce the `smbios_full_table_len` function to consolidate table length calculation. The case where the length of a table equals the length of the structure happens when a table has no strings. Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01arch/x86/smbios.c Move calculation next to usageAngel Pons
Change-Id: I949da86605e76b186ef2fdbfbc112b71544b694a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_carve_table` functionAngel Pons
Factor out some boilerplate code into a helper `smbios_carve_table` function, which zeroes out the table memory and fills in the header fields common to all tables. Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Introduce struct for SMBIOS table headerAngel Pons
All SMBIOS `type X` tables start with the same 4-byte header. Add a struct definition for it, and use it where applicable. The union is temporary and allows doing the necessary changes in smaller commits. Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/pcengines/apuX: Refactor to avoid dead assignmentAngel Pons
The initial value of `len` is never used. Declare and initialise all local variables in a single statement to avoid this problem. Change-Id: Ieb96758f4cd19d9d3f8fdc543e8ca17db06a2123 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01arch/x86/smbios.c: Trim some `len` variablesAngel Pons
Reduce the scope or remove some `len` variables. This is done to ease replacing `sizeof` on struct types in a follow-up commit, by ensuring that all to-be-replaced appearances follow the variable declarations. Change-Id: Ied38fcaf87ef5b1e4f93076b4ba2898ad1f98a72 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01drivers/mrc_cache: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Icf4f1c8fe9f54c44b041a65eb46d6ec9f9fd6367 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30commonlib: Add Intel-specific timestamps for before/after sending EOPTim Wawrzynczak
Change-Id: I11daebbfc44959f1e498ddac2ee7633e31a1a7d5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2021-06-30soc/intel/jasperlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#619830. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I36fe448ff279ba054ad5e79e71c995dc915db21e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#612229 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/intel/alderlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#627331. TEST=on brya, autotest firmware_CheckEOPState confirms ME is in post-boot state Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/intel/common/block/cse: Add BWG error recovery to EOP failureTim Wawrzynczak
This patch adds functionality to attempt to allow booting in a secure configuration (albeit with potentially reduced functionality) when the CSE EOP message fails in any way. These steps come from the CSME BWG (13.5, 15.0, 16.), and tell the CSE to disable the MEI bus, which disables further communication from the host. This is followed by requesting the PMC to disable the MEI devices. If these steps are successful, then the boot firmware can continue to boot to the OS. Otherwise, die() is called, prefering not to boot over leaving the insecure MEI bus available. BUG=b:191362590 TEST=Set FSP UPD to disable sending EOP; called this function from a BS_PAYLOAD_LOAD, ON_ENTRY entry; observed that with just cse_mei_bus_disable() called, Linux can no longer communicate over MEI: [ 16.198759] mei_me 0000:00:16.0: wait hw ready failed [ 16.204488] mei_me 0000:00:16.0: hw_start failed ret = -62 [ 16.210804] mei_me 0000:00:16.0: H_RST is set = 0x80000031 [ 18.245909] mei_me 0000:00:16.0: wait hw ready failed [ 18.251601] mei_me 0000:00:16.0: hw_start failed ret = -62 [ 18.257785] mei_me 0000:00:16.0: reset: reached maximal consecutive.. [ 18.267622] mei_me 0000:00:16.0: reset failed ret = -19 [ 18.273580] mei_me 0000:00:16.0: link layer initialization failed. [ 18.280521] mei_me 0000:00:16.0: init hw failure. [ 18.285880] mei_me 0000:00:16.0: initialization failed. Calling both error recovery functions causes all of the slot 16 devices to fail to enumerate in the OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I06abf36a9d9d8a5f2afba6002dd5695dd2107db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55675 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30mb/google/brya/variants/gimble: init overridetree for gimbleMark Hsieh
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf BUG=b:191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3f6875ef438b147436605629445d346a56896a87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 03:05:52 +0000