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2024-07-13soc/intel/alderlake: Fix system hang by enabling SMI handlingJamie Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:350623902 TEST=reboot test on 40 google/xol by ODM, all passed w/o hang. Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83432 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Edward Doan <edoan@chromium.org>
2024-07-13mb/google/brask/var/bujia: remove DPTF fan controlShon
Fan control is assign to EC handle now. Remove relate setting on coreboot. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: Iff0776ce3db6f27e250162357abb3c7e9b1a0dc3 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83380 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-12skl/kbl mainboards: Move PCIe related settings into their device scopeFelix Singer
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-07-12soc/intel: Adapt crashlog IP to also support 64-bitSowmya Aralguppe
This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. uintptr_t data type is used for Address pointers and void* for dereferencing BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/google/brox/var/lotso: Add FW_CONFIG for FPWentao Qin
This patch adds FW_CONFIG to accommodate different Lotso BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent BUG=b:350360162 BRANCH=None TEST=Boot image on SKU2 and check FP working. Change-Id: I1ee5fcd1c29099bdbee741ef76c00cf45fcc1189 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83388 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/intel/mtlrvp: Set USB2-10 as cnvi_wifi bluetooth companion deviceJeremy Compostella
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. This commit also updates the USB2 port 10 description and set its type to the more appropriate `UPC_TYPE_INTERNAL' type. BUG=b:348345301 TEST=BRDS method is added to the CNVW device and returns the data supplied by the SAR binary blob Change-Id: I66c9b75d2aaa1b221313b037defcd2c579fd6b61 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com>
2024-07-12amdfwtool: make fields unsignedGeorge Burgess IV
The value stored in `gen` is only ever `1` or `0`. Storing `1` causes Clang to warn, since the only valid values for a 1-bit int are -1 and 0: ``` amdfwtool.c:1487:27: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] 1487 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; ``` TEST=Rebuilt coreboot; no warning was emitted. Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Signed-off-by: George Burgess IV <gbiv@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83412 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2024-07-12mb/google/nissa/var/riven: add fw_config probe for storage devicesDavid Wu
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree instead of variant.c, it can avoid suspend(s0ix) fail issue. BUG=b:328580882 TEST=On riven eMMC and UFS SKUs, boot to OS and run `suspend_stress_test -c 10` pass. Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/google/brask/var/bujia: Disable thunderboltShon
Bujia does not support Thunderbolt anymore, therefore disable related TBT setting. The bujia fit image CL, cf. chrome-internal:7468938. BUG=b:349923139 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12soc/intel/cmn/cse: Correct CMOS error message for CSE partition firmwareSubrata Banik
The CMOS entry for CSE partition firmware was incorrectly labeled as `ramtop` and `partition firmware` in the error messages. This patch corrects the messages to accurately refer to `CSE partition firmware`. Additionally, the alignment and size check comments are updated to reflect this change. Change-Id: Ib3a7fb88f52c4d0c47d828bcd1c4649e62d19654 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-11Update amd_blobs submodule to upstream mainMatt DeVillier
Updating from commit id ae5fc7d: 2024-03-15 19:58:57 +0100 - (picasso: Update PSP fw to version 00.08.14.7B) to commit id 26c5729: 2024-07-10 10:10:50 -0500 - (CZN: Update SMU fw to 64.72.0) This brings in 2 new commits: 26c5729 CZN: Update SMU fw to 64.72.0 942adff Add VanGogh blobs Change-Id: I4c699379a196a0819201f7a6c9f1b3319edef4ff Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-11libpayload/x86: Add x86-64 support to rdtsc()Subrata Banik
This patch adds support for x86-64 to the rdtsc() function, allowing it to correctly read the Time Stamp Counter (TSC) on both 32-bit and 64-bit x86 architectures. BUG=b:242829490, b:351851626 TEST=Builds and boots on google/rex0 and google/rex64 systems and manually verified correct TSC readings on x86-32 and x86-64 hardware. Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-11soc/intel/cmn/cse: Refine boot partition loggingSubrata Banik
This patch ensures CSE boot partition (RO/RW) version information only log when the status is "success". If the status is not successful, log an error message indicating the failure and status code. This change avoids logging potentially incorrect version information when the boot partition is not valid. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11mb/google/rex: Refactor CSE config options for model-specific settingsSubrata Banik
This patch refactors CSE config options, moving the selection of: * `SOC_INTEL_CSE_LITE_SKU` * `SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2` * `SOC_INTEL_CSE_SEND_EOP_ASYNC` from the generic `BOARD_GOOGLE_REX_COMMON` to individual board models. This enables finer-grained control over CSE features and sync behavior on different Rex and variants platforms. Specifically: * `google/rex0`: Selects `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot. * `google/rex64`: Selects `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` and `SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD` to defer CSE sync to the payload. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: Ib5957496b1e1dad8d135b3e10541cb83dd339539 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83397 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel/meteorlake: Conditional selection of CSE Lite PSRSubrata Banik
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being enabled. This ensures that CSE Lite PSR is only active when both ChromeOS is the target platform and CSE sync is performed inside coreboot. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel: Extend CSE RW Update and ME read access for payload syncSubrata Banik
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-MSubrata Banik
This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibilitySubrata Banik
This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)Ronald Claveau
Mainboard is identified as 0Y2MRG. The version tested is with Nvidia dGPU (gfx 560ti). The flash is a 4MiB Winbond W25Q32BVSIG. It can be flashed internally with flashrom. Add a strap on the service mode pin of the mainboard for internal flash. Tested working: - SeaBIOS - All USB ports - SATA - dGPU - Ethernet - Environment control - GPIOs - S3 Sleep mode - WakeOnLan Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059 Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-11drivers/qemu: Clarify config option name for QEMU display resolutionAlper Nebi Yasak
A previous commit splits out Cirrus display support from Bochs display support, with both using the pre-existing Bochs config options for the requested display resolution. Rename these config names to clarify they are not only specific to the Bochs display driver. Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11drivers/qemu: Split Cirrus display support from Bochs display supportAlper Nebi Yasak
QEMU's Cirrus display device is supported along with the Bochs driver since commit 7905f9254ebc ("qemu: cirrus native video init"). It is no longer the default since QEMU 2.2. The code supporting it can work independently of the Bochs display driver and depends more heavily on port I/O and VGA support code, so split it from that code to make it easier to support the Bochs driver in other architectures. Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11mainboard/qemu-aarch64: Set CONFIG_PCI_IOBASE to 0x3eff0000Alper Nebi Yasak
Define the PCI I/O base address necessary to use port I/O functions on the qemu-aarch64 mainboard, so that we can get the VGA display devices working. The config value is from hw/arm/virt.c [1]: [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, [1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164 Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11sconfig: Provide simple constants for aliased devicesNico Huber
Expose aliased PCI and PNP devices as `pci_/pnp_devfn_t` constants in <static_devices.h>. They will be named `_sdev_<alias>` to have a underscore prefix for consistency and to not collide with the `struct device` objects (with `_dev_` prefix). Change-Id: I2d1cfe12b1e7309f8235c84dd220bd090ebfe1b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-11sb/intel/smbus: Implement smbus_send_byte()Nico Huber
Allows to use this driver for the SMBus console without sending an index byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER). Tested with WiP VIA CX700-M2 port and FT4222H as receiver. Change-Id: Ic368ef379039b104064c9a91474b188646388dd2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/amd/phoenix: Fix APOB NV size/base for non-vboot buildsMatt DeVillier
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Myst boards. TEST=untested, but same change as made for Mendocino Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-07-11soc/amd/mendocino: Fix APOB NV size/base for non-vboot buildsMatt DeVillier
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Skyrim boards. TEST=build/boot Skyrim (Frostflow), verify RAM training only run on first boot after flashing. Change-Id: I9be1699d675331b46ee9c42570700c2b72588025 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-07-11console/i2c_smbus: Allow to send data w/o register offsetNico Huber
Not every I2C target requires a register address. Not sending one for every console char saves us a lot of overhead. Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82762 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10autoport: Drop ioapic, ioapic_irq, and lapic handling for devicetreeNicholas Chin
The ioapic and ioapic_irq keywords are no longer valid tokens as of commit e84b095d3a23 (util/sconfig: Remove unused ioapic and irq keywords), and the associated driver had previously been removed in commit ca5a793ec31c (drivers/generic/ioapic: Drop poor implementation). Thus, drop them from autoport. Also, the IOAPICIRQs map that this code relied on to generate ioapic_irq entries never seems to have been populated by any code in any previous commit, so this appears to have been dead code since autoport was created. The lapic keyword was removed from sconfig in commit 15d5183e4af7 (util/sconfig: Remove lapic devices from devicetree parsers) so remove autoport handling for it as well. Change-Id: Icf2582594b244cf5f726c722eb3a3c12573a2662 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-10console: Fix I2C/SMBus console if it's the only slow oneNico Huber
Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82761 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10mb/google/brask/var/bujia: Add wireless and memory thermal sensorShon Wang
Bujia has 4 thermal sensors, so add two missing sensors settings. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. check ACPI SSDT table have new TSR info. $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT check SSDT.dsl Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-10emulation/qemu-q35: Remove redefine TSEG_SZ_MASKElyes Haouas
TSEG_SZ_MASK is already defined in "q35.h" Change-Id: I32ea08c18e1c41d16137ea14a1643f8c8d527722 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83386 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10Documentation: Use pkgconf over pkg-configElyes Haouas
Change-Id: I3e9a92d019854214a5760f705b9cbe3cabe6d2e8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-07-10xcompile: Use one line per CLANG_CFLAGS_${TARCH} flagElyes Haouas
Change-Id: I5c649898218a9c5d51d18a35264e9636e3dee179 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-09ec/google/chromeec: Stop checking CBI for UCSIAbhishek Pandit-Subedi
The ucsi_enabled flag is no longer used by the EC. Update coreboot to only use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled. BUG=b:319124515 TEST=emerge-brox coreboot chromeos-bootimage Cq-Depend: chromium:5664227 Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83252 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Forest Mittelberg <bmbm@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-09releases/coreboot-24.08: Remove ACPICA lineElyes Haouas
ACPICA reverted from 20240321 to 20230628 (commit 7c1813c1). Change-Id: Id238f77c6a0b4052ae3d835caf98aaf26a7e570f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-09Documentation/Makefile: Fix test targetNicholas Chin
The test target called make with the `-K` flag, which is not valid. Change it to `-k` (keep going if some targets fail) which is what was probably intended. It also tried to build the `doctest` target from Makefile.sphinx, which results in an error. Further investigation reveals that this is because the sphinx doctest extension was not enabled in conf.py. However, from the documentation of doctest [1], it seems like it is intended to ensure that documentation containing Python snippets along with the expected output of the snippet remain in sync, which is something that we probably don't need. So, remove the call to it. [1] https://www.sphinx-doc.org/en/master/usage/extensions/doctest.html" Change-Id: Id514950b4486ed8644d078af222c96ed711fc8f9 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83381 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-07-09Documentation: Fix header levelsNicholas Chin
This fixes the following MyST Parser warnings: - Non-consecutive header level increase - Document headings start at H2, not H1 The header levels (the number of "#" characters before a heading) are intended to form a logical hierarchy of each section and subsection in a document. A subsection typically should have a header level one more than its parent section. Most of these warnings are caused by extra "#" characters, which were simply removed, or sections missing a "#" character to make it fall under its parent section. Notable changes: getting_started/kconfig.md: Changed the header level of the "Keywords" section from 2 to 3 to fall under "Kconfig Language" (level 2), and increased the level of each keyword from 3 to 4 to remain under "Keywords". This also fixes the warnings of "H3 to H5" increases, since the Usage/Example/Notes/Restrictions sections for each keyword had a level of 5. soc/intel/cse_fw_update/cse_fw_update.md: Changed the first line to a top level header acting as the title of the document. Without this soc/intel/index.md displays all the level 2 headers in this document instead of a single link to cse_fw_update.md. Change-Id: Ia1f8b52e39b7b6524bef89a95365541235b5b1b9 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83382 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-07-09Docs: Fix paths in references to other markdown documentsNicholas Chin
This fixes a few "cross-reference target not found" warnings from MyST parser. In these cases, the relative path to the target markdown document was incorrect. Change-Id: I5d01deacc3ba7401faba30fc832e2357d4aedad8 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83383 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-09mb/asrock/z97_extreme6: Fix EDID mapping for DVI-IAngel Pons
This board has a DVI-I connector, which supports both digital and analog display outputs. The I2C bus to retrieve the EDID is shared between both outputs, so `select GFX_GMA_ANALOG_I2C_HDMI_B` to describe this. Can't currently test this due to lack of hardware. Change-Id: Ib8239917e2f7ee5bb982621752ec406c2d3ca302 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82753 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-09Documentation: Remove explicit install of 'm4'Elyes Haouas
Remove m4 as it will be installed automatically by flex and bison. Change-Id: Ifb748e5aaabb96825813ddb92cf28d2ea7bdcbf9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-07-09Doc/tutorial/part1.md: Correct libncurses-dev pkg name for debianElyes Haouas
Change-Id: I5a71b914d40a9ea45be87f4581ff0072605e8c00 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-07-09payloads/ipxe/kconfig: Fix option name prefixFelix Singer
With commit 238ff1e9c7 ("payloads/ipxe: Prefix iPXE options with "IPXE" instead "PXE""), the prefix for iPXE related Kconfig identifiers was unified to "IPXE". So rename the identifier for the TRUST_CMD option as well, which was introduced later. Change-Id: I918358b859003503526ba7849494bb23f8c893fd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83361 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-08Makefile.mk: Fix int-shift-leftMaximilian Brune
commit 4a8d73d6a4 ("Makefile.mk: Remove bc dependency") broke the left shift, since the expr tool does not support shifting operations. This patch uses the left shift operator inside arithmetic expansion. Every posix shell should support this. Tested: Build amd/birman mainboard and check that the soft-fuse parameter doesn't change. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If3b29dae727875b0788100a2cb02c86736ffaf8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83377 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-07-08chromeec: support reading long battery stringsPeter Marheine
The Chrome EC currently supports two ways to read battery strings on ACPI platforms: * Read up to 8 bytes from EC shared memory BMFG, BMOD, ... * Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from the response. This is assumed to be exclusively controlled by the OS, because host commands' use of buffers is prone to race conditions. To support readout of longer strings via ACPI mechanisms, this change adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473) and allows ACPI firmware to read strings of arbitrary length (currently limited to 64 characters in the implementation) from the EC and to determine whether this function is supported by the EC (falling back to shared memory if not). BUG=b:339171261 TEST=on yaviks, the EC console logs FIFO readout messages when used in ACPI and correct strings are shown in the OS. If EC support is removed, correct strings are still shown in the OS. BRANCH=nissa Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-08Makefile.mk: Remove bc dependencyMaximilian Brune
bc was added as dependency in commit 229e021110 ("Makefile.inc: Add left shift macro") bc is not stated as dependency in our docs (e.g. package installation). If you don't have bc installed you can easily get false positives on coreboot builds. For example you build a mainboard and coreboot tells you the build succeeded, even though you don't have bc installed. This patch is from julius comment on CB:21601. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I6ab4bc2bd7a45e84b923d4fe7ec473e6c7db2146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-08util/ifdtool: dump SPI modes from FLCOMPAlexander Goncharov
These fields are documented in the Alder Lake-S Client Platform SPI Programming Guide, but they are not presented in the Skylake-LP Client Platform SPI Programming Guide Change-Id: I624fe5cb28aa3cb207bc48aa8d31b2a71b70bcf2 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-08cpu/intel/model_206ax: Allow PL1/PL2 configurationAnastasios Koutian
Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I064af25ec4805fae755eea52c4c9c6d4386c0aee Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-08mb/google/brox/var/lotso: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,according to b:348285763#comment6. BUG=b:348285763 TEST=emerge-brox coreboot Change-Id: I67e16a2596884d501273a5787119406dff7a20f9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83304 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-08mb/google/brya: Select Intel PDC to PMC CONFIGURATION for orisaAmanda Huang
Orisa uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. BUG=b:345070027 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3f740bedc8ff667d15f077fa57d201ab0d42ebf8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83324 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2024-07-08mb/google/trulo/var/orisa: Add fw_config field for PDC controlAmanda Huang
Add a new fw config field to determine which firmware edition shall be flashed to the PDC. BUG=b:334793686 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I817e9415aca1d2f68b484d8e23b581e1a75d6f84 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83353 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-06util/sconfig: Remove unnecessary strdup() callsJakub Czapiga
getopt() optarg value can be used without duplicaing if it is not modified, as it is the case here. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie5a27f64077af1c04b06732cd601145b8becacfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/70525 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05tgl mainboards: Move PCIe root port settings into their device scopeFelix Singer
Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05autoport: Print location of generated sourcesNicholas Chin
Autoport determines the mainboard vendor and board names based on DMI entries, which sometimes doesn't result in the most obvious name. In addition, newcomers may not be familiar with coreboot's directory structure and have no idea where to look. Print out the absolute patch of the generated sources once autoport finishes so that it is easier to locate the files. Change-Id: I4ba00484ac57355d7539fa6e36e0e6df62719f8a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83344 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-05autoport: Factor out GPIO config generationNicholas Chin
Intel chipsets from ICH7 through Lynxpoint use the same GPIO register format and thus mainboards using using these platforms have similar gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so that it other chipsets added to autoport can use it. This was originally written by Iru Cai in his Haswell autoport patch in CB:30890; I have simply split out the code to a separate commit as it is a separate logical change. TEST=Generated output is identical before and after this patch when run against logs from a Dell Latitude E6430 Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05util/liveiso/nixos: Install flashprogFelix Singer
Change-Id: Id0a0de9bbbe2d3b0885bec2abea0a2022a7e1cbb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-05payloads/external: don't prevent parallel build of iPXESergii Dmytruk
When starting a nested instance Make communicates information on the number of jobs and how to synchronize difference instances via MAKEFLAGS variable. Explicitly overwriting it when invoking payloads/external/iPXE/Makefile ends up forcing serial build of iPXE. iPXE builds hundreds of files and its dependency generation is done separately from compilation making the whole process take couple minutes on a single CPU (which becomes several seconds if large enough number of CPUs is available). iPXE seems to have Make-based build system that has no problems with parallel build and not utilizing that effectively turns it into a bottleneck when building a coreboot image in parallel. It's unclear whether MAKEFLAGS= was even added for any particular purpose. It doesn't prevent child instances from using variables of parents, nor it prevents child instance from running in parallel (because it's still passed as an environment variable that's processed prior of variable assignments on command-line), but it does prevent grandchild instance from running in parallel (actual iPXE's Makefile). MFLAGS contains flags from MAKEFLAGS and isn't used implicitly by Make, so no need to clear it either because iPXE doesn't use it. Change-Id: Iac00e2f86d160793d3217e00ddc5012202b3196a Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-07-05mb/google/brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSWentao Qin
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable the MPHY clock in the SKU2 configuration to ensure that S0ix functions normally. BUG=b:350609955 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04soc/amd/common/acpi/ivrs: use PCI_DEVFN macroFelix Held
Use the PCI_DEVFN macro to make the calculation of the ivhd->device_id value a bit clearer. TEST=Timeless build results in identical binary for Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b7949ad3524790e7d7d527c488a32e785f55bc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83343 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-04util/liveiso/nixos: Update to 24.05Felix Singer
Change-Id: I62dc3a7fd5b8aef467fc547015f23e41d3260122 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-04mb/google/lotso: Add hid report address for gt7986uKun Liu
Add hid report address for gt7986u. BUG=b:342932183 BRANCH=None TEST=Verify touchscreen work normal. Change-Id: I464c2691505083314528519f608108c8a31e6cc0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83201 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-04drivers/spi/acpi: Update generic property listKun Liu
Update generic property list for build test result fail https://qa.coreboot.org/job/coreboot-gerrit/259702/ BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iecd8573343706184dce5edfc12fe7a143390e0e9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83301 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-07-04mb/google/nissa/var/domika: Create a domika variantWisley Chen
This patch creates a new domika variant which is a Twin Lake platform. This variant uses Yavilla board mounted with the Twin Lake SOC and hence the plan is to reuse the existing yavilla code. BUG=b:350399367 BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I42c56770f8b8d6018592253d2bb16b8166eb5719 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04mb/google/brya: disable early EC sync for orisaAmanda Huang
Disable VBOOT_EARLY_EC_SYNC for all trulo boards. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83303 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-04doc/tutorial/part1.md: Remove trailing whitespaceMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ife87475d367c5491807215342536e3bb0fd15a45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83312 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdtShuo Liu
Domain device objects are created with HID/CID/UID/_OSC/_PXM Dynamic domain SSDT generation could benefit the support of SoCs with multiple SKUs, or the case where one set of codes supports multiple SoCs. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. GNR codes run with dynamic domain SSDT generation to fit for both GraniteRapids and SierraForest SoCs. TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03tests/drivers/efivars: Remove duplicated <limits.h>Elyes Haouas
Already included <types.h> is supposed to provide <limits.h>. See `Documentation/contributing/coding_style.md` section `Headers and includes` Change-Id: I945eeeeccb16851f64d85cf5c67ea6e256082e11 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-07-03Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"Maximilian Brune
This reverts commit 41fdb882f1f0c3cda41651c2e9c920580415a0dc. Reason for revert: The version downloaded does not match the version that is printed out when executing `iasl --version`. coreboot notices that and refuses to compile QEMU-Q35 mainboard. I tested it on 2 different PCs. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83296 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)Jan Philipp Groß
This is a rudimentary port of this board. It was done with Haswell Autoport, wherein some adjustments for Broadwell were made (Thanks to Angel Pons!). The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version 2.20 of the vendor firmware. Working: - Broadwell MRC.bin - S3 suspend and resume - All DIMM slots - Libgfxinit - HDMI-Out Port - DVI-I Port (including passive DVI to VGA adapter) - USB 2.0 Ports - USB 3.1 Gen1 - RJ-45 LAN Port - SATA3 6.0 Gb/s Connectors - m.2 PCIe SSD - mPCIe WiFi slot - x16 PCIe slot - USB 3.1 Gen1 Header - Front Panel Audio Connector - edk2 Not yet tested: - SATA Express 10 Gb/s Connector - HDMI-In Port - DisplayPort 1.2 - Optical SPDIF Out Port - PS/2 Mouse/Keyboard Port - USB 2.0 Headers Not working: - Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6: Add new mainboard) Special thanks to Angel Pons for guiding me through the process of porting this board and pushing it to Gerrit! Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82760 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03mb/google/rex: Set cnvi_wifi bluetooth companion deviceJeremy Compostella
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support 320Mhz Bandwidth Enablement per MCCPoornima Tom
Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support Bluetooth Regulator Domain SettingsJeremy Compostella
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This commit introduces a `bluetooth_companion' field to the generic Wi-Fi drivers chip data. This field can be set in the board design device tree to supply the bluetooth device for which the BRDS function must be created. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/asrock: Add Fatal1ty Z87 Professional (Haswell)Jan Philipp Groß
This port was done via autoport and subsequent manual tweaking. Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM! The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - both RJ-45 Gigabit LAN Ports - USB 2.0 Ports - USB 3.1 Gen1 Ports - both USB 3.1 Gen1 headers - HD Audio Jack (audio output) - all six SATA3 6.0 Gb/s connectors by Intel - all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061 - all three PCI Express 3.0 x16 slots - PCI Express 2.0 x1 slot - half mini-PCI Express slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection via jumper not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Front panel audio connector - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03mb/google/geralt: Replace GERALT_USE_MAX98390 with FW_CONFIG for TAS2563Rui Zhou
Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG, we remove GERALT_USE_MAX98390 from Kconfig. BUG=b:345629159 BRANCH=none TEST=emerge-GERALT coreboot TEST=Verify beep function through deploy in depthcharge successfully. Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-03mb/google/ovis/variants/deku: Add K3KL9L90CM-MGCT to RAM ID tableTony Huang
Add RAM ID for K3KL9L90CM-MGCT 0 (0000) BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/google/brox/var/lotso: Tune I2C frequency for 400 kHzJing Tong
Before: I2C0 - 401kHz I2C4 - 405kHz After: I2C0 - 392kHz I2C4 - 395kHz HW: Change R8409/R8411 to 33ohm. BUG=b:349743464,b:349735055 TEST=emerge-brox sys-boot/coreboot Test pass by EE Change-Id: I985837b1b80e973f148529b446905580c0f95e98 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-07-03soc/intel/xeon_sp/gnr: Support fast bootGang Chen
Fast boot will used pre-saved hardware configuration data to accelerate the boot process, e.g. DDR training is skipped by using pre-saved training data. Enable fast boot on cold and warm resets by default. Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03security/vboot: Set VBOOT_ALWAYS_ENABLE_DISPLAY if BMP_LOGOYu-Ping Wu
If BMP_LOGO is set, currently display_init_required() will always return 1, so that platform code will always initialize display. However, that information isn't passed to vboot, which may result in unnecessary extra reboots, for example when the payload needs to request display init (by vb2api_need_reboot_for_display()). Since there is already a Kconfig option VBOOT_ALWAYS_ENABLE_DISPLAY to tell vboot that "display is available on this boot", enable it by default if BMP_LOGO is set. BUG=b:345085042 TEST=none BRANCH=none Change-Id: I20113ec464aa036d0498dedb50f0e82cb677ae93 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-03mb/gigabyte/ga-h61m-series: Initial GA-H61M-S2P-R3 bringupPugzAreCute
Working: - Both DIMM slots - All Rear USB 2.0 ports - Integrated graphics (libgfxinit) - Realtek RTL8111F GbE - Flashing internally with flashrom (Note: Works from stock too due to Gigabyte not following Intel recommendations, confusing ME) - SeaBIOS (1.16.3) to boot Arch Linux Installer - EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer - Audio output (green jack, rear) - S3 suspend/resume - VBT Untested for now (i.e. should work, will eventually test): - EHCI debug - Front USB 2.0 ports - The other audio jacks - PCIe ports - Non-Linux OSes Untestable (i.e. cannot test due to unavailable hardware): - PS/2 port - Serial port - SATA ports Not working: - USB 3.0 ports: The on-board VLI VL805 does not have a flash chip, so its firmware needs to be loaded on each boot. However, documentation about the (chip-specific) firmware loading procedure is nowhere to be found. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. Change-Id: I106c195c890823f07227739c6b30133b996f6510 Signed-off-by: PugzAreCute <me@pugzarecute.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03soc/intel/common: Skip ME version log for Lite SKUSubrata Banik
This change skips the ME firmware version logging in print_me_fw_version() if the ME firmware SKU is detected as Lite SKU. The reasoning is that the RO (BP1) and RW (BP2) versions are already logged by the cse_print_boot_partition_info() function for Lite SKUs, making the additional log redundant. The check for the Lite SKU has been moved to print_me_fw_version(), where the decision to print the version is made, instead of in get_me_fw_version(), where the version information is retrieved. TEST=Able to build and boot google/rex. w/o this patch: [DEBUG] ME: Version: Unavailable w/ this patch: Unable to see such debug msg. Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-03soc/intel/cmn/cse: Make ME firmware version query function staticSubrata Banik
This change modifies the get_me_fw_version() function to be statically scoped within src/soc/intel/common/block/cse/cse.c, as it is only used by the print_me_fw_version() function in the same file. The function declaration is also removed from intelblocks/cse.h. The order of the function definitions in cse.c was also changed to be more logical, with the now static helper function get_me_fw_version() defined first, before it is used. TEST=Able to build google/rex. Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Conditionally disable ME status reportingSubrata Banik
This patch disables the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03drivers/intel/ish: Skip ISH version call if CSE sync is done by payloadSubrata Banik
This patch skips the ISH firmware version print when CSE sync is done by payload. The payload is responsible to dump the ISH version as ISH version resides into the CSE boot partition table. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Skip CSE version call if sync is done by payloadSubrata Banik
This patch skips the CSE firmware version print when CSE sync is done by payload. The payload is responsible to dump the CSE version. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE EOP configsSubrata Banik
Refactor CSE lite End-of-Post (EOP) configs to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot will skip initiating CSE EOP operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_SEND_EOP_EARLY - SOC_INTEL_CSE_SEND_EOP_LATE - SOC_INTEL_CSE_SEND_EOP_ASYNC - SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD BUG=b:305898363 TEST=Able to build google/rex. Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE lite configsSubrata Banik
Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-03Revert "Makefile.mk: Use Walloc-size GCC option"Felix Held
This reverts commit 6ab188ee6c99b1d9924b607d7e939d91e35014ec. This breaks the build using a slightly older toolchain that doesn't know this option yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bdc909c0e53b5353743dca521c963bbec792f7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83311 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-07-03tree: Use <console/console.h> only when usedElyes Haouas
Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-02Makefiles: Add site_local-target to run early in the buildMartin Roth
This double-colon target doesn't do anything unless it's implemented by another makefile. It's intended to be used only by the site-local makefile to allow it to run any necessary steps before the actual coreboot build begins. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I01f98c9cf8375bca21ab87f9becf66a25402c758 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-07-02mb/asrock: Add Z87M OC Formula (Haswell)Jan Philipp Groß
This port was done via autoport and subsequent manual tweaking. Special thanks to Nicholas Chin! This port would have never succeeded without his help. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection switch and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - USB 2.0 Ports - Vertical Type A USB 2.0 - USB 3.1 Gen1 Ports - HD Audio Jack (audio output) - Front panel audio connector (audio output) - RJ-45 Gigabit LAN Port - SATA3 6.0 Gb/s connectors - mSATA/mini-PCI Express slot - half mini-PCI Express slot - PCI Express 3.0 x16 slots (both) - PCI Express 2.0 x4 slot - PCI Express 2.0 x1 slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection Switch - Slow Mode Switch (locks the CPU at 800MHz) not (yet) tested: - IR header - COM Port header - Power LED header - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - Optical SPDIF Out Port not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. - Post Status Checker (PSC) Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-023rdparty/vboot: Update submodule to upstream mainFelix Singer
Updating from commit id 09fcd218: 2024-02-23 06:42:12 +0000 - (Makefile: Test compiler for -Wincompatible-function-pointer-types) to commit id b6f44e62: 2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10) This brings in 58 new commits: b6f44e62 futility: updater: Increase try count from 8 to 10 cfc87db2 OWNERS: Add czapiga eabf5784 OWNERS: Remove twawrzynczak and quasisec f8af818e host: Add stub implementation for pkcs11 key aaf4ecbb crossystem: Add support for Panther Lake gpiochip de89c5cd make_dev_ssd: allow ptracers to write proc/mem ffc9cc15 utility: Add vbnv_util.py for debugging b6174bdb futility: show: Print keyblock signature size and data size 6e39c99f Android: Add support for doing zipalign before doing apksigner ead73381 futility: flash: Enhance WP status reporting by adding more instructions c3368084 futility: modify private key validation to work for both local and cloud c22d72f8 futility: flash: Correct the output syntax of 32bit hex f423ae13 crossystem: Drop support for tried_fwb and fwb_tries fc5488c7 futility: flash: Correct the allowlist of options 16dede85 Revert "futility: Split load_firmware_image() into two functions for AP and EC" ded07831 futility: Try to load ecrw versions regardless of image type 7a685705 futility: Refactor code for --manifest f5ad0856 futility: Add more checks for incompatible arguments 05659d33 futility/updater_manifest: Warn about inconsistent RW versions 6720827b futility: Support ecrw version for --manifest daae7e56 futility: Split load_firmware_image() into two functions for AP and EC 40c77bba futility: Warn about inconsistent RW_FWID_A and RW_FWID_B versions c168ac8e tests/futility/data: Update bios_geralt_cbfs.bin with swapped ecrw 512648ae host/lib: Add cbfstool_file_exists() and cbfstool_extract() e37e6511 sign_official_build: add missing info keyword 2c0758b4 sign_official_build: loem support for firmware 016f6149 scripts/image_signing/swap_ec_rw: Always add ecrw.* as raw CBFS file b26c700a scripts/image_signing/swap_ecrw: Support ecrw.version 2e8d1003 tlcl: Add const qualifier to TlclTakeOwnership arguments 96b8674c host: stop installing unused image signing scripts 8da83c43 Android: Handle update certs using for hardcoded certs 4ca60534 scripts/image_signing: Add swap_ec_rw d30d6b54 make_dev_ssd: Remove logic choosing editor value 4cc5d090 futility/dump_fmap: Fix error message prefix for '-x' e7062a58 futility/dump_fmap: Exit with error if specified section is not found 4489dd09 scripts: Remove newbitmaps directory 8dcc82b0 host/lib/cbfstool: Redesign cbfstool_get_config_value() API 856fd693 Android: Hack for now to let things silently fail instead of erroring 28845c97 sign_uefi: Handle case where the crdyshim key does not exist 201244c3 sign_uefi_unittest: Refactor in preparation for more tests 702f8b53 tests: Add tests for cbfstool_get_config_value() 52a21327 Android: Add support for gcloud KMS in android signing 3310c49f tests/futility/test_update.sh: Use unique test names for IFD tests 493f7afc sign_gsc_firmware: add support for Nightly target 5c307cad keycfg: more consistent typo fix 11e4f60b image_signing: Add missing arg in sign_uefi_kernel 37c730d8 keycfg: handle arrays appropriately in key_config 59c37697 sign_uefi: Add detached crdyboot signature b66926e2 sign_uefi: Refactor the is-pkcs11 function for reuse 94aa8b80 image_signing: Pass crdyshim private key to sign_uefi.py 0ac99bcb sign_uefi: Stop signing crdyboot files with sbsign 6f6a6432 vboot_reference-sys: replace denylist with allowlist 73ebd8f8 vboot_reference-sys: add vboot_host pkg-config fallback 476282ef make_dev_ssd: Skip firmware validity checks on nonchrome 9330a65a vboot_reference: Add support for allowing overlayfs 48c8833f sign_official_build: remove cloud-signing aa70bb19 create_new_keys.sh: add --arv-root-uri 38d1af69 sign_official_build: Dedup calls to sign_uefi.py Change-Id: I14aaf1e1e230107e7bae60195c7e4684bf5a0533 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-023rdparty/fsp: Update submodule to upstream masterFelix Singer
The filename of the Elkhart Lake FSP binary changed in the FSP repository. It's unlikely that it will be renamed to the original name soon. Thus, update the filename in the coreboot repository. Updating from commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) to commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) This brings in 23 new commits: 800c857 Update Fsp.fd 41e4590 NEX AZB IPU24.4 (5254_00) FSP 0efd8a3 IoT RPL-PS PV (5045_47) FSP 196e3fe Update README.md 380afd8 Update README.md 5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP 22762e9 Merge branch 'master' of https://github.com/intel/FSP 8134dbd Elkhart Lake IPU2024.3 FSP 3819544 add required SECURITY.md file for OSSF Scorecard compliance a6ee963 Delete AlderLakeFspBinPkg.dec 9d819ea Deprecate Client/AlderLakeFspBinPkg f963690 Raptor Lake FSP C.1.C8.50 f67f9ef Raptor Lake FSP C.0.C8.50 68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP 6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP 8cf0372 IoT ADL-N MR4 (5061_00) e5ceb0b Merge branch 'master' of https://github.com/intel/FSP aada6a5 Elkhart Lake IPU2024.2 FSP 90d1d3b Update README.md 1a5a3ee Testing 61c069a NEX RPL-S MR3 (4445_03) FSP Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-02util/ifdtool: fix spacing issuesAlexander Goncharov
Ensure consistent spacing around colons in bit fields, operators, statements and function calls. Found by the linter (check-style). Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-01Makefile: Add symlink targets to helpMartin Roth
Also capitalize the first letter of each help line while I'm here. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I595265d53a5ecfeb5989075dd4ce23dbdf366c00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-07-01Makefile: update clean-symlink targetMartin Roth
This almost completely replaces the original clean-symlink target to remove links from site-local into the coreboot tree. Changes include: - Symbolic links removed are based on the EXTERNAL_SYMLINKS value of symlink.txt files under site-local. - Verify that there are site-local symlink.txt files to work on before doing anything. - Verify that the symlink.txt files reference links inside the coreboot directory. - Print out whether or not there are remaining symbolic links in the tree. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ife0e7cf1b856b7394cd5e1de9b35856bd984663c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-07-01nb/intel/sandybridge/chipset.cb: Add alias for `cpu_cluster`Angel Pons
Define a devicetree alias for `cpu_cluster` so that it can be referenced in C code as `DEV_PTR(cpu_bus)`. Change-Id: Id6ead3d98d8fc17cab44ecf0b2af60a23187e036 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-01commonlib/bsd/lz4_wrapper.c: Fix misaligned accessMaximilian Brune
Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Make the compiler generate code that adheres to natural alignment by fixing the LZ4_readLE16() function and creating LZ4_readLE32(). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01drivers/spi/acpi: Add generic property listKun Liu
The touchscreen vendor (Goodix) needs to use this value (hid-report-addr) in the touch driver, and this value needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table. BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01soc/nvidia: Remove unneeded white spacesElyes Haouas
Change-Id: Ifd19cdcfbdf0b01984e0db0aa880fdcb256663b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-01mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panelYang Wu
Add LCE_LMFBX101117480 MIPI panel for Wugtrio. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 12:41:13 +0000