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2023-03-23mb/asrock/b75m-itx: Set HDA pin configuration like vendor BIOSKevin Keijzer
While doing the initial port of this board, hda_verb.c was mainly put together by guesswork and borrowing the pinouts from similar boards. While it was mostly correct, not everything was tested properly. This change takes the values of vendor BIOS version P1.80, obtained by running `cat /sys/class/sound/hwC0D0/init_pin_configs` while booted from the vendor firmware. 7.1 channel audio and front panel audio are now also tested. Change-Id: I60b0f55c203f42b220f13cf943912f7428476792 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73935 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fabian Groffen <grobian@gentoo.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-23mb/hp/snb_ivb_laptops: Add HP EliteBook 2170p as 2570p variantBill XIE
Most of the code is taken from 2570p, adjusted with autoport, SuperIO from 8470p and inteltool, GPIO config from inteltool via autoport. The laptop works well under coreboot with SeaBIOS 1.16.1 payload, running Debian GNU/Linux with kernel 6.1.15. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I854104516d5b6fbd78ee2989197000a7dbb85136 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73856 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23mb/asrock/b75m-itx: Move subsystemid from NIC to PCIe root port 4Kevin Keijzer
As a follow-up to commit 1a591d0c4460 (mb/asrock/b75m-itx: Make NIC a child device below PCIe port 4), this change corrects the subsystemid being incorrectly applied to the Realtek NIC instead of the PCIe root port. Change-Id: Ib6fb8bf808132c008846d8ca9acde0eef277765c Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23mb/asrock/b75m-itx: Remove cpu_fan_tach_src from CMOS layoutKevin Keijzer
This board inherited cmos.default and cmos.layout from asrock/h77pro4-m, which has two CPU fan headers and a CMOS option to select which one will provide the tachometer source. However, the code for this was never implemented. Moreover, this board only has one CPU fan header, rendering the option useless. This change removes the option from cmos.layout and cmos.default. Change-Id: Ib4580e243781e2340af2cefb825f26ee896c2bd3 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73931 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23soc/intel/xeon_sp: Fix PCH IOAPIC IDPatrick Rudolph
FSP may program a different ID under certain circumstances. Read IOAPIC ID from hardware instead of using some define that might not reflect how hardware is configured. Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23nb/intel/snb: Abolish mainboard_should_reset_usb()Keith Hui
Of the 13 mainboards that implement mainboard_should_reset_usb() hook, all but one do the same: Stop MRC from resetting USB when resuming from S3 suspend. This hook turns out is only here to facilitate a USB reset workaround on samsung/stumpy for an old ChromeOS kernel which is no longer needed. Drop the workaround, the hook, and headers no longer used. roda/rv11/early_init.c is left with no useful code after this patch, so drop it entirely from both bootblock and romstage. Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23soc/intel/cmn/cse: Make heci_(send|receive) public functionsJeremy Compostella
Having these two functions public allow "asynchronous" HECI command implementation. Typically, these function can be use to implement an asynchronous End-Of-Post. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Successful compilation for brya0 Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-23soc/amd/mendocino: Remove GPP bridge to Bus BMartin Roth
The internal GPP bridge to bus B is not used on MDN, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4f95afd192c5b799b7a3e12650476b7933cdd118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-23soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC KconfigMichał Żygowski
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23mb/google/brya/var/taeko: Correct comments to prevent confusionJoey Peng
The PCIE RP 9 on taeko is for eMMC. Correct the comments to prevent confusion. BUG=b:271003060 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-23soc/intel: Rename IA common code module from `TOM` to `RAMTOP`Subrata Banik
This patch renames all references of `top_of_ram` (TOM) in IA common `basecode` module (for example: functions, variables, Kconfig, Makefile and comments) with `ramtop` aka top_of_ram to make it more meaningful and to avoid conflicts with Intel SA chipset TOM registers. BUG=Able to build and boot google/rex with the same ~49ms savings in place. Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23mb/google/skyrim: Re-enable hotplug for SDMartin Roth
It seems like the hotplug enable might be doing more than just enabling devices to be hot-plugged, so re-enable the feature for the SD card. Removing it from SD increased resume time and may have caused reboot issues for SD after resume. This is a partial revert of CB:73512 BUG=b:273620322 TEST=See resume time go down on Skyrim BRANCH=Skyrim Change-Id: I4814d4377d0ba8a1e9b308853b3e02a4a27bd8d5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73868 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-23mb/google/skyrim: Enable SPL fusing on frostflowFrank Wu
Enable Frostflow platform to send the fuse SPL (security patch level) command to the PSP. BUG=b:274028833 BRANCH=none TEST=FW_NAME="frostflow" emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Change-Id: I6437d5324877702f2f8b4c69d4c850543e1b74be Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73884 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-23intel/common/block/smm: remove return statements from void functionsYuchen He
To be consistent with other occurrences in soc/intel/common, remove the return statements of weak void funtions since they are not generally useful. Found by the linter. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-23mb/google/poppy/rammus: rework method get_wifi_sar_cbfs_filenameYuchen He
The return statement at the end of the method is never reached. Remove it. Also while at it, assign the return value of variant_board_sku() to ski_id while the variable declaration and make it const. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: If05df8934f68ffec9ad21c88394055f71d618133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-22x86/include/registers.h: macros should not use a trailing semicolonYuchen He
Macros should not use a trailing semicolons. Remove those from 'LONG_DOWNTO8' aswell as 'LONG_DOWNTO16' and add them at places where the macros are used. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I5ba01bc09f9a2d9ecd54014e27ec0a24c7297412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-22mb/google/skyrim: Remove todo about BT controller timeoutsMartin Roth
This will be tracked directly in the bug, so a code comment is not needed. BUG=263161283 TEST=none BRANCH=Skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4d5af35762354c8825d30f813098547a7e009e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73828 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-22security/tpm/tspi: Fix preram TPM log max entriesJeremy Soller
Pre-RAM TPM logs use a separate define for the max number of logs. This one fits into the 2 KiB region assigned to TPM_LOG in the CAR linker script. Change-Id: Idda08a33c4a29fcb50085ca93487585dedf11012 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-22soc/amd/*/acpi: assign proper boolean values in get_pstate_core_freqFelix Held
Assign true/false instead of 1/0 to the valid_freq_divisor bool variable in get_pstate_core_freq. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I92d0eb029c55f80a2027ff6d404c63ed84282750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add CXL memory into memory mapJonathan Zhang
If the host supports CXL, get proximity domain info from FSP HOB. The proximity domains may include both processor domains and CXL domains. Add header definition for proximity domain. Add CXL memory into memory map. Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: skip configuring VTD devJonathan Zhang
DPR should not be configured for VTD devices of other stacks for SPR-SP. Such processor(s) would be configured with SOC_INTEL_MMAPVTD_ONLY_FOR_DPR. Change-Id: Ib33b1b62f59a10d362c6585b1403490d4a1aedeb Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72616 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add NCMEM base/limit to map entriesJonathan Zhang
... instead of ME base/limit if the processor is configured with SOC_INTEL_HAS_NCMEM. Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flagJohnny Lin
This soc utility function can set cmos flag to enforce FSP MRC training. Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu
After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22drivers/intel/fsp2_0: Add support for FSP_ERROR_INFO_HOBRay Han Lim, Ng
Add a new Kconfig CONFIG_ENABLE_FSP_ERROR_INFO option to enable retrieval of FSP_ERROR_INFO_HOB from HobList created by FSP. Such a HOB could be generated by Intel SPR-SP FSP. This HOB data is defined in Intel®Firmware Support Package External Architecture Specification v2.1 Doc#611786-2.1. Change-Id: I812d1c22c1bbe5146630948ca6ca12c46ffd5504 Signed-off-by: Ray Han Lim, Ng <ray.han.lim.ng@intel.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22mb/google/hades: Add variant device treeEric Lai
Follow 03_16 schematic to add the device tree. BUG=b:272816611 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85a05fec816954fd3408feccae84e0b9860ecdc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73838 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-22soc/intel/elkhartlake: Increase BSP stack size by 1 KiB to 193 KiBMichał Żygowski
The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and coreboot's romstage requires ~1 KiB, but it is not satisfied currently. Increase the BSP stack size by the missing 1KiB for romstage like other SoCs do. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iddd4a4613bc174aec4331732371a27450225258c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22mb/msi/ms7d25/gpio.h: add spaces around bitwise or operatorYuchen He
To be consistent with other occurrences, add a space around the bitwise or operator. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I674311ae330789b75fe7d189ad0fddeae45efe02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-22mb/google/dedede/var/magolor: Add FW_CONFIG probe for EXT_VRMorris Hsu
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on magolor. BUG=b:223687184 TEST=emerge-dedede coreboot chromeos-bootimage and pass suspend_test and firmware_ConsecutiveBoot test Change-Id: I47ad313c4a14edb687913698986df9ece6cd721d Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73833 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-22mb/google/hades: Remove gspi from baseboard device treeEric Lai
GSPI is not used, remove it. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I55d3f5119bc502621bdeae63b3d1e4cf43582038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-21soc/intel/xeon_sp/spr/cpu: add missing device_match_mask in CPU tableFelix Held
Commit 6a6ac1e0b929 ("arch/x86/cpu: introduce and use device_match_mask") added the device_match_mask element to the cpu_device_id struct and uses it to be able to mask off for example the stepping ID when checking for CPU table entry that matches the silicon the code is running on. Commit 3ed903fda9cb ("soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code") added a CPU table that was missing the device_match_mask which results in this being 0, so the first entry of the CPU table would match for any Intel CPU which isn't the intended behavior. Also use CPU_TABLE_END instead of the final {0, 0, 0} array element. Likely all entries could be replaced by one entry that uses the CPUID_ALL_STEPPINGS_MASK instead of the CPUID_EXACT_MATCH_MASK, but that's out of scope for this fix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0be2e9fe3c31487c83c9b1cf305a985416760b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21nb/intel/haswell/pcie.c: Make UBSAN not complainAngel Pons
UBSAN complains about "shift out of bounds", likely because integer literals are signed by default and the result of the operation will shift into the sign bit, yielding a negative value. However, as the negative value is then casted to an unsigned type, it works anyway. To make UBSAN happy, make sure the two troublesome integer literals are unsigned so that there's no sign bit to shift into. Tested on out-of-tree Asrock Z97 Extreme6, UBSAN now dies elsewhere. Link: https://ticket.coreboot.org/issues/449 Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72806 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21mb/asrock/b75m-itx/devicetree.cb: Fix errors for PNP 2e.b and 2e.308Kevin Keijzer
Currently, cbmem shows five errors when running `cbmem -c -B +ERROR`: Resource didn't fit!!! PNP: 002e.308 60 * size: 0x8 limit: fff io Resource didn't fit!!! PNP: 002e.b 62 * size: 0x2 limit: fff io PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.308 60 io size: 0x0000000008 not assigned in devicetree These changes resolve all the warnings by setting proper io and irq values. Change-Id: I5f669e2a1bd1338010a5d801a1d2a48ae11b3c89 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73815 Reviewed-by: Fabian Groffen <grobian@gentoo.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-21soc/intel/apl: Fix programming temporary MTRR on GLKArthur Heymans
Programming MTRR happens later in the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath. fast_spi_cache_bios_region() assumes an existing MTRR solution from x86_setup_mtrrs_with_detect(). This fixes a problem introduced by 829e8e6 "soc/intel: Use common codeflow for MP init". Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21arch/arm64/include/armv8/arch/barrier.h: Add spaces around colonsYuchen He
The linter requests spaces around colons. Add them. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I46d11666126dd8585ef7d4bab68a5b4b01fb7c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73748 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21soc/amd/mendocino: Remove 2 unused PCIe functionsMartin Roth
Mendocino only has 4 PCIe lanes exposed, so there's no need for 6 PCIe functions to control them. These functions just show up as leftover devicetree devices. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b801d82f085d77706b8053a8fc9728101f155e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-21mb/asrock/b75m-itx: Disable unused ME KT PCI deviceFabian Groffen
Resolve this message: [INFO ] PCI: Static device PCI: 00:16.3 not found, disabling it. The ME KT is very unlikely to exist on a consumer device as it is only used in combination with Intel AMT. AMT comes only with the corporate ME variant, whilst this mainboard is consumer grade. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I15dd586db9cb4b2dd615b7bf78665df86a32cb9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73829 Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-21mb/google/skyrim: Remove TODO about moving AMDFWMartin Roth
We're not going to move the AMDFW binary around at this point, so get rid of the TODO. BUG=None TEST=None BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If802c3ee19f4e6a3a74da49bbda55f6a89fa8060 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73827 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-03-21mb/google/skyrim: Delete PSPP TODOMartin Roth
Because Mendocino doesn't support PCIe Gen4, PSPP on this platform does not save any power, so leave it disabled. BUG=273889287 TEST=None BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1a1c6692cd0a44469a35582042b92eeec31073fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-21util/amdfwtool: remove unused union from embedded_firmware structFelix Held
Since commit 2f6b7d557d97 ("amdfwtool: Move the filling of table headers into functions"), the combo_psp_directory union element in the embedded_firmware is unused and the new_psp_directory element is used in all places, so replace the union of new_psp_directory and combo_psp_directory with just the new_psp_directory struct element. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-21soc/intel/common/block/acpi: Support more than 255 coresPatrick Rudolph
Replace the legacy ACPI Processor() object as it only supports 8bit IDs and thus no more than 255 cores. Use the new ACPI Device() object that supports more than 255 cores. Test: - Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running 384 CPU cores in total. - Verified on Intel ADL RVP with 20 cores that Linux 5.15 is still working without errors. Change-Id: I309c06b6824704c84fd16534655334a6f269904a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-03-21mb/prodrive/atlas: Configure PCIe CLKREQMaximilian Brune
Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#. If the GPIO is set to native mode for a device, which does not support SRCCLKREQ#, then during RTD3 exit link would not be established. Because controller samples the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS as controller detects SRCCLKREQ# as de-asserted. As a workaround the Pins must not be configured in Native Mode (CLKREQ native function). Therefore here they are not configured at all. source: 689882 (intel document ID) So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such. That workaround suggestion however also brought a patch to FSP, which in turn causes the same bug (even if SRCLKREQ are not configured). Usually in order to make use of root port power saving features (e.g. clock gating), the Root port must either be disabled or a CLKREQ Pin must be configured. The patch however removed that check before enabling power management for the rootport. Workaround (until FSP is fixed): pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the FSP UPDs. That will cause FSP to configure the CLKREQ Pin and enable power management for said rootport, but it will not crash on L1 entry/exit. That has been done on the Atlas board (as workaround) for a short period of time (before applying FSP Fix) like this: // RP 5 (the rootport you want to fix) - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // e.g. choose a clkreq pin that is not routed out - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent the same issue, but for CPU root ports. If not done the following will happen in coreboot: [DEBUG] PCI: 00:06.2 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:06.2 [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] PCI: 02:00.0 [1344/5410] enabled [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] ASPM: Enabled L1 [EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting [EMERG] Code: 0 eflags: 00000046 cr2: 00000000 [EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000 [EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100 [EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56 [EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If2acdc16f37cdae0292f55d210b058f82179bfb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-21mb/intel/adlrvp: Enable onboard GBEPatrick Rudolph
The ADL RVP has an i219 PHY connected to the PCH internal MAC. Enable it to have working ethernet on the board. Test: Added GBE region and verified that the PCI device 00:1f.6 is working. Change-Id: I2ca1af00ae4564a04f5388cd3734bb735d87352e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-21mb/siemens/mc_ehl4: Limit PCIe root port #4 and #5 speed to Gen 1Mario Scheithauer
Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3) and #5 (00:1c.4), the speed must be limit to Gen 1. BUG=none TEST=RX signal measured with oscilloscope Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21soc/intel/elkhartlake: Make PCIe root port speed limit configurableMario Scheithauer
In cases where there are limitations on the connected device behind the PCIe root port it can be necessary to limit the speed. The FSP parameter 'PcieRpPcieSpeed' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21mb/siemens/mc_ehl4: Enable PCIe devicesMario Scheithauer
Correct the remaining PCI devices, differing from the ehl1 mainboard. Change-Id: Ie09188b72a62c4d5cba2fcda6f60f3bc0098633e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21soc/intel/alderlake/vr_config: Add i3-1220PEPatrick Rudolph
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the vr_config table. Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-20soc/amd/mendocino: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic489b8e1332dde2511647c065ccbdef541bcbcc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20soc/amd/cezanne: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If92a4773c669ac2df45396eee52f6de780adbdca Reviewed-on: https://review.coreboot.org/c/coreboot/+/73644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20soc/amd/picasso: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. TEST=The coreboot-generated SSDT containing the P state packages stays identical on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8dc293351f9941cfb8a9c84d9fb9a4fd76361d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20mb/asrock/b75pro3-m/devicetree.cb: Fix errors for PNP 2e.308Fabian Groffen
[ERROR] PNP: 002e.308 60 io size: 0x0000000008 not assigned in devicetree [ERROR] ERROR: Resource didn't fit!!! PNP: 002e.308 60 * size: 0x8 limit: fff io Configure GPIO pins like asrock/h77pro4-m, this resolves the error and makes CPU-fan readings work. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: If717d046d9f60ca66d1e33db59ad67d23c393376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-20mb/asrock/b75pro3-m/devicetree.cb: Silence errors for PNP 2e.bFabian Groffen
[ERROR] PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree [ERROR] PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree Set them to zero. This is also what the values are set to using vendor firmware 1.90. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ide5980224f042e3da289aa28a18042ee8505d943 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73812 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-20mb/asrock/b75pro3-m: Disable unused ME KT PCI deviceFabian Groffen
Resolve this message: [INFO ] PCI: Static device PCI: 00:16.3 not found, disabling it. The ME KT is very unlikely to exist on a consumer device as it is only used in combination with Intel AMT. AMT comes only with the corporate ME variant, whilst this mainboard is consumer grade. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ie1f0bad276f5c124d8d52772330982bf1342c72e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-20soc/intel/meteorlake: Enable GPIO IOSTANDBY configurationSubrata Banik
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. TEST=Able to build and boot google/rex. GPIO debug print is showing GPIO PAD config DW1 bit[14:17] are getting programmed. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-20soc/amd/mendocino: Consume fsp misc_data hobJason Glenesk
Provide support function to query fsp misc_data hob and return smu reported power and thermal limit. BUG=b:253301653 TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in the hob. Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-20mb/google/rex: Enable USB camera powerIvy Jian
Add enable_gpio for USB power resource BUG=b:273891168 TEST=Able to detect USB CAM Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I08ebe560c8b75c8b590c889b7b90dbe678318d2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-20mb/google/skyrim/var/winterhold: Update DPTC settings for final versionEricKY Cheng
Follow thermal team's request on b/248086651 comment#32. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651,b:241180483 TEST=emerge-skyrim coreboot Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-19soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SPTim Chu
Intel SPR-SP chipset has EBG instead of LBG. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959 Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang
It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/mtl: Choose serial msg `log_level` based on DIMM countSubrata Banik
This patch modifies the serial msg log_level at runtime to highlight an ERROR if the DIMM count is zero. It would help to draw the attention while parsing the serial msg and catch any underlying issue. TEST=Able to see ERROR msg while booting google/rex with FSP v3064 Without this patch: [DEBUG] 0 DIMMs found With this patch:     [ERROR]  No DIMMs found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19mb/google/rex: Move BOARD_GOOGLE_BASEBOARD_REX to Kconfig.nameEric Lai
Align project style with other chrome projects. TEST=built FW not changed Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icfd1d274216d387cab6feb68afa49fc63c8c52e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-19mb/google/rex: Add DRIVERS_GENESYSLOGIC_GL9755Eric Lai
Rex uses GL9755 and miss select the driver. BUG=b:273906526 TEST=SD card is functional. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I674b052689c80873e8a3b295d15788f3a93f0b82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-19soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks
Some MSRs used in SPR code are common among currently supported Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs which have changed are added to SPR's soc_msr.h. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-18mb/asrock/h77pro4-m: Use VBT provided by Linux' debugfsMichael Büchler
The current VBT causes problems with Windows 10. Once the Intel driver is used instead of the generic graphics driver, the display turns off although the system keeps running normally. Linux has no issues. It had been extracted from the vendor video BIOS, which in turn had been extracted from the vendor firmware. This change replaces the VBT with one that was dumped through debugfs and the drm/i915 driver in Linux, booted from the vendor firmware at version 2.10 (beta). It fixes the issue with the Intel graphics driver on Windows 10. Change-Id: Icbb3950b37dad5ed308f3bafb73b71859227d26b Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17util/liveiso: Move NixOS configs to subdirectoryFelix Singer
Move the NixOS configuration into a subdirectory so that configurations for other distros can be added as well. Change-Id: I0462c1a6541878c973be4302c5c5e9e9bfaed2a6 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-03-17Makefile.inc: fix multiple jobs build issueMichał Żygowski
Certain C source files for coreboot stages require fmap_config.h to be present. When building coreboot using multiple jobs the dependency is not always satisfied due to race condition and results in make error. Work around it by adding fmap_config.h to stage C deps. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a70beedf2eb1c018c5ff98163904253f9a87a61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69819 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-03-17Update arm-trusted-firmware submodule to upstream masterElyes Haouas
Updating from commit id 9881bb93a: 2022-11-21 19:12:00 +0100 - (Merge "docs(spm): update threat model" into integration) to commit id 4c985e867: 2023-03-14 19:53:19 +0100 - (Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integration) This brings in 547 new commits. Note: commit id 1f49db5f solves the "LOAD segment with RWX permissions" error when binutils 2.39 is used. Change-Id: I35355040c6958d470d78002048e78a06fd7f6f02 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73735 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-17soc/intel/alderlake: Hook the VT-d DMA protection optionMichał Żygowski
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake/hsphy.c: Handle case with DMA protectionMichał Żygowski
The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTDMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17intelblocks/vtd: Add VT-d block with DMA protection APIMichał Żygowski
Add new common block with VT-d/IOMMU support. The patch adds an option to enable DMA protection with PMR. However the payload and OS must support VT-d in order to properly handle I/O devices. TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-03-17vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064Subrata Banik
This patch updates the Memory Hob Info data structure as per FSP v3064 source code change. BUG=b:273894357 TEST=Able to see `smbios type 17` table while booting google/rex. Without this patch: [DEBUG] 0 DIMM found With this patch: [DEBUG] 8 DIMM found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-17mb/google/nissa/var/uldren: Create RAM ID tablevan_chen
DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3KL6L60GM-MGCT 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) K3KL8L80CM-MGCT 2 (0010) H58G56BK7BX068 2 (0010) BUG=b:270103716 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia53c2be2ec606f42ac8bca06103b028e62ae6dbc Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-03-17mb/google/nissa/var/yavilla: Generate SPD ID for supported memory partsTony Huang
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56BK7BX068 1 (0001) MT62F1G32D2DS-026 WT:B 1 (0001) K3KL8L80CM-MGCT 1 (0001) H58G66BK7BX067 2 (0010) MT62F2G32D4DS-026 WT:B 2 (0010) K3KL9L90CM-MGCT 2 (0010) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I82919919ec33d6bf9d86132490df754873b5df88 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-17qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLibSudheer Kumar Amrabadi
This patch passes a hint flag to QcLib on Lazor boards to tell it to limit the DDR frequency for certain memory parts (8GB Hynix) to work around a board-specific stability issue. BRANCH=trogdor BUG=b:267387867 TEST=Validated on qualcomm sc7180 development board Change-Id: I45915cf93d2a57ff0c9710f2ac36dfb665eff1c6 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2023-03-17mb/google/brya: Create yavilla variantTony Huang
Create the yavilla variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVILLA Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-17mb/google/brya/var/omnigul: Update RAM ID tableJamie Chen
Add new ram_id:0010 for Micron MT62F1G32D2DS-023 WT:B. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H58G56BK8BX068 2 (0010) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:273138520 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Idc08624469590096047e5f77fb2e4ffb733f09ec Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73726 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-03-17mb/google/skyrim/var/crystaldrift: Add 1 Micron parts to RAM ID tableYunlong Jia
Add new memory MT62F2G32D4DS-026 WT:B to replace H9JCNNNBK3MLYR-N6E． Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) MT62F2G32D4DS-026 WT:B 3 (0011) K3LKBKB0BM-MGCP 4 (0100) BUG=b:273177939 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I545bd8d9f88e7b3055acef4066769e6fcb766cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73681 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-16arch/x86/ioapic: Print IOAPIC ID for GSI #0Jay Patel
Print IOAPIC ID for GSI #0 in logs, as part of IOAPIC initialization. BUG=None TEST=Confirmed "IOAPIC: ID = 0x00" printed in logs. Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: I8d8e94fe623795d059ec2abbb3319b60fd80f5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/73707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-03-16mb/google/brya/var/taniks: Remove unused temp sensor settingJoey Peng
Rwmove temp sensor 3 for taniks since we do not use it. BUG=b:265075696 TEST=emerge-brya coreboot, flash to DUT and will not see error messages Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-16amdfwtool: Print which combo entry is being processedZheng Bao
Change-Id: I9e83a3ac56d5c42d8d6839cc4d961adf0b656fb5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73725 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16mb/intel/mtlrvp: Add new MTL-P board variant for MCHP1727Harsha B R
This patch will add new board variant to enable MCHP1727 EC Card for MTL-RVP BUG=b:262800416 BRANCH=none TEST=check if you can observe MEC EC option as part of make menuconfig. Able to boot to ChromeOS with Microchip EC. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie0d3c37bcab5e4b90a131e17996c4b6dcbae7d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-16amdfwtool: Remove meaningless double parenthesesZheng Bao
Change-Id: I4a9192c55d63531621dd7bc49f1ead7f58dff893 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-16amdfwtool: Check combo_index before checking the combo_configZheng Bao
Otherwise Checking combo_config[++combo_index] causes Out-of-Bounds access. Change-Id: I50d466ee98edfb18c01fc7ba43e929640b33c7c1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73647 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16amdfwtool: Add asserting before accessing array combo_configZheng Bao
Change-Id: Ia98fdbee4c4005562662313ebe2478d0aeb879bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73724 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16mb/google/brask/var/aurash: Allow USB2/3 wakeups to (un)plug events in dtZoey Wu
BUG=b:271373437 BRANCH=none TEST=Verify USB-A device could wake up Aurash. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I67fc02d6c5660e0e3d1ab95bbda8ace1dc14b524 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73414 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15mb/google/rex: Add Hayden Bridge (HB) to USB_DB FW_CONFIGSubrata Banik
This patch increases FW_CONFIG for USB_DB to 3-bits. BUG=b:273346973 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib07ba1d54e7f7e2b09a99438529e503d9c9edb7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-15mb/google/dedede: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:268377440 BRANCH=firmware-dedede-13606.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I24f929ae60a406d0091956dc6cab3e2876ca23e9 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15mb/google/rex: Configure _DSC for camera devicesJamie Ryu
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:268607999 TEST=Build and boot rex proto1 to OS and verify privacy LED behavior. Change-Id: Ife849f7407b02867ddb992d7eebb08b0b44aecc8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.cJohnny Lin
With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore should be used. Therefore we use uncore_acpi.c (instead of nb_acpi.c) going forward. Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-15soc/amd/mendocino: MP2 firmware isn't needed in the RO imageMartin Roth
The MP2 firmware doesn't do anything useful when booting into recovery mode, so don't include it in the RO image if vboot is enabled. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5afbf7e9e730e6951c416f3a3ca75f69a22099cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/73660 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/amd: Print amdfwtool debug info if V=1Martin Roth
When doing coreboot builds, we can set V=1 to see all of the make info printed as the compile is happening. Use this flag to set the debug flag for amdfwtool so it doesn't have to be enabled separately. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b05cbc9f9b540a174db479822af657cf35733de Reviewed-on: https://review.coreboot.org/c/coreboot/+/73658 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-15soc/amd/common: Ignore * in PSP dependency generationMartin Roth
The regex getting rid of lines containing a '*' didn't match anything in any configs, so get rid of it. There's nothing in the amdfwtool dataparse.c file that would match it either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I05aaf46cfb479cebab9234a47574073335984a5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15soc/amd/common: Update PSP dependency generationMartin Roth
After adding the ability to add paths into the amdfw.cfg file for the amdfwtool, the dependency generation needs to be updated to not add the firmware location in front of those values. This also allows us to filter out the MP2 binaries as dependencies based on whether or not the Kconfig value is set. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a9b9c8246808dc60020a32a7d9d926bc5e57ccd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15util/amdfwtool: Update config parser to accept full pathsMartin Roth
This allows individual components to be placed in a location other than what is specified by the FIRMWARE_LOCATION line. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a83e52d081a5909d54eacc575dd2b40b09e4038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-15mb/google/skyrim: Do not pass recovery APCBKarthikeyan Ramasubramanian
If recovery APCB is not passed, amdfwtool will build amdfw*.rom with AMD_BIOS_APCB_BK entry pointing to the same offset as AMD_BIOS_APCB entry. This will help to save 40 KiB flash space in each FW slot. On ChromeOS, this means saving ~120 KiB flash space. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Change-Id: Ib3bbc1eededae20b2cd48f514722a207c46536a0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73662 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15util/amdfwtool: Support not passing recovery/backup APCBKarthikeyan Ramasubramanian
If Recovery/Backup APCB is not passed, then AMD_BIOS_APCB_BK entry is not populated. But PSP expects that bios directory entry to be populated. Also on mainboards where both APCB and recovery APCB are same (eg. Skyrim), 2 copies of the same APCB are added to amdfw*.rom. Update amdfwtool to support not passing recovery/backup APCB. If the recovery APCB is not passed, then populate AMD_BIOS_APCB_BK entry and make it point to the same offset as AMD_BIOS_APCB entry. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Ensure that the device can enter recovery mode. Perform multiple suspend/resume cycles. Change-Id: I031ba817573cd35160f5e219b1b373ddce69aa6b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73661 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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