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The Agesa wrapper and UDELAY_TIMER2 define their own timer functions,
so don't shove in UDELAY_IO
Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This code used a special case for checksum calculation to
prevent the century byte from messing things up, since
writes "sometimes" didn't happen.
That should be stable now, so the special case isn't necessary.
Downside: On century rollovers (ie. 1999-12-31, 2099-12-31)
CMOS will be reset to the defaults.
Change-Id: Ibe589a1ec953b7b3ba39be30cebd9fc2b27326ae
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1870
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This ensures that there's only one disable/enable cycle for
the entire rewrite instead for every single byte.
Change-Id: Ic06e6dcb08976d158ff784660838c0fbad875176
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In principle this isn't necessary. However there's a byte (or several)
outside the first 14 bytes that are part of the RTC, and require
locking (century/altCentury).
Since their location is mostly unknown, guard writes properly.
Change-Id: I847cd4efa92722e8504d29feaf7dbfa5c5244b4e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1868
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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nvramcui is a small libpayload based utility that provides
an interactive CMOS editor for pre-boot environments.
Change-Id: I514b8a7682f89d242d1b31b6907cc6bff34da4bf
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1871
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If they come from the build system, file names might be guarded in
quotes, which confuses make. Drop them here.
Change-Id: Ice0d3c4bc2c45a3f121a85e1b9f5f6420c5761d5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fix side-effects of name translation, treat original name as const.
Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Deletes unused file:
src/northbridge/amd/agesa/family15tn/bootblock.c
Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1843
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1879
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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flex is needed by acpica. This patch makes the build fail early
instead of after gcc has been compiled, if flex is not there.
Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1860
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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intel_irq_routing_table is a local structure that should not be used
globally, because it might not be there on all mainboards.
Instead, the API has to be corrected to allow passing a PIRQ table in
where needed.
Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1862
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Some boards selected GENERATE_ instead of HAVE_
Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1841
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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- move VGA handling options into devices/Kconfig
- make Devices a top level menu
- move some options "closer" to the code they control
Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1840
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET
are not likely to go away any time soon, so let's not keep them
in Kconfig.deprecated_options but move them close to the code they
control.
Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1839
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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It's only mentioned in Kconfig and never set nor used.
Change-Id: Icc0ac56ae7b325a9e93ed5cdce9dc4b7bab43140
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1838
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.
Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Add mainboard_smi.c from arch/x86/Makefile if it's there
- Add mainboard's chromeos.c from the chromeos Makefile
Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1835
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch is the beginning of a Kconfig cleanup series
- drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it
exists in the mainboard directory
- drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig
if it only defines the defaul value of 0
- Add mptable.c, fadt.c, reset.c and ssdtX.asl when they
exist, not based on some Kconfig magic
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200
Reviewed-on: http://review.coreboot.org/1832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We had mixed virtual and physical pointers in struct sysinfo_t. Some
being virtual by accident which led to problems when we tried to
reinitialize lib_sysinfo after relocating FILO (to get intentionally
virtual pointers valid again). I guess this didn't cause much trouble
before, as lib_get_sysinfo() was always called with physical addresses
being equal to their virtual counterparts.
For FILO, two possibilities seem practical: Either, have all pointers in
struct sysinfo_t physical, so relocation doesn't hurt. Or, have all
pointers virtual and call lib_get_sysinfo() again after relocation.
This patch goes the latter way, changing the following pointers for
situations where virtual pointers differ from physical:
.extra_version
.build
.compile_time
.compile_by
.compile_host
.compile_domain
.compiler
.linker
.assembler
.cb_version
.vdat_addr
.tstamp_table
.cbmem_cons
.mrc_cache
We could also just correct the accidentally virtual pointers. But, IMO,
this would lower the risk of future confusion.
Note 1: Looks like .version gets never set.
Note 2: .option_table and .framebuffer were virtual pointers but treated
like physical ones. Even in FILO, this led to no problems as
they were set before relocation.
Change-Id: I4c456f56f049d9f8fc40e62520b1d8ec3dad48f8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1855
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Libpayload uses the linux kernel's config style, where CONFIG_* defines
don't get written for unset tristates.
Change-Id: I3f832cf86bca9a1e153d96af4bf6434a19eba2f6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1847
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The board incorrectly overrides the southbridge hook, so use the
new mainboard hook instead. This change also activates the actual
southbridge hook to enable decode of complete 4 MB flash memory region.
Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1831
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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It's a bool, not a number
Change-Id: I70d52c6af6703101dbd534970ec65275902a283d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1842
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The board was broken for use with CONFIG_PCI_OPTION_ROM_RUN_YABEL.
Change-Id: Ia57d630143386fe637af83b9e7345d0d3750b089
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1854
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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YABEL's version of mainboard_interrupt_handlers() was hidden behind an
inline stub. This fixes it.
Change-Id: Ie53424a8ce074e93a720c0ef94cb39994cacd023
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Some time ago our CMOS checksum algorithm was changed under the topic:
Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
Here is another copy of the algorithm that had to be updated.
Change-Id: I58659c7b8a89c89c76efdff405ee0620e7302277
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1852
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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uhci_reset() differs in semantics compared to the other HCI's reset()
implementations. uhci_reset() does some initialization work after a
controller reset. So move the initialization part to a new function,
uhci_reinit(), which get's exported through a new entry in hci_t:
hci_t.init().
Warning: This breaks code that relies on the current, special,
counterintuitive behaviour of uhci_reset(). If one wants a working host
controller after calling hci_t.reset(), he should call hci_t.init()
afterwards.
Change-Id: Ia7ce80865d12d11157645ce251f77f349f8e3c34
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1851
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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When ohci_reset() was implemented, OHCI controllers stopped working
since the stub ohci_reset() is called at the end of ohci_init().
This is fixed by removing the call. To prevent further problems the call
to the xhci_reset() stub is removed, too.
Change-Id: If89825c8e6caf40f7f4fe078e8b2e90054a54ba2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1850
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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All shutdown() implementations but ehci_shutdown() free the hci_t
structure. This seems correct and the reference to the hci_t shouldn't
be used after shutdown(), so do it in ehci_shutdown(), too.
Change-Id: Ie3506d769e73007735f3211710734a5f0107e43a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1849
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The semantics of the controller functions, start(), stop(), reset() and
shutdown(), are not self-explanatory which let to some confusion. At
least the reset() functions of the different host controller drivers
were implemented following different interpretations. Let's make the
intended behaviour of these functions clear.
The stated inconsistencies will be addressed in following commits.
Change-Id: Id2e300f65c21039218b6ba3f87c0fcd4f0dda0a8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1848
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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FILO can use this as offset to enumerate AHCI and its own IDE
devices together.
Change-Id: I57380e7bd1df6db5c882427e9a34d068f4348fb2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1846
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ifdec69ca46ba8cbd3eb154d8f4af4b3cafa8019d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1805
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1834
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The VIA chipsets CX700, VT8623 and VX800 required to be
configured with real mode option rom code enabled. This
patch fixes the issue and drops some unneeded header files.
Change-Id: I0d8a3f8f99c2eacec7666f08f85b99f09c06af84
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1833
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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We moved GNVS to it's own section, but forgot to tell the cbmem code
about it. This is purely cosmetical, but add it anyways.
Change-Id: Icb3788c0325ea79cc1efff4a876412d07da7936e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1782
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The search for save state was comparing the entire RAX
value when it needs to just operate on the bottom byte
so it can find the GSMI command in bits 7:0 but not the
extended command code in bits 15:8.
Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1774
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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At boot time when the ACPI tables are created and the location
of GNVS is determined then save that address for resume time.
This also sets the values of USB charging in S3/S5 to the expected
default values for Stout/Butterfly that were not set correctly.
Change-Id: I9b94b868aa6e81aced06c0262cc2697ad4faf1e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1768
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Instead of hijacking some random memory addresses to
relay the GNVS pointer to SMM we can use EBX register
during the write to APM_CNT register when the SMI is
triggered.
Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1766
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Using global variables with the TSEG is a bad idea because
they are not relocated properly right now. Instead make
the variables static and add accessor functions for the
rest of SMM to use.
At the same time drop the tcg/smi1 pointers as they are
not setup or ever used. (the debug output is added back
in a subsequent commit)
Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1764
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is currently used by the ELOG GSMI interface but is a
good way to pass data to SMM so move the current searching code
to a separate function and make it a bit more versatile with the
checks it does to find a match so it can be used in other
situations.
Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1763
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The SMM GNVS pointer is normally updated only when the
ACPI tables are created, which does not happen in the
resume path.
In order to restore this pointer it needs to be available
at resume time. The method used to locate it at creation
time cannot be used again as that magic signature is
overwritten with the address itself. So a new CBMEM ID
is added to store the 32bit address so it can be found
again easily.
A new function is defined to save this pointer in CBMEM
which needs to be called when the ACPI tables are created
in each mainboard when write_acpi_tables() is called.
The cpu_index variable had to be renamed due to a conflict
when cpu/cpu.h is added for the smm_setup_structures()
prototype.
Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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If the PEI System Agent doesn't run PCIe initialization, the PEG
clock gating will not be setup. Add the PEG clock gating when
pei_data->pcie_init is 0.
Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The IvyBridge reference code does some slow and
extensive PCIe init that we do not need on Link.
Hence, add a flag to disable/enable running that
init code from coreboot.
NMode was used during bringup. We'll switch
the setting back to auto, to let MRC decide the right thing.
Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1826
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This will enable DDR3 1.35V support for memory training in
the reference code. It requires the board to be setup for
1.35V with whatever board-specific GPIOs are available.
Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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I added a comment to the pei_data.h to remind users about
how the OC pins are mapped.
Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1824
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Let memory initialization code use the coreboot romstage console. This
simplifies the code and makes sure that all output is available in
/sys/firmware/log.
The pei_data structure is modified to allow passing the console output
function pointer. Romstage console_tx_byte() is used for this purpose.
Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1823
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Updating microcode on several threads in a core at once
can be harmful. Hence add a spinlock to make sure that
does not happen.
Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1778
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This prepares the way for vboot to inform coreboot when it needs the VGA
Option ROM loaded. Coreboot can't always know when it's needed (with
keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not).
By the time we get to U-Boot, it's too late, so we need two extra bits - one
for vboot to tell coreboot to load the Option ROM and another for coreboot
to let vboot know it's been done.
This change sets up the communication, but doesn't act on it just yet.
Even with this CL we always load the VGA Option ROM, so there's nothing to
test. There should be no user-visible change.
Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: http://review.coreboot.org/1822
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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ChromeOS' top of the tree u-boot expects coreboot to export information
about option ROM status (started/not started). Stumpy and Lumpy were
left behind and are not exporting this information. This CL fixes the
problem.
Change-Id: Id90035bd76ab177e4fc269efc2b74f15f641c77d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1713
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Fix GPIO exporting for new Vboot for oprom-matters GPIO
and to make the power button static.
Change-Id: Ic042c428a1d43512228c686121fa057d876606e1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Several small improvements of the stack checking code:
- move the CPU0 stack check right before jumping to the payload
and out of hardwaremain (that file is too crowded anyways)
- fix prototype in lib.h
- print size of used stack
- use checkstack function both on CPU0 and CPU1-x
- print amount of stack used per core
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Test: Boot coreboot on Link, see the following output:
...
CPU1: stack: 00156000 - 00157000, lowest used address 00156c68,
stack used: 920 bytes
CPU2: stack: 00155000 - 00156000, lowest used address 00155c68,
stack used: 920 bytes
CPU3: stack: 00154000 - 00155000, lowest used address 00154c68,
stack used: 920 bytes
...
Jumping to boot code at 1110008
CPU0: stack: 00157000 - 00158000, lowest used address 00157af8,
stack used: 1288 bytes
Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df
Reviewed-on: http://review.coreboot.org/1787
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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In hardwaremain() we can't add timestamps before we actually
reinitialized the cbmem area. Hence we kept the timestamps in
an array and added them later. This is ugly and intrusive and
helped hiding a bug that prevented any timestamps to be logged
in hardwaremain() when coming out of an S3 resume.
The problem is solved by moving the logic to keep a few timestamps
around into the timestamp code. This also gets rid of a lot of ugly
ifdefs in hardwaremain.c
Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1785
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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For reasons of security and testing we want to be able to
enable/disable ME section locking through a config option.
Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1798
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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- drop changelog and add license header instead
- 80+ character fixes
- make stacks array static because it's not used externally
- rename copy_secondary_start_to_1m_below()
Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1821
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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This addition is in support of future multicore support in
coreboot. It also will allow us to remove some asssembly code.
The CPU "index" -- i.e., its order in the sequence in which
cores are brought up, NOT its APIC id -- is passed into the
secondary start. We modify the function to specify regparm(0).
We also take this opportunity to do some cleanup:
indexes become unsigned ints, not unsigned longs, for example.
Build and boot on a multicore system, with pcserial enabled.
Capture the output. Observe that the messages
Initializing CPU #0
Initializing CPU #1
Initializing CPU #2
Initializing CPU #3
appear exactly as they do prior to this change.
Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/1820
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
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There are some function dependancies that didn't work
when MAX_CPU was set to 1 and the build would fail.
Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1819
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
|
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This change allows us to figure out how much of the AP stacks we are
using, as well as to catch any case of an AP overrunning its stack.
Also, the stack is poisoned, which is a good way to catch programming
errors -- code should never count on auto variables being zerod.
The stack bases are recorded in a new array, stacks. At the end,
when all APs are initialized, the stacks are walked and the
lowest level of the stack that is reached is printed.
Build and boot and look for output like this:
CPU1: stack allocated from 00148000 to 00148ff4:\
lowest stack address was 00148c4c
CPU2: stack allocated from 00147000 to 00147ff4:\
lowest stack address was 00147c4c
CPU3: stack allocated from 00146000 to 00146ff4:\
lowest stack address was 00146c4c
Note that we used only about 1K of stack, even though in this
case we allocated 4K (and in the main branch, we allocate 32K!)
Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/1818
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Right now coreboot's build process produces images that are
not booting on actual hardware because they are smaller than
the actual flash device and also don't have an IFD nor an ME
firmware in them. In order to produce bootable images, you
needed a wrapper script / extra step until now. With this
change, the resulting coreboot.rom is actually bootable.
Change-Id: I82714069fb004d4badc41698747a704bd9fed4da
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1771
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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-CFLAGS = $(INCLUDES) -O2 -pipe -g
+CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe
Change-Id: Icb228d173312a974746e72b6bbae059103b837fc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/1723
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Change-Id: Ie4a98cc8af0dbcf09c7ace79668949ace5938c12
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1752
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The currently encoded register constraints fails compilation
for SMM code or any code that compiles with -fPIC. The reason
is that the ebx register is used for GOT base register.
I don't believe the comment eluding to register constraints for AMD
processors still applies. Therefore remove mmio_conf.h, and use the
mmio methods in io.h.
Change-Id: I391e5c2088ebc760b3a6ed6c37b65bbecab40a5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/1801
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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- Adding more and more optional and non-optional parameters
bloated cbfstool and made the code hard to read with a lot
of parsing in the actual cbfs handling functions. This change
switches over to use getopt style options for everything but
command and cbfs file name.
- This allows us to simplify the coreboot Makefiles a bit
- Also, add guards to include files
- Fix some 80+ character lines
- Add more detailed error reporting
- Free memory we're allocating
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7
Reviewed-on: http://review.coreboot.org/1800
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Change-Id: I9e57c5792409830895a1147799acab95d910a336
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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This removes almost all C++ code (except the wrapper)
Change-Id: I0f84070e3b6dc57c98d49a53150a140479b3221f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1799
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Some of the modules use their own rolled pci_or_configX functions.
Therefore, make them first class so everyone can use them without
copying them.
Change-Id: I9a4d3364c832548dbfe18139c27cce2d60c3316d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/1797
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Double equal sign like "test a == b" works. It really does, except NetBSD.
But I haven't found any clue in the manual for the command test about "==".
Change-Id: I37254cfeb688fd1092f2e549d24f8eb270f02fd8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1817
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
|
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The appropriate compiler (provided by the build system) is used to
ensure proper toolchain options are used.
cbmem.c is being modified to suppress pointer to integer typecast
warnings.
Change-Id: Ibab2faacbd7bdfcf617ce9ea4296ebe7d7b64562
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1791
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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If cmos is invalid for any reason, always set the date and time
before marking RTC valid.
Change-Id: Ib9d154802f75221d58bf28ba9c813f2529904596
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1790
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Remove the duplicate #defines and use what is set in mc146818rtc.h.
Change-Id: Ic471e03c68b591d19c0646fdbea78374af11c8b8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1789
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The MRC cache code, as implemented, in some cases uses configuration
settings for MRC cache region, and in some cases - the values read
from FMAP. These do not necessarily match, the code should use FMAP
across the board.
This change also refactors mrccache.c to limit number of iterations
through the cache area and number of fmap area searches.
Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1788
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Adding an entry for 0x306a0 will make sure that all
CPUs with CPUIDs 0x306aX will execute the driver (analog to
Sandybridge behavior)
Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1783
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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in the resume case, timestamps were collected in RAM stage
but not stored in CBMEM. This leads to only a single time stamp
covering 200ms being available for all of ram stage.
Change-Id: Ibf0bb92caf5e032c12fe4e1b9b84b3624d499511
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1781
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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coreboot uses about 2K of stack on the BSP, and about 1K of stack on the
APs. No reason to use an overdimensonal stack of 32k per core/thread.
Change-Id: I734c240b992d40e1e35db3df5437c36da0a755cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1780
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Change-Id: Ia20c138dae1fc1382abe74303e1117472c513d1d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1779
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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This is a basic romstage driver that can be used for the
MRC cache code on systems where we do not have the MRC cache
stored in a flash region that is memory mapped.
It uses the hardware sequencing interface to avoid having
to know anything about the flash chip itself.
BUG=chrome-os-partner:15031
BRANCH=stout
TEST=manual: this was tested with debug code added to romstage
that attempted to read the MRC cache at offset 0x3e0000.
SPI READ offset=003e0000 size=64 buffer=ff7fba00
SPI ADDR 0x003e0000
SPI HSFC 0x3f00
SPI READ: 0=4443524d
SPI READ: 1=00000bb0
SPI READ: 2=00008e24
SPI READ: 3=00000000
SPI READ: 4=001c8bbb
SPI READ: 5=0c206466
SPI READ: 6=0a043220
SPI READ: 7=000058b4
SPI READ: 8=00000000
SPI READ: 9=00000000
SPI READ: 10=00100000
SPI READ: 11=00100005
SPI READ: 12=20202025
SPI READ: 13=000e0001
SPI READ: 14=00000000
SPI READ: 15=00000000
Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1777
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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If the event log is stored in flash that is not memory
mapped then it must use the SPI controller to read from
the flash device instead of relying on memory accesses.
In addition a new CBMEM ID is added to keep an resident
copy of the ELOG around if needed. The use of CBMEM for
this is guarded by a new CONFIG_ELOG_CBMEM config option.
This CBMEM buffer is created and filled late in the process
when the SMBIOS table is being created because CBMEM is
not functional when ELOG is first initialized.
The downside to using CBMEM is that events added via the
SMI handler at runtime are not reflected in the CBMEM copy
because I don't want to let the SMM handler write to memory
outside the TSEG region.
In reality the only time we add runtime events is at kernel
shutdown so the impact is limited.
Test:
1) Test with CONFIG_ELOG_CBMEM enabled to ensure the event
log is operational and SMBIOS points to address in CBMEM.
The test should involve at least on reboot to ensure that the
kernel is able to write events as well.
> mosys -l smbios info log | grep ^address
address | 0xacedd000
> mosys eventlog list
0 | 2012-10-10 14:02:46 | Log area cleared | 4096
1 | 2012-10-10 14:02:46 | System boot | 478
2 | 2012-10-10 14:02:46 | System Reset
3 | 2012-10-10 14:03:33 | Kernel Event | Clean Shutdown
4 | 2012-10-10 14:03:34 | System boot | 479
5 | 2012-10-10 14:03:34 | System Reset
2) Test with CONFIG_ELOG_CBMEM disabled to ensure the event
log is operational and SMBIOS points to memory mapped flash.
The test should involve at least on reboot to ensure that the
kernel is able to write events as well.
> mosys -l smbios info log | grep ^address
address | 0xffbf0000
> mosys eventlog list
0 | 2012-10-10 14:33:17 | Log area cleared | 4096
1 | 2012-10-10 14:33:18 | System boot | 480
2 | 2012-10-10 14:33:18 | System Reset
3 | 2012-10-10 14:33:35 | Kernel Event | Clean Shutdown
4 | 2012-10-10 14:33:36 | System boot | 481
5 | 2012-10-10 14:33:36 | System Reset
Change-Id: I87755d5291ce209c1e647792227c433dc966615d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1776
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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- Fix handling of 5-byte Fast Read command in the ICH SPI
driver. This fix is ported from the U-boot driver.
- Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by
defining a name for the bool in Kconfig and removing the
forced select in southbridge config
- Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers
to use #if instead of #ifdef
- Relocate flash functions in SMM so they are usable.
This really only needs to happen for read function pointer
since it uses a global function rather than a static one from
the chip, but it is good to ensure the rest are set up
correctly as well.
Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1775
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Applied function attribute to function definition to avoid 'conflicting type' warning.
Function declaration is in src/include/cpu.h
void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0)));
But function definition in lapic_cpu_init.c is missing the "__attribute__" part.
Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e
Signed-off-by: Han Shen <shenhan@google.com>
Reviewed-on: http://review.coreboot.org/1784
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Only thing not decoded now are the PCH straps
ifdtool -d path/to/image.bin
File path/to/image.bin is 4096 bytes
Found Flash Descriptor signature at 0x00000010
FLMAP0: 0x02040003
NR: 2
FRBA: 0x40
NC: 1
FCBA: 0x30
FLMAP1: 0x12100206
ISL: 0x12
FPSBA: 0x100
NM: 2
FMBA: 0x60
FLMAP2: 0x00210120
PSL: 0x2101
FMSBA: 0x200
FLUMAP1: 0x000004df
Intel ME VSCC Table Length (VTL): 4
Intel ME VSCC Table Base Address (VTBA): 0x000df0
ME VSCC table:
JID0: 0x001740ef
SPI Componend Device ID 1: 0x17
SPI Componend Device ID 0: 0x40
SPI Componend Vendor ID: 0xef
VSCC0: 0x20052005
Lower Erase Opcode: 0x20
Lower Write Enable on Write Status: 0x50
Lower Write Status Required: No
Lower Write Granularity: 64 bytes
Lower Block / Sector Erase Size: 4KB
Upper Erase Opcode: 0x20
Upper Write Enable on Write Status: 0x50
Upper Write Status Required: No
Upper Write Granularity: 64 bytes
Upper Block / Sector Erase Size: 4KB
JID1: 0x001720c2
SPI Componend Device ID 1: 0x17
SPI Componend Device ID 0: 0x20
SPI Componend Vendor ID: 0xc2
VSCC1: 0x20052005
Lower Erase Opcode: 0x20
Lower Write Enable on Write Status: 0x50
Lower Write Status Required: No
Lower Write Granularity: 64 bytes
Lower Block / Sector Erase Size: 4KB
Upper Erase Opcode: 0x20
Upper Write Enable on Write Status: 0x50
Upper Write Status Required: No
Upper Write Granularity: 64 bytes
Upper Block / Sector Erase Size: 4KB
OEM Section:
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Found Region Section
FLREG0: 0x00000000
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1: 0x07ff0180
Flash Region 1 (BIOS): 00180000 - 007fffff
FLREG2: 0x017f0001
Flash Region 2 (Intel ME): 00001000 - 0017ffff
FLREG3: 0x00001fff
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
FLREG4: 0x00001fff
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section
FLCOMP 0x64900024
Dual Output Fast Read Support: supported
Read ID/Read Status Clock Frequency: 50MHz
Write/Erase Clock Frequency: 50MHz
Fast Read Clock Frequency: 50MHz
Fast Read Support: supported
Read Clock Frequency: 20MHz
Component 2 Density: 8MB
Component 1 Density: 8MB
FLILL 0x000060c7
Invalid Instruction 3: 0x00
Invalid Instruction 2: 0x00
Invalid Instruction 1: 0x60
Invalid Instruction 0: 0xc7
FLPB 0x00000000
Flash Partition Boundary Address: 0x000000
Found PCH Strap Section
PCHSTRP0: 0x0820d602
PCHSTRP1: 0x0000010f
PCHSTRP2: 0x00560000
PCHSTRP3: 0x00000000
PCHSTRP4: 0x00c8e000
PCHSTRP5: 0x00000000
PCHSTRP6: 0x00000000
PCHSTRP7: 0xc0001ae0
PCHSTRP8: 0x00000000
PCHSTRP9: 0x30000580
PCHSTRP10: 0x00410044
PCHSTRP11: 0x99000097
PCHSTRP12: 0x00000000
PCHSTRP13: 0x00000000
PCHSTRP14: 0x00000000
PCHSTRP15: 0x0000033e
PCHSTRP16: 0x00000000
PCHSTRP17: 0x00000002
Found Master Section
FLMSTR1: 0x0a0b0000 (Host CPU/BIOS)
Platform Data Region Write Access: disabled
GbE Region Write Access: enabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: enabled
Flash Descriptor Write Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: enabled
Intel ME Region Read Access: disabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
Requester ID: 0x0000
FLMSTR2: 0x0c0d0000 (Intel ME)
Platform Data Region Write Access: disabled
GbE Region Write Access: enabled
Intel ME Region Write Access: enabled
Host CPU/BIOS Region Write Access: disabled
Flash Descriptor Write Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: enabled
Intel ME Region Read Access: enabled
Host CPU/BIOS Region Read Access: disabled
Flash Descriptor Read Access: enabled
Requester ID: 0x0000
FLMSTR3: 0x08080118 (GbE)
Platform Data Region Write Access: disabled
GbE Region Write Access: enabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: disabled
Flash Descriptor Write Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: enabled
Intel ME Region Read Access: disabled
Host CPU/BIOS Region Read Access: disabled
Flash Descriptor Read Access: disabled
Requester ID: 0x0118
Found Processor Strap Section
????: 0x00000000
????: 0xffffffff
????: 0xffffffff
????: 0xffffffff
Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1756
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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The Intel PCH can override the ASPM settings via the MPC2 register.
Add a chip override for F0-F7. Mainboards may implement this as
needed.
This also fixes the final PM setup being done too early. It was
being done prior to the PCIe ASPM setup, which happens in the
bridge scan.
Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Right now the SPI bus is getting set to 20mhz for transactions
initiated with the software sequence interface.
In order to be able to do reasonable fastread/write/erase we
can bump this up to a higher value at boot before it gets
locked at 20mhz.
To do this read out the speed set in the SPI descriptor for
hardware sequencing and apply it to software sequencing.
Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The chips we are using do not use BE52 (block erase 0x52)
so we can use that opcode menu location to enable fast read.
Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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At least when CONFIG_CHROMEOS is turned on, it's possible for
CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid
information to put into the framebuffer coreboot table. That means that what's
put in there is junk, probably all zeroes from the uninitialized global
variable the mode information is stored in (mode_info).
When a payload uses libpayload and turns on the coreboot framebuffer console,
that console will attempt to scroll at some point and decrease the cursor's y
coordinate until it is less than the number of rows claimed by the console.
The number of rows is computed by taking the vertical resolution of the
framebuffer and dividing it by the height of the font. Because the mode
information was all zeroes, the coreboot table info is all zeroes, and that
means that the number of rows the console claims is zero. You can't get the
unsigned y coordinate of the cursor to be less than zero, so libpayload gets
stuck in an infinite loop.
The solution this change implements is to add a new function,
vbe_mode_info_valid, which simply returns whether or not mode_info has anything
in it. If not, the framebuffer coreboot table is not created, and libpayload
doesn't get stuck.
Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/1758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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And move the pre-hardwaremain post code to 0x79
so it comes before hardwaremain at 0x80.
Emit these codes from ACPI OS resume vector as well
as the finalize step in bd82x6x southbridge.
Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a
Reviewed-on: http://review.coreboot.org/1816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Coreboot and u-boot create a table of timestamps which allows to see
the boot process performance. The util/cbmem/cbmem.py script allows to
access the table after ChromeOS boots up and display its contents on
the console. The problem is that shipping images do not include Python
interpreter, so there is no way to access the table on a production
machine.
This change introduces a utility which is a Linux app displaying the
timestamp table. Conceivably the output of this utility might be
included in one of the ChromeOS :/system sections, so it was attempted
to write this procedure 'fail safe', namely reporting errors and not
continuing processing if something goes wrong.
Including of coreboot/src .h files will allow to keep the firmware
timestamp implementation and this utility in sync in the future.
Test:
. build the utility (run 'make' while in chroot in util/cbmem)
. copy `cbmem' and 'cbmem.py' to the target
. run both utilities (limiting cbmem.py output to 25 lines or so)
. observe that the generated tables are identical (modulo rounding
up of int division, resulting in 1 ns discrepancies in some
cases)
localhost var # ./cbmem
18 entries total:
1:62,080
2:64,569 (2,489)
3:82,520 (17,951)
4:82,695 (174)
8:84,384 (1,688)
9:131,731 (47,347)
10:131,821 (89)
30:131,849 (27)
40:132,618 (769)
50:134,594 (1,975)
60:134,729 (134)
70:363,440 (228,710)
75:363,453 (13)
80:368,165 (4,711)
90:370,018 (1,852)
99:488,217 (118,199)
1000:491,324 (3,107)
1100:760,475 (269,150)
localhost var # ./cbmem.py | head -25
time base 4249800, total entries 18
1:62,080
2:64,569 (2,489)
3:82,520 (17,951)
4:82,695 (174)
8:84,384 (1,688)
9:131,731 (47,347)
10:131,821 (89)
30:131,849 (27)
40:132,618 (769)
50:134,594 (1,975)
60:134,729 (134)
70:363,440 (228,710)
75:363,453 (13)
80:368,165 (4,711)
90:370,018 (1,852)
99:488,217 (118,199)
1000:491,324 (3,107)
1100:760,475 (269,150)
Change-Id: I013e594d4afe323106d88e7938dd40b17760621c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The sleep type is 5 for S3 and 7 for S5.
Change-Id: I7ffdb3d27b6994ac4a12a343caf4d7abb82fe6ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If these values are non-zero then the kernel will issue
an SMI for each core (cstate) and package (pstate).
Since we don't do anything with these SMI callbacks we
can avoid taking the extra SMIs at boot time by zeroing
these fields.
Change-Id: I3bc5fe0a9f45141d46884cb77ecdfaeaa45d2439
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The VMX MSR may come up with random values and needs to be
initialized to zero. This was done incorrectly in finalize_smm.
It must be done on a per core basis in the general CPU init.
This touches all Sandybridge and Ivybridge configs.
Change-Id: I015352d0f8e2ebe55ac0a5e9c5bbff83bd2ff86b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1794
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The MSR for VMX can start with a random value and needs to be
cleared by coreboot. I am reverting this change, as
it handles almost everything and doing a follow-on change to fix
the improper clearing of the MSR.
Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1793
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The reporting of cores and threads in the system was a bit
ambiguous. This patch makes it clearer.
Change-Id: Ia05838a53f696fbaf78a1762fc6f4bf348d4ff0e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1786
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib1c05828258b9dc7107920ae6cb25bc92ffa86d1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1795
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Example:
cbfstool image-link.bin add-flat-binary u-boot.bin fallback/payload \
0x100000 0x100020
will add u-boot.bin as fallback/payload with a load address of 0x100000
and an entry-point of 0x10002.
Change-Id: I6cd04a65eee9f66162f822e168b0e96dbf75a2a7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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A payload may want to decide whether it uses certain input/output consoles,
or that it wants support for outputing to a particular device but not to use
that device as a console. This change adds a config option which skips the
call to console_init in start_main.
Change-Id: I32b224d4d0bd3a239b402ecb09ee907d53225735
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/1732
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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This makes their names more consistent with other constants in this header,
avoids name collisions, and makes it more obvious where the names came from.
Change-Id: I7b8bd4ada0fbaf049f35759a907281265f5bb2e6
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/1729
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Some constants which were used to interpret the contents of the coreboot
tables were moved to the appropriate libpayload header file. The constant which
describes the maximum length of a GPIO name was renamed to have a CB_ prefix.
That makes it more obvious what sort of GPIO name it describes, and reduces the
change of a name collision. It also makes it more consistent with other names
in that header, although some other exceptions still exist.
Change-Id: I6c0082b3198d34e8a78507fbfac343ee8facf0dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/1728
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Added ehci_reset() function to do a full reset of
the host controller
Change-Id: Ia48db8462ebbb8f260813eb6ba8349d002c4678b
Signed-off-by: Anton Kochkov <a.kochkov@securitycode.ru>
Reviewed-on: http://review.coreboot.org/1814
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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On Sandybridge and Ivybridge systems the firmware image has to
store a lot more than just coreboot, including:
- a firmware descriptor
- Intel Management Engine firmware
- MRC cache information
This option allows to limit the size of the CBFS portion in
the firmware image.
Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1770
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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src/include/timestamp.h is an interface describing timestamp storage
in coreboot. Exporting this interface is complicated by inclusion of
tsc.h which is needed only for the API and is not used in structure
definitions. Including this dependency only when needed fixes the
problem.
Change-Id: Ie6b1460b1dab0f5b5781cb5a9fa89a1a52aa9f17
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1753
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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These bits are used by the IGD OpRegion code
Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1751
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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