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2016-09-06mainboard/google/reef: drop remaining proto board referencesAaron Durbin
The last vestige of the proto boards is the memory sku id gpios. The internal pullups are still required because there's only pulldown stuffing options available on the reef boards. BUG=chrome-os-partner:56791 Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16432 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06mainboard/google/reef: add baseboard nhlt configurationAaron Durbin
Move the current NHLT configuration implementation to the baseboard area such that other variants can leverage it or provide their own configuration. BUG=chrome-os-partner:56677 Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16431 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: add baseboard memory configurationAaron Durbin
Move the current memory configuration implementation to the baseboard area such that other variants can leverage it. The swizzle config is exported as a global to allow duplicate swizzles to use the same structure while still allowing different memory SKUs. BUG=chrome-os-partner:56677 Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16430 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: provide cros_gpio variant APIAaron Durbin
Add support for Chrome OS gpio ACPI table information by providing weak implementation from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16422 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: consolidate gpio related defines to one placeAaron Durbin
Since multiple boards will be living within one directory move all the macros for defining anyting related to GPIOs to the gpio.h header file. That way, when other boards land they can override or use them as is. BUG=chrome-os-partner:56677 Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16421 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: declare mainboard_ec_init() in each C fileAaron Durbin
There's no common EC header file in the code base, and I didn't want to use a header file for single declaration. Therefore, just move the declaration to each file that uses that symbol. BUG=chrome-os-partner:56677 Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16420 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: add variant API for board_id and gpioAaron Durbin
Provide APIs for the board_id() and gpio table functionality. Default and weak implementations are provided from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16419 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06vendorcode/intel/Makefile.inc: Remove extraneous underscoreMartin Roth
Commit e96543e1 (vendorcode/intel: Add UDK 2015 Bindings) had an extra underscore at the end of one of the make lines that we missed in the review. Remove it. Fixes this build warning: .../Makefile.inc:34: Extraneous text after `ifeq' directive Change-Id: I0bc76d827207b4f641ac5ff08f540a114347533b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16411 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-09-05src/include: Improve code formattingElyes HAOUAS
Change-Id: Ic8ffd26e61c0c3f27872699bb6aa9c39204155b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16390 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-05src/superio: Improve code formattingElyes HAOUAS
Change-Id: I8597d205ca84bee0171c3d45549a28b58a050529 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16433 Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-05intel/minnowmax: Clean up whitespaceMarshall Dawson
Align the column of comments. Change-Id: Iec3a173af26710f8ff56519a14784344ea71d489 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16427 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-04intel/minnowmax: Enable all PCIe portsMarshall Dawson
A recently announced Turbot system populates two Ethernet controllers. Enable the remaining disabled PCIe port. Also add a clarifying comment regarding the port associated with Function 0. Coreboot must not be allowed to disable the function which breaks PCI compatibility. Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16429 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04intel/minnowmax: Program GPIO for power LEDMarshall Dawson
MinnowBoard Turbot systems have a GPIO-controlled LED that is generally used to indicate the CPU is running. Commit 2ae9cce8 changed the parameter for GPIO_NC, exposing an issue with the assumed behavior of the signal. Use a pull-down to turn on the LED. Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16428 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04util/lint: Update to latest checkpatch.plStefan Reinauer
Taken from upstream Linux kernel. Change-Id: Id8c9d48b8ca3c7592dc4d78cfd092714bbbb2abf Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04northbridge/intel/i945: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16371 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-04device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__Antonello Dettori
Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__ in order to account for the coreboot stages that do not define device_t and are not __PRE_RAM__ (i.e. smm) device_t Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16369 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/sandybridge. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16409 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04arch/acpi.h: add #if guard to handle the absence of device_t typeAntonello Dettori
Avoid the inclusion of a function declaration if the argument type device_t is not defined. This was not a problem until now because the old declaration of device_t and the new one overlapped. Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16404 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04southbridge/intel/bd82x6x: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/bd82x6x. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16407 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04google/reef: Fix indent in devicetree.cbDuncan Laurie
Indent the I2C device for touchscreen with tabs so it aligns properly. Change-Id: Id9b2d26a4acdd6fe6c69055907258df3cc035b31 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-09-04mainboard/google/reef: provide baseboard and variant conceptsAaron Durbin
To further the ability of multiple variant boards to share code provide a place to land the split up changes. This patch provides the tooling using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing. The directory layout with a single variant, reef (which is also the baseboard), looks like this: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/reef - code variants/reef/include/variant - headers New boards would then add themselves under their board name within the 'variants' directory. No split has been done with providing different logic yet. This is purely a organizational change. BUG=chrome-os-partner:56677 Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16418 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04mainboard/google/reef: prepare sharing directory for variantsAaron Durbin
Instead of completely duplicating the a reference board's directory when doing a variant or follower device start providing a means to share code within a single directory. This change just starts the process from the Kconfig side, but subsequent patches will follow which disentangles the board specific pieces from and common logic. BUG=chrome-os-partner:56677 Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16417 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04mainboard/google/reef: correct EC ASL includesAaron Durbin
The superio.asl wasn't being included within the right scope. Fix that as well as clean up the per-mainboard header includes to be in one place. BUG=chrome-os-partner:56677 Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16413 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-09-04mainboard/google/reef: remove unused gpio.h macrosAaron Durbin
Some of the macros in gpio.h are no longer used because devicetree.cb is being used to autogeneric the ACPI AML. Therefore remove the unused macros. BUG=chrome-os-partner:56677 Change-Id: I433a929229a0318f6c1df652655d046a5152cc63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16412 Tested-by: build bot (Jenkins) Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04Makefile.inc: Use $(MAINBOARDDIR)Iru Cai
Commit 93ef3ff makes the following only print the part number when the ROM is built. In Makefile.inc, $(MAINBOARDDIR) is the variable that has the quotes stripped off from $(CONFIG_MAINBOARD_DIR), so use it instead of $(MAINBOARD_DIR). build_complete:: coreboot printf "\nBuilt %s (%s)\n" $(MAINBOARD_DIR) \ $(CONFIG_MAINBOARD_PART_NUMBER) Change-Id: I729a583182937db7a926eb75aa28dfb53360046c Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/16410 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04src/cpu: Improve code formattingElyes HAOUAS
Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16391 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-04lpss_i2c: Increase default timeout to 4msDuncan Laurie
Increase the default timeout in the LPSS I2C driver to 4ms from 2ms. During testing with some slower devices I found that the existing timeout could be too short leading to transaction failures. Change-Id: Ied86c7a0aa26d55b31f447c5938803c194d0045e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16392 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-02Update .checkpatch.confStefan Reinauer
- Don't require a description of every config statement in the Kconfig changes - Don't complain about externs in .c files - Don't complain about the use of the volatile keyword. The kernel may not want it, but we definitely need it. - Disable checks that seem to be broken. Change-Id: Ic419b81cd36852a91e887e610d4a04984ab5fbd7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16010 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-02.gitignore: Add coreinfo build residue, defconfigMartin Roth
Change-Id: I387603aff6efd6da5e9d78f204d94c064a99e1d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16389 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker
2016-09-02apollolake: relocate fsp header files to vendorcodeBrandon Breitenstein
FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02vendorcode/intel: Add UDK 2015 BindingsRizwan Qureshi
Add UDK 2015 Bindings for FSP header compatibility. These bindings add the necessary code to read FSP Headers without any modifications from FSP Source. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image and verified boot Change-Id: I2887f55b6e63cd0a2b2add9a521be9cfaf875e7d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16307 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02commonlib: update fsp_relocate to make it compatible with UEFI 2.6Brandon Breitenstein
UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32 which cannot be read using read_le32(&returnval). Add in a cast in order to safeguard for any non x86 architecture that may use this relocate. The proper change will be to get the UEFI header files changed to not cast this return value. Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02lenovo/x60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/x60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02southbridge/amd/cs553x: Fix whitespace early_setup.cMartin Roth
Commit ba28e8d7 (src/southbridge: Code formating) incorrectly inserted some whitespace in these files. Change-Id: Ifdcc3580aaba224a396c6efec319e22610c6c81d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16385 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-02lenovo/x200,t400: use gpio.h instead of gpio_setupArthur Heymans
Uses gpio.h instead of default_southbridge_gpio_setup to configure southbridge GPIO's. This is more consistent with how GPIO's are configured on newer targets. Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16379 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02buildgcc: Search the cksum command without checking OS typezbao
The checksum command might appear to be unpredictable only by checking the OS. Just list the candidates, sorted by possibility. Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/11483 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-02Fix newlines at the end of filesMartin Roth
All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-01soc/intel/apollolake: Use consistent convention for community namesFurquan Shaikh
Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO community names, follow one single convention. This allows for re-using macros easily. Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16353 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-01nvramcui: remove undeclared variableAntonello Dettori
Remove an undeclared variable that was accidentally left over, nvramcui is currently unable to compile and operate because of this. Regression introduced in: 904dd303cbe99541025cbea008855f807a5d9f5c (nvramcui: refactor code) Fixes: https://ticket.coreboot.org/issues/70 Change-Id: Ieaba615838d7593546ab5696baf1b8f9828da345 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-01mainboard/google/reef: drop proto gpio supportAaron Durbin
Many changes make proto boards very hard to work with since proto boards were using A stepping processors. Everyone has moved on. Therefore, drop non-proto support. BUG=chrome-os-partner:56791 Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16377 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-09-01mainboard/google/reef: add pen connectionsAaron Durbin
A pen interface was added. Prepare for possibly testing it by plumbing in the gpio configuration. It's very possible these changes need to be tweaked, but no driver code has been seen yet nor a datasheet detailing how some of these signals actually function. BUG=chrome-os-partner:56739 Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16376 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: fix polarity of FP_INTAaron Durbin
The formerly name FP_INT_L net is actually active high and is push-pull. Therefore adjust for the new net name, FP_INT, and polarity. The pulldowns are there because the device is on another board that isn't always available. BUG=chrome-os-partner:56740 Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16375 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: add new memory SKUsAaron Durbin
Two new SKUs are being utilized for reef DVT. Add the following: Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100 Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101 BUG=chrome-os-partner:56738 Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16374 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: support WLAN_PE_RSTAaron Durbin
The reef DVT build added another way to assert the wifi module's reset line. Ensure it's deasserted by default. For previous boards this GPIO doesn't matter because it wasn't routed anyway. BUG=chrome-os-partner:56737 Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31amd/sb700/bootblock.c: Restore accidentally deleted codeMartin Roth
The recent changes to this file from commit 6e5421d2 (sb/amd/sb700: Add option to increase SPI speed to 33MHz) were accidentally removed in a code cleanup patch: commit ba28e8d7 (src/southbridge: Code formating). Change-Id: I6cf3e8f29d5c0384d35637f35e051be40318d20f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16384 Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Tested-by: build bot (Jenkins)
2016-08-31rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpuEric Gao
Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16304 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31src/ec: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I013f71b702644ab337c3d76be1489530bad6e6cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16322 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK.Elyes HAOUAS
Change-Id: I5b69a8429eb2f7add08bc134d5d2366a1afe6a4f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16343 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-08-31src/southbridge: Code formatingElyes HAOUAS
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-08-31src/drivers: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16321 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/via: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic644cf6792a5d360527e48e04c74ae92be0d1d4f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31src/soc: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31src/console: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ibb2ce383322c174bdb3bcc88ae35c17f179f6d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16323 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31skylake: Add initial FSP2.0 supportRizwan Qureshi
Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31rockchip/rk3399: Move romstage.c to mainboard/gruShunqian Zheng
The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31Provide CAR decoration for tpm2 staticsVictor Prupis
Decorated tpm2 statics with CAR_GLOBAL BUG=chrome-os-partner:55083 BRANCH=none TEST=none Change-Id: I85620d5c6ffddab5514c01c2c652670bf33b4e7e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ae43d3bb7fed5b891ed38cd268bfe4e1416b77e2 Original-Change-Id: I871442ec096836a86870f8d53a3058c9c040cff8 Original-Signed-off-by: Victor Prupis <vprupis@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373243 Original-Commit-Ready: Stefan Reinauer <reinauer@google.com> Original-Tested-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16366 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31parade/ps8640: disable mipi mcsJitao Shi
Disable ps8640 mipi mcs function to avoid recognizing the normal mipi dsi signal as msc cmd. BUG=chrome-os-partner:56346 BRANCH=none TEST=build pass elm and show ui Change-Id: I91c690fb1ff3bd9b5c1f227205829c914347cd30 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4fd441b46300fea9f238b27c9c1cda4e9e53c80d Original-Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373219 Original-Commit-Ready: Daniel Kurtz <djkurtz@chromium.org> Original-Tested-by: jitao shi <jitao.shi@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/16365 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31parade/ps8640: add delay to every loop when polling ps8640 readyJitao Shi
Add delay before and in polling ps8640 ready to reduce the frequency of polling. BUG=chrome-os-partner:54897 BRANCH=none TEST=build pass elm and show ui Change-Id: I43c833af910490e53496a343330a6a6af35623a9 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bc8c3d6f7cf0b2da693a465cf3845e8bbc53825a Original-Change-Id: I5c725eed8110ff9f545c1142ca28bcff336b6860 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/371718 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: jitao shi <jitao.shi@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/16364 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31mainboard/*/Kconfig: Set GBB_HWID where missingPatrick Georgi
Provide GBB's hardware ID (used on Chrome OS devices) because it will be dropped from depthcharge. BRANCH=none BUG=none TEST=none Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00 Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/372579 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16363 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31soc/intel/apollolake: Disable Periodic Retraining per-SKUAndrey Petrov
Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=run RMT test, pass Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-31soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3Brandon Breitenstein
Update FSP Header files to provide UPD for periodic training disable. This is for the SIC 1.1.3/150_11 FSP release. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image with new headers for reef Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16352 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-31driver/intel/fsp2.0: Add External stage cache region helperRizwan Qureshi
If ramstage caching outside CBMEM is enabled i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a helper function to determine the caching region in SMM should be implemented. Add the same to FSP2.0 driver. FSP1.1 driver had the same implementation hence copied stage_cache.c. The SoC code should implement the smm_subregion to provide the base and size of the caching region within SMM. The fsp/memmap.h provides the prototype and we will reuse the same from FPS 1.1. Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16312 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-31soc/intel/apollolake: Gather microcode revisionJohn Zhao
Expose get_microcode_info in cpu initialization. Microcode revision is retrieved and stored into log file at verstage. BUG=chrome-os-partner:56544 BRANCH=None TEST=Built coreboot image and validate log file Change-Id: I1e792e70f1318df64b4b85a319700013f3757952 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16311 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-30fsp_broadwell_de: Refactor code for SPI debug messagesWerner Zeh
Currently boards based on fsp_broadwell_de fail to compile if the config switch CONFIG_DEBUG_SPI_FLASH is selected. The error is caused by the usage of const for the address pointer in the functions writeb_, writew_ and writel_. The reason why it stayed hidden for so long is the fact that the switch is used with the preprocessor and nobody really selects it until there is a bug one want to find in this area. This patch fixes the parameter type definition which solves the error. In addition the config switch is not used on preprocessor level anymore but instead on compiler level. This ensures that at least the code syntax is checked on build time even if the config option is not selected. Also prefix the messages with "SPI:" to make them more meaningful in a full log. Change-Id: I3514b0d4c08bf5a4740f2632641e09af1b3aaf3a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16347 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-30soc/intel/skylake: Include Kabylake specific IGD Device IDsBarnali Sarkar
Add Kabylake specific Graphics IDs in report_platform.c and igd.c. BUG=none BRANCH=none TEST=Built and boot kunimitsu Change-Id: I3b810d0ff51eb51d396b783e282779aefb2dcb8c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-30nyan-blaze: Correct indentation for sdram configsPaul Kocialkowski
This corrects indentation for sdram configs in nyan_blaze. Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16342 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-30mainboard/google/reef: set SLP_S3_L assertion width to 28msAaron Durbin
The reef board needs at least ~28ms for its S0 rails to discharge when S3 is entered. Because of the granularity in the chipset the effective SLP_S3_L assertion width is 50ms. BUG=chrome-os-partner:56581 Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16327 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-30soc/intel/apollolake: add option for SLP_S3_L assertion widthAaron Durbin
In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
Change-Id: Iea3f12a5a7eb37586f5424db2d7a84c4319492f8 Reported-by: Coverity (1361947) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16335 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28src/arch: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I8a44a58506d7cf5ebc9fe7ac4f2b46f9544ba61a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16287 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28src/cpu: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I7fb9bfcaeec0b9dfd0695d2b2d398fd01091f6bc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16286 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker
2016-08-28soc/intel/apollolake: Add CQOS CAR implementationAndrey Petrov
Add new option to set up Cache-As-RAM by using CQOS, Cache Quality of Service. CQOS allows setting ways of cache in no-fill mode, while keeping other ways in regular evicting mode. This effectively allows using CAR and cache simultaneously. BUG=chrome-os-partner:51959 TEST=switch from NEM to CQOS and back, boot Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28soc/intel/apollolake: Update stage link addresses for 768 KiB cacheAndrey Petrov
Update link addresses for romstage and verstage. Also update FSP-M relocation address. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15454 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28soc/intel/apollolake: Handle CAR sizes other than 1 MiBAndrey Petrov
Since whole L2 (1MiB) is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to set it up. This is a part of CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15453 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28src/cpu: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: Iebdcc659bf2a3e738702c85ee86dbb71b504721a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16279 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-28src/arch: Capitalize CPU and ACPIElyes HAOUAS
Change-Id: I37dfa853c3dbe93a52f6c37941b17717e22f6430 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16277 Reviewed-by: Omar Pakker Tested-by: build bot (Jenkins)
2016-08-28src/device: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I48477c2917ab1be14d3cedf25e8b97dae1c1d309 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16289 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-28src/include: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I307d37cdf2647467d4c88dfa4be5c66c8587202e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16285 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-28src/device: Remove unnecessary whitespace before newlineElyes HAOUAS
Change-Id: I3536a99a1a6fd2bc7b10777654c1937b92e8eacd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16288 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-28src/southbridge: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16290 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-28src/soc: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I89bc8b26f2dba4770aea14b8bbc7e657355e8c59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16325 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-27rockchip/rk3399: Enable ramstage compression, shuffle around memlayoutJulius Werner
Since we now have so much more room for activities in our romstage SRAM section, we can easily fit the LZMA decompressor to enable ramstage compression. Also shuffle around memlayout sections a little more to make use of unused space, and balance out leftover memory so that all sections that might need future expansion have a reasonable amount. Change-Id: I47f2d03e520fc3103ef04257b4ba7e93874b8956 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27gru: Make SDRAM parameters individual struct files in CBFSJulius Werner
This patch changes Gru SDRAM parameters from structures that just get compiled into the romstage to individual CBFS files. This allows us to only load the parameter set we need for the board we're booting from flash, which reduces our boot time and the SRAM memory footprint required to hold the romstage. TEST=Booted Kevin. Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27cbmem: Always maintain backing store struct in a global on non-x86Julius Werner
The current CBMEM code contains an optimization that maintains the structure with information about the CBMEM backing store in a global variable, so that we don't have to recover it from cbmem_top() again every single time we access CBMEM. However, due to the problems with using globals in x86 romstage, this optimization has only been enabled in ramstage. However, all non-x86 platforms are SRAM-based (at least for now) and can use globals perfectly fine in earlier stages. Therefore, this patch extends the optimization on those platforms to all stages. This also allows us to remove the requirement that cbmem_top() needs to return NULL before its backing store has been initialized from those boards, since the CBMEM code can now keep track of whether it has been initialized by itself. Change-Id: Ia6c1db00ae01dee485d5e96e4315cb399dc63696 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16273 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27cbfs: Add "struct" file type and associated helpersJulius Werner
This patch adds functionality to compile a C data structure into a raw binary file, add it to CBFS and allow coreboot to load it at runtime. This is useful in all cases where we need to be able to have several larger data sets available in an image, but will only require a small subset of them at boot (a classic example would be DRAM parameters) or only require it in certain boot modes. This allows us to load less data from flash and increase boot speed compared to solutions that compile all data sets into a stage. Each structure has to be defined in a separate .c file which contains no functions and only a single global variable. The data type must be serialization safe (composed of only fixed-width types, paying attention to padding). It must be added to CBFS in a Makefile with the 'struct' file processor. Change-Id: Iab65c0b6ebea235089f741eaa8098743e54d6ccc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27commonlib: cbfs: Add CBFS attribute supportJulius Werner
This patch adds support for the CBFS attributes that were already introduced in cbfstool and libpayload. I'm only copy&pasting the header definitions needed for this once more. Really, we should be unifying the definitions (and possibly part of the code) from cbfstool with commonlib, but apparently that hadn't been done when this feature was introduced and I don't really have time to do it cleanly now. Also add a function to extract info from the compression attribute, which can then be used to run cbfs_load_and_decompress() on the file. Change-Id: I7b6463597757122cfe84f006c946a1658bb3acc6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16271 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27lenovo/x200,t400: enable C4 cpu low power stateArthur Heymans
This enables the C4 low power state on the lenovo x200 and t400. It's inspired by the thread on the mailinglist: "[coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS". What this does, is to enable a C3 state using MWAIT(C3) request and set the southbridge config c4onc3_enable to automatically upgrade C3 to the lower power C4 state. The latency (0x37) is the same value used by the vendor bios. With C4 enabled the idle power consumption is about ~2-3W lower. TEST= build and install on target. Use powertop top to measure power usage. To manually disable c-state to compare them, do (tested on linux 4.4): echo 1 > /sys/devices/system/cpu/cpu*/cpuidle/stateX/disable Change-Id: I1a1663a7662ebc7157a965667680688ad6a33545 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15251 Tested-by: build bot (Jenkins) Reviewed-by: Swift Geek Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-26sb/amd/sb700: Add option to increase SPI speed to 33MHzTimothy Pearson
Some SB700-based systems and ROMs support high speed (33MHz) SPI access instead of the power-on default 16.5MHz. Add an option to enable high speed SPI access in the bootblock, and set the default value to Disabled. This greatly decreases boot time on SB700-based systems, especiall when a large payload is in use. On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the command prompt was accessible within 20 seconds of power on, which incidentally is faster than the proprietary BIOS on the same machine could even reach the GRUB bootloader. Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Test: Booted KGPE-D16 with Linux payload Reviewed-on: https://review.coreboot.org/16306 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-25soc/intel/apollolake: Enable ELOGBrandon Breitenstein
Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15937 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-25intel/common: Clear wake status bits before sleepShaunak Saha
Call power management utility function clear_wake_sts from southbridge_smi_sleep before going to sleep. This is needed to clear the wake status bits in ACPI registers GPE0. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from built-in keyboard. Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16299 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-25intel/apollolake: Add power management utility functionShaunak Saha
This patch adds a power management utility function to clear wake status bits in ACPI GPE0 registers. We need to call this function before going to sleep from common smi handler function. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from built-in keyboard. Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16298 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time. By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail). Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16318 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-24soc/intel/skylake: Bump up bootblock size to 48KFurquan Shaikh
When UART_DEBUG is enabled bootblock size grows more than the current 32K. Bump this up to 48K. Change-Id: I580137dfdc9b4ad226c866f2b23b159bd820c62c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16317 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-24soc/intel/skylake: align chromium Chrome OS configAaron Durbin
The chromium tree is currently using a different config for Chrome OS than what is being built in coreboot.org. Align those settings to reflect how skylake Chrome OS boards are actually shipped to provide proper parity between coreboot.org and chromium. Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16313 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-24google/reef: Tune eMMC DLL settings for reef evtChiranjeevi Rapolu
Apply eMMC tuned DLL settings for reef evt. Modify comments to avoid replicating info. Add EDS reference. BUG=chrome-os-partner:55648 BRANCH=none TEST=Verify that reef evt boots to OS from eMMC. Change-Id: If3bf51f3b7d38320f504ea6fbecf7c188a94ae5c Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16296 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-24drivers/spi: remove unconditional RW boot device initializationAaron Durbin
The SPI drivers for the various chipsets are not consistent in their handling of when they are accessible. Coupled with the unknown ordering of boot_device_init() being called this can lead to unexpected behavior (probing failures or hangs). Instead move the act of initializing the SPI flash boot device to when the various infrastructure requires its usage when it calls boot_device_rw(). Those platforms utilizing the RW boot device would need to ensure their SPI drivers are functional and ready when the call happens. This further removes any other systems failing to boot as reported in https://ticket.coreboot.org/issues/67. BUG=chrome-os-partner:56151 Change-Id: Ib3bddf5e26bf5322f3dd20345eeef6bee40f0f66 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16300 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 14:54:34 +0000