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2024-02-22soc/intel/xeon_sp: Refactor IOAT compiler optimization outsShuo Liu
IOAT logics are optimized out for non-IOAT platforms where CONFIG(HAVE_IOAT_DOMAINS) as false. This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead of is_ioat_iio_stack_res() check in the corresponding if statement to fulfill the optimization outs. TEST=intel/archercity CRB Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes
ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22mb/intel/adlrvp: Remove ADLRVP_M mainboardSean Rhodes
These boards are not commerically available so can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-22soc/intel/alderlake: Sync UPD Usb4CmMode with KconfigSean Rhodes
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will time out. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22mb/google/rex/variants/deku: Enable PCIe wifi deviceTony Huang
BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot built FW image correctly. Change-Id: I8db065e25e21406f1966d8020a3b926b3a62ae12 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22mb/google/nissa/var/glassway: Generate SPD ID for supported memory partsDaniel Peng
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) K3KL6L60GM-MGCT 1 (0001) H58G56AK6BX069 2 (0010) H9JCNNNBK3MLYR-N6E 3 (0011) BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2024-02-22tests/lib/ux_locales-test: Simplify macrosYu-Ping Wu
The cmocka problem of sanitizing XML strings has been fixed in CB:80382. Therefore the helper macros UX_LOCALES_GET_TEXT_FOUND_TEST() and UX_LOCALES_GET_TEXT_NOT_FOUND_TEST() can be merged into one. TEST=make unit-tests JUNIT_OUTPUT=y -j Change-Id: Ic3199e2a061550282fb08122943994c835845543 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2024-02-21i2c/drivers/generic: Add support for including a rotation matrixSean Rhodes
The Rotation Matrix allows the specification of a 3x3 matrix representing the orientation of devices, such as accelerometers. Each value in the matrix can be one of -1, 0, or 1, indicating the transformation applied to the device's axes. It is expected by Linux and required for the OS to interpret the data from the device correctly. It is used by various drivers, mainly in `iio/accel`. It was tested on Ubuntu, by rotating the device and verifying the orientation was correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80179 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-21mb/amd/birman_plus: Add Birman+ board support for Phoenix SOCAnand Vaikar
1) Initial commit for upstreaming Birmanplus mainboard changes. 2) Add the DXIO descriptors for Birmanplus mainboard. Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-213rdparty/fsp: Update submodule to upstream masterFelix Singer
Updating from commit id 507ef01: 2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP) to commit id dd98487: 2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path) This brings in 6 new commits: dd98487 Fix EagleStreamFspBinPkg Path fcf623b Fix MAX_VMD_STACKS_PER_SOCKET e07f875 Fix EagleStream BSF File 85f37ab Idaville FSP - New UPDs for SSC 98e497f IoT RPL-P MR1 (4445_03) FSP fc5e3c9 IoT RPL-P MR1 (4445_03) FSP Change-Id: If7d852e1a92d8409a5161797c0aa3a55a71c8b49 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-02-21lib/lzmadecode: Allow for 8 byte reads on 64bitArthur Heymans
This adds an optimization to lzma decode to also read from the boot medium in chunks of 8 bytes if that is the general purpose register length instead of always 4 bytes. It depends on the cache / memory / spi controller whether this is faster, but it's likely to be either the same or faster. TESTED - google/vilboz: cached boot medium 64bit before - 32bit - 64bit after load FSP-M: 35,674 - 35,595 - 34,690 load ramstage: 42,134 - 43,378 - 40,882 load FSP-S: 24,954 - 25,496 - 24,368 - foxconn/g41m: uncached boot medium for testing 64bit before - 32bit - 64bit after load ramstage: 51,164 - 51,872 - 51,894 Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-02-21mb/ocp/*: Remove unused ACPI opregionArthur Heymans
The base for this region is a magic number and none for the fields are used, which likely means this was simply copied from a different firmware. Change-Id: I217bbd0b098cd15ef296854cc6262d651f11d10e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73183 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21mb/google/brya/var/xol: Add support memory partsSeunghwan Kim
Add support memory parts for Xol. - Samsung K3KL6L60GM-MGCT - Samsung K3KL8L80CM-MGCT BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Proto board can boot to ChromeOS. Change-Id: Ic6a36e40f0f93109f296c5cc67a368ace81bd217 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-21mb/google/brya/var/xol: Update memory configurationSeunghwan Kim
Update memory configuration following proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Proto board can boot to ChromeOS. Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21soc/intel/alderlake: Include ADL-N ID 5Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21mb/google/brya/var/xol: Update thermal policySeunghwan Kim
Update initial DTT policy and TCC setting for Xol. The setting values are from internal power team. - Critical CPU temparature: 105 -> 99 - TCC offset: 90 -> 94 BUG=b:323989520 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80410 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-21mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 WWeimin Wu
Set tdp_pl1_override to 15 for performance required by the thermal team. Fix policies.critical index from 2 to 0. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21mb/google/volteer: Disable PM ACPI timer to fix S0i3 regressionMatt DeVillier
Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disabling it. Fixes: 0e90580 (soc/intel: transition full control over PM Timer from FSP to coreboot) This mirrors an identical commit for google/brya: 1ce0f3aab72d ("mb/google/brya: Fix S0i3 regression") TEST=Boot Linux on google/drobit, verify S0i3 counter incrementing after exiting S0ix suspend states. Change-Id: I644e42388c0f6127512bf52e774b79721601ecc9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21mb/google/brya: Create glassway variantDaniel Peng
Create the glassway variant of the nivviks reference board by copying the template files to a new directory named for the variant. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=None Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-213rdparty/cmocka: Update cmocka to latest stable-1.1Jakub Czapiga
New patches: 8be3737 cmocka: Fix assert_memory_equal() display fb38de9 cmake: disable `-Wdeclaration-after-statement` a74d9cd Sanitize XML strings. 4e92198 Improve c_strreplace implementation ea6ab8b cmake: Set CMOCKA_LIBRARIES in package config for backwards compatibility 53de473 cmocka: Add overflow check for test_calloc() e738d6e tests: Add test for test_calloc() a01cc69 Bump version to 1.1.7 123f00e cpack: Update ignore files for source package generation f1e1615 Bump version 1.1.6 35dd06e tests: The exception handler doesn't work on Windows 9d72cf9 tests: Raise segmantation fault 2b20a4d tests: Rename exceptions tests array 4cd1fda tests: Better match for test_exception_handler 8ad2c4e cmake: Fix path relocation in pkgconfig file for mingw 3137fa5 cmake: Do not use CMAKE_(BINARY|SOURCE)_DIR for compile_commands.json 6e9d32f Improve INSTALL.md c4da7e1 doc: Link to the examples for mocking b13f29b include: Update copyright year info 98c451d include: Define strtok_r with Visual Studio 4aae816 gitlab-ci: Move memory and ub sanitizer to analysis stage 559381b gitlab-ci: Move freebsd to test stage ce43813 examples: Add missing compile and link options 5ead982 gitlab-ci: Introduce stages 5f366b6 gitlab-ci: Fix typo in fedora/mingw32 build 77476f7 gitlab-ci: Use gitlab windows runners 200393b gitlab-ci: Reformat yaml 406591a tests: Initialize 'struct stat' in test_assert_macros.c b201da5 cmake: Fix path where to find cmocka.dll a47b3da include: Improved call ordering documentation 61b1fb9 doc: Remove redundant words 2cc8cba Fix issue with fail_msg TEST=make unit-tests TEST=make unit-tests JUNIT_OUTPUT=y TEST=(cd payloads/libpayload; make unit-tests) TEST=(cd payloads/libpayload; make unit-tests JUNIT_OUTPUT=y) Change-Id: I60b37021e2587cc32c755719ef40a650a1c14b59 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20lib/hardwaremain: align '\' in multi-line macroFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5967cebad3ad52b5cbc7babc0c808039d7da5227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80635 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20mb/google/brox: enable DPTF functionality for broxSumeet Pawnikar
Enable DPTF functionality for brox board BRANCH=None BUG=b:324360936 TEST=Built and tested on brox board Change-Id: I0315f7f45688ccc36d321d6be4fa4fac7559a16b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-20soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI headerShuo Liu
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC are ACPI table specific, and could be used across Xeon-SP SoCs. This patch moves their definition from FSP header to Xeon-SP layer ACPI header. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-02-20soc/intel/xeon_sp: Add support for is_ioat_iio_stack_resShuo Liu
IOAT is the term for the on-chip accelerator technology of Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack. Different SoC has different check criteria for IOAT stacks, this patch introduces an util function to abstract these differences as well as cleaning up the usage of names. TEST=intel/archercity CRB Change-Id: I376928ad89b68b294734000678dad6f070d3c97d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80578 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20treewide: Remove unused CHIPsArthur Heymans
No devicetree uses these anymore. Change-Id: Ia65a0a56a6668a13761bad35f6a44ed8f6a35a78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72600 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20util/crossgcc: Update LLVM from 16.0.6 to 17.0.6Felix Singer
Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20crossgcc: Upgrade binutils from 2.41 to 2.42Elyes Haouas
Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20Documentation: Release notes for the 24.02 releaseMartin Roth
These will be updated and finalized after the release to capture any final changes, remove "upcoming release", and finalize all stats. Change-Id: Idc224c43f2459faabf91a9ef282bb9eaeba42240 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80617 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier
Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMERMatt DeVillier
It's not needed other than for booting w/SeaBIOS, where it is already selected by default, and enabling it with edk2 payload prevents Linux/ Windows from fully entering S0ix. TEST=build/boot purism/librem_cnl (Mini v2), verify Win11/Linux able to enter and exit S0ix properly. Change-Id: I974a82bedc4e06f48ce801f2bc0c29afbd80ffcf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80602 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19mb/starlabs/starbook: Always include the tcss.aslSean Rhodes
The tcss.asl doesn't just relate to tcss, it is required for core scheduling, so include it for all platforms. Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes
This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19util/liveiso/nixos: Install lm_sensors packageFelix Singer
Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2024-02-19soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/jasperlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19mb/google/dedede/var/beadrix: Disable un-used C1 port by daughterboardKevin Yang
Probe usb ports by FW_CONFIG setting to disable C1 port on beadrix poin2 new daughterboard without C1 port. BUG=b:316365055 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-02-19mb/google/dedede/var/beadrix: Generate SPD ID for supported memory partKevin Yang
Add beadrix supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. CXMT CXDB4CBAM-ML-A BUG=b:321830738 TEST=Use part_id_gen to generate related settings Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-02-18cbfstool: Support 64bit addresses for flat imagesPatrick Georgi
SELF has the fields wired up for 64bit, but adding flat images cuts the upper half. Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18arch/riscv/Makefile.mk: Fix OpenSBI compilationMaximilian Brune
1. romstage.S should only be included if we have a separate romstage 2. FW_JUMP and FW_DYNAMIC are opposing options and we only support FW_DYNAMIC Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79952 Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18util/crossgcc/buildgcc: Compile RISC-V GCC with medanyMaximilian Brune
currently the HiFive Unmatched mainboard produces the following error: ``` util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a (_clzsi2.o): in function `__clzdi2': util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in .rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/ rv64imafdc/lp64d/libgcc.a(_clz.o) ``` This is due to the fact that the libgcc.a library is compiled with the medlow code model but the mainboards are compiled with the medany code model. Changing the code model of the GCC libraries to the medany code model fixes the issue. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc/intel/xeon_sp/spr: Don't leak memoryPatrick Rudolph
Only call fill_pds() once to prevent leaking memory. Previously it was called for every active stack on every socket. Only call dump_pds() once to prevent spamming the console with the same information. Drop the return value since it's always returning success. Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18soc/intel/xeon_sp/uncore: Don't print uninitialized memoryPatrick Rudolph
The struct map_entry has two zero'd entries due to the ifdef being used. Do not read those entries and do not print those entries. Fixes a NULL string being printed along as the vendor and device ID of the PCI device. Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18util/cbfstool/linux_trampoline: Support more e820 entriesPatrick Rudolph
Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866 "[PATCH] Increase number of e820 entries hard limit from 32 to 128" made in 2005 the number of e820 entries passed from the bootloader is 128. Use the boot protocol version to check for support of 128 entries and use them if necessary. Tested on IBM/SBP1: Fixes booting a Linux payload when more than 32 entries are present in the memory table, which can easily happen on a 4 socket platform. Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18mb/purism_librem_cnl/var/*: Drop redundant entries in overridetreesMatt DeVillier
Now that the baseboard uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default or the baseboard default, since they are pointless clutter. TEST=build/boot purism/librem_cnl (Mini v2), verify output of lspci and lsusb unchanged before and after patch. Change-Id: I12498e7261dafd7ee59fe79926532399392d1b09 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80600 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/purism/librem_cnl: Drop devicetree entries identical to chipset.cbMatt DeVillier
Now that the board uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default, since they are pointless clutter. TEST=build/boot purism/librem_cnl (Mini v2), run lspci and verify output unchanged before and after patch. Change-Id: I6c656d227962548cebde61f1d82333837adbbf56 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80599 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc/intel/mtl: Skip RW CBFS ucode update if RO is lockedSubrata Banik
This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2024-02-18soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier
Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/intel/tglrvp: Drop selection of SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier
It's already selected at the SoC level, so selecting at the board level is redundant. Change-Id: Ifbe7f88858b9e5e8e5185dbff5853186fd3c66cb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80557 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc/intel/common/block/dtt: Add ACPI stub for TCPU deviceMatt DeVillier
Add an ACPI stub containing the TCPU device in proper scope, along with the device status, on boards not using the DPTF driver, so that there exists an ACPI device to be referenced from the PEPD LPI constraint list. Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for _SB.PCI0.TCPU on boards with the SA thermal device enabled but which do not use the Intel DPTF driver. TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2). Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier
This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc/intel/common/block/sata: Fix scope for SATA ACPI deviceMatt DeVillier
acpi_device_path() includes the device name, so we end up with: Scope (\_SB.PCI0.SATA) { Device (SATA) { ... Fix this by using acpi_device_scope() instead. TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify SATA device scope correct. Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/*: Add SPDX headers for cmos.default filesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/samsung to mb/up: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/opencellular to mb/roda: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/inventec to mb/ocp: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/cavium to mb/foxcomm: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ib100a677935cf3309a380952c35e9060e64433cb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: I71dc3dd270b9a61c86b59031f898af37f0fea345 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80590 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18ec, lib, security, sb: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18drivers: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ib27894f0f1e03501583fffb2c759b493d6a7b945 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80588 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18arch to cpu: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: I7dd7b0b7c5fdb63fe32915b88e69313e3440b64a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80587 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18payloads: Add SPDX headers to KconfigMartin Roth
Change-Id: Iea569fd457b3cd1f4746fbc6a96319eb42733a6b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80586 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18LICENSES: Add LGPL 2.1 licenseMartin Roth
This is used in util/cbfstool/elf.h and lzmadecode. Change-Id: I75e71259f23bee602ffb54b0c51e0e4a9da3f8e5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18Treewide: Fix incorrect SPDX license stringsMartin Roth
These strings didn't match the license names exactly, so update them to match. Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/prodrive/hermes: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I81dd67fd200768942fe355180b75db0746cda8ea Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-02-17mb/google/rex: Do not power on FPMCU in ramstagePatryk Duda
When 'reset_gpio' and 'enable_gpio' properties are defined in overridetree.cb, the kernel will power on the FPMCU. If the device was previously enabled the kernel will reset it. To avoid situation in which the FPMCU is powered on and reset later we leave the FPMCU powered off in coreboot and started by the kernel. This is exactly what other boards do (e.g. brya). TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once (e.g. examine FPMCU console logs) Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1 Signed-off-by: Patryk Duda <patrykd@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-17intelblocks/systemagent: Add missing N6005 Jasper Lake SKU to PCI ID listMichał Żygowski
Change-Id: I3fb4c6cfe24290c34682ff1c3396540465048727 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-17soc/intel/jasperlake/bootblock: Report missing Jasper Lake SKUMichał Żygowski
Change-Id: Ie0d25eca75225ab33e6c15ef5ccb9073151f4148 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-17mb/google/brox: Handle bluetooth enable on devicesAshish Kumar Mishra
For devices that require CNVi Bluetooth select WIFI_BT_CNVI in FW_CONFIG. Discrete Bluetooth devices need to select WIFI_BT_PCIE. BUG=b:319188820,b:325084796 BRANCH=None TEST=Boot image on SKU1,SKU2 and check BT devices enumerate. Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80564 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-16mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPICShelley Chen
Setting the EC interrupt GPIO as an APIC is able to solve many problems that we are currently seeing: 1. Routing through the APIC make the IRQ# associated with this pin unavailable to claim for other devices in the kernel. This is causing EC interrupts to not work. 2. Since EC interrupt are not working, we are not able to flash the EC from the DUT. 3. Also, the GPI_INT configuration does not allow us to set the polarity of the GPIO, which means that it is by default set as active high. As a result, we are seeing an excessive number of host command interrupts to the EC. This disappears when we change the configuration to APIC and set the polarity as INVERT. BUG=b:319129926,b:324707182 BRANCH=None TEST=1. After boot up, check if ec_cros_lpcs driver was successfully registered. Look for the following string: "cros_ec_lpcs GOOG0004:00: Chrome EC device registered" 2. Make sure can flash the EC image from the DUT 3. Make sure EC console is not getting continuous stream of host commands. Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.corp-partner.google.com>
2024-02-16soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MBSubrata Banik
This patch increases the IgdDvmt50PreAlloc value as per Intel recommendation starting with GFX PEIM 103x. TEST=Able to build and boot google/rex. Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-15soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devicesSean Rhodes
Rename tcss_mux_init to disconnect_tcss_devices to make it clear what this function is doing, as it doesn't initialise anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79874 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-15mb/starlabs/starbook/rpl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-15mb/starlabs/starbook/adl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-15ec/starlabs/merlin: Remove ubtc.aslSean Rhodes
Remove the ubtc.asl as it's no longer needed. Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-15ec/starlabs/merlin: Remove the CMOS Bank 1 entriesSean Rhodes
These entries no longer exist as they are stored in CFR. Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-15mainboard/qemu-aarch64: Map entire RAM space as read-write memoryAlper Nebi Yasak
Commit 977b8e83cb0a ("mb/emulation/qemu-aarch64: Add MMU support") adds MMU support for ARM64 QEMU VMs, but registers a limited 1GiB region for the DRAM, with a note that ramstage should update it. However on recent versions of QEMU "virt" VMs, accessing RAM outside this registered region results in an exception even if the address is backed by actual RAM. This interferes with RAM detection which catches these exceptions, effectively limiting us to detecting a maximum 1GiB of RAM even if more is available. Register the entire RAM space to MMU instead of just the 1GiB, so that probing RAM addresses can correctly detect how much RAM we have. Change-Id: I3afbd27b91ab37304a29a62506f965ac3cfb1c06 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-02-15util/ifdtool.c: Fix long_options for platformVojtech Vesely
Platform has argument, but has_arg was mistakenly set to 0. Change-Id: I7d5c31c2b1da544cb73d9e213d463332fcdba7df Signed-off-by: Vojtech Vesely <vojtech.vesely@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80432 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2024-02-15mb/lenovo/x230: Disable the USB P8 portAlexei Sorokin
This port is not connected on the X230, X230i, X230t. When X230 support was introduced and pei_data was filled in, this port was disabled, but after commit 3dc12c1e1918 (bd82x6x: Consolidate early native USB init) it has become enabled. Change-Id: I952193798c0894b256b21d9fb3f238074ff5f0f0 Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80468 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14include/device/device: drop unused soft_reserved_ram_resource macroFelix Held
The unused soft_reserved_ram_resource expanded to the non-existent fixed_mem_resource function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-14mb/google/dedede/Kconfig.name: Alphabetize board listingMatt DeVillier
Change-Id: I7230bb8f9883f186c10f41132a2919c3fd99f8c1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-14mb/google/dedede/Kconfig: Alphabetize selections for baseboardsMatt DeVillier
Change-Id: I245eb8a9961e3e0025c0275f306a4d989b532331 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80491 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14mb/google/dedede/Kconfig: Alphabetize variant board listingsMatt DeVillier
Change-Id: I2909375d38c37332293bd7928ae33d5bb502694f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80490 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14util/showdevicetree: drop unmaintained toolFelix Held
This tool doesn't have a makefile, when trying to compile it manually with the given instructions it even fails to compile after fixing the paths in the given command, and it references the non-existing PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14drv/gfx/generic: Add Intel ACPI Backlight funcs for LCD devicesMatt DeVillier
Normally this would be done by the Intel GMA driver, but we can't have two copies of the _DOD method, so generate the LCD backlight controls here to allow use of this driver instead of the default GMA panel definition. TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness controls functional. Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80061 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14mb/google/dedede: Add VBTs and select INTEL_GMA_HAVE_VBTMatt DeVillier
Vbt data files extracted from dedede recovery image 120.0.6099.272. Change-Id: I28485d501e519cdaa06c55c20eba07190c5c6b6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-14mb/starlabs/starbook/kbl: Remove tcc_offset entrySean Rhodes
The TCC offset is configured in devtree.c, so remove it from the devicetree. Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-14ec/starlabs/merlin: Remove the call to pc_keyboard_initSean Rhodes
As DRIVERS_PS2_KEYBOARD isn't set, this function is not doing anything. Change-Id: Ie8842a32fca56f330a0f044cf96112dc5cae6546 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-14Documentation/vboot: Update vboot supported boards listMatt DeVillier
Auto-generated by util/vboot_list/vboot_list.sh. Change-Id: I35dc51915c8468543c981e1b046e4ecf8d5b4bbf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-02-14tree; Remove unused <lib.h>Elyes Haouas
Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80433 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14mb/lenovo/x230: introduce EDP variantAlexander Couzens
There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a custom eDP panel instead of the stock LVDS display. There are several adapter boards present on the market and all of them use the same method of enabling the custom eDP panel. To make this work with coreboot, the internal LVDS connector should be disabled in libgfxinit. Additionally, VBT has been modified to keep brightness controls functional on the adapter boards that use LVDS for the job. The modifications done to the VBT are: - Remove the LVDS port entry. - Move the DP-3 (which is the 2nd DP on the dock) entry to the first position on the list. - Set the DP-3 as internally connected. This has been reported to work with the following panels: - LP125WF2-SPB4 (1920*1080, 12.5") - LQ125T1JW02 (2560*1440, 12.5") - LQ133M1JW21 (1920*1080, 13.3") - LTN133HL10-201 (1920*1080, 13.3") - B133HAN04.6 (1920*1080, 13.3") - B133QAN02.0 (2560*1600, 13.3") Other eDP panels not on this list should work as well. Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mainboard: Enforce usage of AZALIA_ARRAY_SIZESNicholas Sudsgaard
This is the de facto method and should be enforced to keep things consistent. Change-Id: I7eee77f7fd49bc38e27cb0e6be0a4a6555098cc7 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-13mb/clevo/tgl-u: Use enum for AZALIA_PIN_CFG misc fieldNicholas Chin
Use the new JACK_PRESENCE_DETECT and NO_JACK_PRESENCE_DETECT enums instead of raw values in the misc field of AZALIA_PIN_CFG. TEST: Timeless build for clevo/tgl-u did not change Change-Id: Ic3f4128ecbf89ddce3b6e705ebef76da343a433c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13include/device/azalia_device.h: Add enum for misc fieldNicholas Chin
The HDA specification defines bits 11:8 of the Configuration Default register as a miscellaneous field for other jack information. Only bit 8 has a standard meaning, and indicates that the jack does not have presence detect capability. Add an enum for use in the AZALIA_PIN_DESC macro to indicate this field. Note that many vendor firmwares set bits 11:9 to non zero values despite them being reserved in the specification, and their meaning in these cases is not well known. Change-Id: I70cbfca8541828a1e0c7280887060c04e4c71721 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/*: Replace use of gfx/generic addr field with display typeMatt DeVillier
Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. TEST=build/boot google/drallion, dump SSDT and verify DID entry is unchanged. Change-Id: Ic929cf7ec6849ba398653226bbe46d27b4e3fa81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13drivers/gfx/generic: Add display type fieldMatt DeVillier
Add an enum for the Display Type, which if set, can be used to generate the Device ID value dynamically when the addr field is not set. This will allow devicetree entries to specify the display type instead of a hex value for the address which requires referencing the ACPI spec to decode. For an internal panel connected to the first port on the graphics chip, currently an addr value of 0x80010400 is specified. Replacing the 'addr' field with the 'type' field and setting it to 'panel' will generate the same DID value. Change-Id: Id0294a14606b410a13fa22eeb240df9e409a7ca3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/brox: Set display output type for eDP panelMatt DeVillier
Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: If63374329ed5eb4330517ca1bf2ba1ada24fa54a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80244 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 19:48:43 +0000