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2023-12-14MAINTAINERS: Update Jakub's email addressJakub Czapiga
jacz@semihalf.com is no longer available, czapiga@google.com should be used instead. Change-Id: I228b34c961ccf1546103f105276a75409825a432 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79438 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14mb/google/nissa/var/anraggar: Update DTT settings for thermal controlWeimin Wu
Update DTT settings based on the suggestion of the thermal. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I2296990062cadc05202e3d1ab90af04234bda885 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)Weimin Wu
1. Ref to SCH, LTE use USB3 Port3, enable it. 2. Explicitly define the use of USB3 Port1 & USB3 Port2. BUG=b:315061146 TEST=can pass PCIe Hardware Compliance Test Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Change code style for register usb2_portsWeimin Wu
Change code style to be compatible with Nissa's format: register "option" = "{ [0] = value /* comment */ ... }" to register "option[0]" = "value" /* comment */ BUG=none TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I60659bd44813173f9b984216473a0919c5f331b8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14soc/amd/genoa/domain: generate SSDT entries for domainsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iadc37f2724a9be43cad1f1934403ebabd5cca245 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-14soc/amd/genoa: Add basic ACPI supportFelix Held
- DSDT - MADT - SSDT CPUs Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0c86694ae83e9e6aa06a50a8a35bf2b24bc8ab65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76530 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_portsFelix Held
Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O ports in FADT that openSIL configured. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14Update vboot submodule to upstream mainYi Chou
Updating from commit id db533497: 2023-12-05 20:09:44 +0000 - (host/lib/pkcs11: Remove superfluous 'nss' directory from include paths) to commit id c0cb4bfa: 2023-12-08 09:14:32 +0000 - (signer: sign_android_image.sh should die when image repacking fails) This brings in 3 new commits: c0cb4bfa signer: sign_android_image.sh should die when image repacking fails 30e37712 tlcl: Add `TlclCreatePrimary()` support 12fa13e3 2api: Add firmware & kernel PCR support Change-Id: I354c1d07c3b506069d5b64bc2fc476dadc36e0e2 Signed-off-by: Yi Chou <yich@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79484 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard pathKulkarni, Srinivas
Move the existing FSP 4301.01 headers for Raptor Lake out of subdirectory called 43101.01 to follow standard process. Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-13soc/amd/genoa/acpi: update soc.aslFelix Held
Add the missing parts in soc.asl. Compared to earlier versions of this, the includes related to S0i3 and DPTC were removed. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I89ecf469e44ca2a3b35c9fcf57c008ff29e7b9bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/79468 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13soc/amd/genoa/acpi/soc: add root bridges to DSDTFelix Held
Add the 4 root bridge devices using the ROOT_BRIDGE macro. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If405a90981e5c1fea51935c520800a245473317e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79467 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13mb/amd/onyx/dsdt: include acpi/dsdt_top.aslFelix Held
acpi/dsdt_top.asl provides some common functionality and needs to be included at the beginning of the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7b5ddce110b35ed65c6df6cc42995abe93a3ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79466 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13soc/amd/genoa/acpi: include globalnvs.asl in SoC codeFelix Held
Instead of including globalnvs.asl in the mainboard's dsdt.asl, include it in Genoa's soc.asl. This aligns Genoa with Cezanne and newer and also moves more SoC-common code to the SoC folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e3299a95e007188a4d9de824cfff8d25a778be Reviewed-on: https://review.coreboot.org/c/coreboot/+/79465 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13soc/amd/genoa: set up the non-FCH IOAPICsFelix Held
Apart from the IOAPIC in the FCH which is handled by amd_lpc_ops, there's one IOAPIC per PCI root which also needs to be initialized. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I38af5a194062e714827852e95f4e29b45311e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13soc/amd/genoa/domain: fix indentation in genoa_pci_domain_opsFelix Held
There's no need for the two additional spaces between the tabs and the '='. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6824e8c7ee870fc44c5efd70cc05677e9948a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79464 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13soc/amd/genoa/chip: add init & final functions and chip nameFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I00a567f417b1e22167923fc3193583138718dbbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/79463 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13soc/amd/genoa/include/amd_pci_int_defs: rename PIRQ index 0x60 and 0x61Felix Held
PIRQ_SCI is already defined as 0x10 and this also brings the definitions more in line with Phoenix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2ab954b379d2edd0167d7fb229557600cbc4e48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13lib/jpeg: Replace decoder with Wuffs' implementationPatrick Georgi
To quote its repo[0]: Wuffs is a memory-safe programming language (and a standard library written in that language) for Wrangling Untrusted File Formats Safely. Wrangling includes parsing, decoding and encoding. It compiles its library, written in its own language, to a C/C++ source file that can then be used independently without needing support for the language. That library is now imported to src/vendorcode/wuffs/. This change modifies our linters to ignore that directory because it's supposed to contain the wuffs compiler's result verbatim. Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that implements our JPEG API. I further changed it a bit regarding data placement, dropped stuff from our API that wasn't ever used, or isn't used anymore, and generally made it fit coreboot a bit better. Features are Nigel's, bugs are mine. This commit also adapts our jpeg fuzz test to work with the modified API. After limiting it to deal only with approximately screen sized inputs, it fuzzed for 25 hours CPU time without a single hang or crash. This is a notable improvement over running the test with our old decoder which crashes within a minute. Finally, I tried the new parser with a pretty-much-random JPEG file I got from the internet, and it just showed it (once the resolution matched), which is also a notable improvement over the old decoder which is very particular about the subset of JPEG it supports. In terms of code size, a QEmu build's ramstage increases from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA). [0] https://github.com/google/wuffs Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Based-on-work-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13drivers/uart/pl011.c Perform basic UART initNaresh Solanki
Configure UART baud rate, Line Control register as 8n1 with FIFO enable and enable UART TX and RX. Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-13drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13mb/google/brox: Generate RAM ID for supported memory partIvy Jian
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:311450057,b:315913909 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-12soc/amd/genoa/chipset.cb: add missing non-transparent PCI bridgesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d5efa948e8bd993ca4b5af80f664db687b8a766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12mb/amd/onyx/devicetree: enable more PCI devicesFelix Held
Early versions of CB:76519 had more devices enabled in the chipset devicetree which shouldn't necessarily be enabled in the chipset devicetree. Enable most of those in the Onyx mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-12soc/amd/genoa/chipset.cb: disable IOMMU devices by defaultFelix Held
Disable the IOMMU PCI devices in the chipset devicetree. In order for the IOMMU devices on the Onyx mainboard still be enabled, enable them in the mainboard devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa: Parse APOB for DRAM layoutFelix Held
Use the xPRF call to report holes in memory and report those regions as reserved. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5605499e39931e1a1592318310112666f8a0f144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12vendorcode/amd/genoa: Parse APOB for DRAM layoutArthur Heymans
Use the xPRF call to report holes in memory to report those regions as reserved. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/amd/onyx: Add MPIO configMartin Roth
Add the device and chip entries for the various PCIe ports and MPIO lane configuration. Below each PCIe bridge device with an external PCIe port on the mainboard, an MPIO chip is added that provides the corresponding MPIO configuration for this external PCIe port. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8563c5a07eb8fd8ff9dd4e7b63fc9a7d485b1316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78921 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa: Add opensil MPIO chip filesArthur Heymans
Add the openSIL MPIO chip driver that allows specifying the MPIO lane configuration in the mainboard's devicetree instead of having this configuration in a separate port descriptor C file. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12vendorcode/amd/opensil: Add SATA configurationArthur Heymans
For now, we'll use a hard-coded SATA controller configuration that should work in most cases instead of making everything configurable via devicetree settings. In the process of scrubbing opensil for public release SATA became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib37a081c0be4fdd2785e1dca70f376b967ce4462 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76518 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/amd/onyx: Add USB configurationMartin Roth
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I62eefe1061446612168dd27e673a2742903456c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78920 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12vendorcode/amd/opensil: Add USB configurationMartin Roth
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic41f57f3208aebb3a8b42f70cf558de50fa4de24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78919 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa/chip.h: drop unneeded xhci2_enableFelix Held
Genoa has no XHCI2 controller, so drop this devicetree option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b995bb1c0cf0032be25ab215333bc966427f7ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/79454 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12arch/arm64/armv8/Makefile.inc: Add clang -target for .ld CPPArthur Heymans
When preprocessing the linker script the target arch needs to be specified. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id18af3da93d2d06a2ebb83eddd03377c9026c8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/78443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-12mb/google/rex/var/screebo: Increase PL1 max value from 15W to 25WKun Liu
Adjust PL1 max value from 15W to 25W BUG=b:314263021 TEST=emerge-rex coreboot Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12util/abuild: Better identify config string in logMartin Roth
When using the --skip_set and --skip_unset arguments, the config line looked like a statement that the build was being skipped instead of abuild just printing the configuration. This updates those config statements to better show that it's the config and not stating that this particular build is being skipped. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6cc59f9b33dcda51aeb3640d449037a0aa054e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76936 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11ec/google/chromeec: Provide ec_sync wake optionMark Hasemeyer
The ACPI spec defines keywords for the GpioInt and Interrupt resources to specify whether a given pin is wake capable. Some boards are using the ec sync interrupt pin to wake the system so the CREC _CRS needs to be updated accordingly. Provide a new macro that allows a board to specify whether its ec sync pin is wake capable. BUG=b:243700486 TEST=Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2023-12-11soc/amd/genoa/chipset.cb: add missing '_' in gpp_bridge_3_bFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22b9b6781f516b96724b67d1321dd71b98e0e0e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11soc/amd/genoa: Add USB configurationArthur Heymans
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. Add USB OC pins to chipset.cb In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11soc/amd/genoa/chipset.cb: enable dummy functionsFelix Held
Enable the dummy function 0 that don't have an alias in the chipset devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I607245c587a544007fd714f64901cbb50014612f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11libpayload/arm64: Round fb_size up to a multiple of GRANULE_SIZEYidi Lin
If a framebuffer is already configured by coreboot, we need to ensure that the framebuffer size is a multiple of GRANULE_SIZE before passing to `mmu_add_memrange`. Otherwise, we would fail to allocate memory region due to `sanity_check`. Change-Id: Ia6a6400733ca10a61220087e87022f68c28e4789 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79451 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11mb/google/nissa/var/quandiso: Tune P-sensorRobert Chen
Update proximity sensor tuning value from dedede/kracko tuning. Remove GPIO override to use the configuration from nissa baseboard: - GPP_B5 ==> SOC_I2C_SUB_SDA - GPP_B6 ==> SOC_I2C_SUB_SCL BUG=b:310050220 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11soc/amd/common/data_fabric: pass PCI segment group to domain codeFelix Held
Return the PCI segment group number from data_fabric_get_pci_bus_numbers via pointer argument so that amd_pci_domain_scan_bus can handle the PCI segment group numbers once coreboot supports more than one PCI segment group. For now, just print an error and return if the buses are on a PCI segment group other than 0. TEST=Mandolin still boots Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia53cda0ba656201c2197d05bc0d4a8fbbe8ad5d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-11soc/intel/meteorlake: Add entries to eventLog on invocation of early SOLSubrata Banik
This patch records early signs of user activity during CSE firmware synchronization or MRC (re)training events in the event log (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:279173035 TEST=Verified on google/rex, event shows in eventlog after CSE sync and/or MRC. Scenario #1: While performing MRC update 1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2023-11-08 | Memory Cache Update | Normal | Success 3 | 2023-11-08 | System boot | 9 4 | 2023-11-08 | ACPI Wake | S5 Scenario #2: While performing CSE update/downgrade 11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 12 | 2023-11-08 | System boot | 13 Scenario #2: While performing both MRC and CSE upgrade 16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 18 | 2023-11-08 | Memory Cache Update | Normal | Success 19 | 2023-11-08 | System boot | 16 20 | 2023-11-08 | ACPI Wake | S5 Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-11soc/intel/mtl: Display Sign-of-Life message using FSP-MJeremy Compostella
Meteor Lake Firmware Support Package (FSP-M) for ChromeOS includes an pre-memory graphics driver which can be leveraged to display a text message thanks to the following FSP-M UPD (Updateable Product Data): - VgaInitControl (bitfield): Bit 0: Turn on graphics, setup VGA text mode and display `VgaMessage' text centered on the screen. Bit 1: Clear text and tear down VGA text mode and graphics before returning from FSP-M. - VbtPtr (address): Pointer to the VBT (Video BIOS Tables) binary. - VbtSize (unsigned int): Size of the VBT binary. - LidStatus (boolean): Due to limited resources at early boot stages, the text message is displayed on a single monitor. The lid status helps decide which display is the most appropriate. 0: Lid is closed: show the text message on the external display if available, do not display anything otherwise. 1: Lid is open: show the message on the internal display if available, use an external display if available otherwise. - VgaMessage (string): Text message to display. If the `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' flag is set, coreboot configures the UPDs above to display a text message during memory training and CSME update. The text message can be configured via the locale text mechanism using the `memory_training_desc' name. The `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' selects the LZ4 compression algorithm for VBT because LZMA decompression is not available in romstage by default and adding LZMA support increases the romstage binary size more than the VBT binary is reduced. BUG=b:279173035 TEST=Text message is displayed during memory training on a rex board Change-Id: I8e7772582b1895fa8e38780932346683be998558 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78244 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11soc/intel/cse: Add API to check if CSE Firmware update is requiredAnil Kumar
This patch adds a function to check if a CSE FW update is required during this boot. The function is expected to be used during use cases like Pre-Memory Sign of Life text display to inform user of a CSE Firmware update. Bug=279173035 TEST=build and boot on google/rex board. Call the function in romstage and confirm it returns True during CSE FW update and False otherwise Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If5fae95786d28d586566881bc4436812754636ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78243 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-11soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDsKilari Raasi
By default MarginLimitCheck and RMC UPDs are enabled in FSP which enables fast and cold boot retraining causing the boot time increase. So, disabling the same UPDs to fix it. Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11vc/intel/fsp/mtl: Update header files from 3323_86 to 3424_88Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3424_88, previous version being 3323_86. FSPM: 1. Add `MarginLimitCheck` UPD 2. Add pre-memory graphics UPDs i.e `LidStatus`, `VgaInitControl`,`VbtPtr`,`VbtSize`,`VgaMessage` 3. Address offset changes FSPS: 1. Add `Usb4CmMode` UPD 2. Address offset changes BUG=b:310108425 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I3f71cd739a607318fda06fa50d4a379d64857458 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78997 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-09arch/riscv/payload: Remove old RISC-V CSR namesLennart Eichhorn
LLVM/clang 17 removed support for CSR names that are no longer included in the RISC-V ISA Manual Privileged Specification since version 1.12. Related LLVM commit: https://reviews.llvm.org/D149278 Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132 Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-08util/docker/alma: Add Dockerfile.baseFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: Iab15fe908aa6ca81724ed7557caf70c38817ad25 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-08util/docker/rocky: Add Dockerfile.baseFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: I60e00932332801c0f62d88b7860afb330d9469e4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-08util/docker/archlinux: Rename Dockerfile to Dockerfile.baseFelix Singer
Rename Dockerfile to Dockerfile.base since additional Dockerfiles basing on this one will be added later. Change-Id: I70f2c89f739068749e1017524b6f8ef1b03d6456 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79344 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
2023-12-08util/docker/archlinux: Add more packages allowing CI buildsFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: I757e6dbac557bcb640777b819529a978bf54ed93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-08vendorcode/amd/opensil: Set up resource manager input blockArthur Heymans
Tell the resource manager in openSIL to distribute the available IO and MMIO ranges across the different PCI root bridges. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-08Makefile: Make vboot_fw.a a .PHONY targetJulius Werner
vboot_fw.a is built via a sub-invocation of make, but make is not able to track dependencies between different invocations. That means the toplevel make assumes that the vboot_fw.a target depends only on the dependencies explicitly listed in coreboot's Makefile (only config.h in this case), and thus assumes that if config.h didn't change it does not need to rebuild the library. This breaks incremental builds when files inside the vboot repository change. This patch marks the target as .PHONY so that it will always be rebuilt. The vboot Makefile's own dependency tracking will then ensure that on an incremental build we only rebuild the vboot sources that actually changed, so if nothing changed this will just add a simple and quick $(AR) call. Change-Id: I8bdd4e1589124914ba1e877e04b40ee709ea4140 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79375 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN"Zheng Bao
Updated Linux FW works with PCI gen3 speed and PSPP. This reverts commit 05c9a850fd21 ("mb/google/nipperkin: Fix WLAN to GEN2 speed") https://review.coreboot.org/c/coreboot/+/63593 and commit 76fddd963925 ("mb/google/nipperkin: Disable PSPP for WLAN") https://review.coreboot.org/c/coreboot/+/63722 The changes are overlapped and are reverted together. BUG=b:240426142 & b:228830362 The system is able to ran over 2500 cycles on Nipperkin with command suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \ --nofw_errors_fatal The whole variant_update_dxio_descriptors is empty and is pushed back to weak function. Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-12-08acpi.c: Fix generating pointer to cb_tables located >4GArthur Heymans
Use the generic resource_consumer method which works for memory both above and below 4G. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1bc553b18d08cee502b765166227810f8e619631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76181 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-08mb/google/rex/var/screebo: set audio GPIO pins based on fw_configTerry Cheong
Enable BT offload when I2S option is selected for screebo. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo. Fixes: https://review.coreboot.org/c/coreboot/+/77755 Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthchargeWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged, keep mainboard C port to conn0. BUG=b:312998945 TEST=can boot from external Type-c USB disk Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08mb/google/brox: Update configuration for USB portsIvy Jian
Update brox devicetree based on the latest schematics. - Configure typeC to EC mux ports settings. - Configure USB2/USB3 ports settings. - Configure TCSS ports settings. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-07acpi: add missing device/device.h includeFelix Held
The device/device.h provides the definition for struct device used in those files, so include this header file to make sure that it's not only included indirectly via some other header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-073rdparty/intel-microcode: Update submodule to upstream mainFelix Singer
Updating from commit id 6788bb0: 2023-08-08 12:04:21 -0600 - (microcode-20230808 Release) to commit id ece0d29: 2023-11-14 10:19:09 -0600 - (microcode-20231114 Release) This brings in 1 new commits: ece0d29 microcode-20231114 Release Change-Id: I1d65318015803d5ca11dcf52e4011f49cf3129a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-073rdparty/vboot: Update submodule to upstream mainFelix Singer
Updating from commit id ba7fd22d: 2023-11-29 01:50:20 +0000 - (Makefile: Always link libdl) to commit id db533497: 2023-12-05 20:09:44 +0000 - (host/lib/pkcs11: Remove superfluous 'nss' directory from include paths) This brings in 4 new commits: db533497 host/lib/pkcs11: Remove superfluous 'nss' directory from include paths 3307f1a7 tlcl: Add `TlclEvictControl()` support 0bd01137 tlcl: Remove the redundant bytes in TlclReadPublic 9afdf0f2 sign_official_build.sh: stop messing with +x Change-Id: Ib2ded699605dfa4032f4687e1e336297c0af1372 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06soc/amd/common: Move PCIe CLKREQ programming under fspMatt DeVillier
CLKREQ programming as currently implemented is completely dependent on FSP DXIO descriptors, so move under common/fsp/pci and rename the Kconfig to reflect the move. TEST=build google/{guybrush, skyrim, myst} Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06util/docker: Add build scriptFelix Singer
Integration for additional container images might be added to the Makefile at some later point. However, in order to build and test new images just add a simple script which fulfills that requirement until then. Change-Id: Ibd0a6d59f395e074c784452849650d7f03b4f1d8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06util/docker/alpine: Rename Dockerfile to Dockerfile.baseFelix Singer
Rename Dockerfile to Dockerfile.base since additional Dockerfiles basing on this one will be added later. Change-Id: I611feca234ae7600f9c17ae397f9f3903879c057 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06vendorcode/amd/opensil: Add initial setup and API callsArthur Heymans
- First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-06mb/google/brox: Generate RAM IDs for two modulesIvy Jian
Add the support LP5 RAM parts for brox: 1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E 2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:311450057 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ib17f26a310435e37088191594863a645aa751440 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-06sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetreeFelix Held
Since the EHCI controllers in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the EHCI device operations to the PCI devices during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetreeFelix Held
Since the XHCI controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the XHCI device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetreeFelix Held
Since the PCI bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the PCI bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetreeFelix Held
Since the SMBus controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the SMBus device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79168 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06commonlib/bsd: Use tabs instead of whitespacesVarshit Pandya
Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridgeFelix Held
Function 0 of the device that has the bridges to other buses is a dummy function that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on that device isn't enabled. That dummy device function is however not a PCI host bridge, so change the comment from 'Dummy Host Bridge' to 'Dummy device function'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79397 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06soc/amd/*/chipset.cb: don't call dummy device functions host bridgesFelix Held
Function 0 of the devices that have the bridges to other buses are dummy functions that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on those devices isn't enabled. Those dummy device functions are however not PCI host bridges, so change the comments from 'Dummy Host Bridge' to 'Dummy device function'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-06mb/google/rex/variants/deku: Enable CNVi PCI deviceEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I41a64252f08304ffc66fd782e54720252064ca49 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-06soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaultsFelix Held
Add defaults for the CONSOLE_UART_BASE_ADDRESS Kconfig symbol so that the SeaBIOS payload will know where the MMIO address of the UART is to build successfully without any additional user input during the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79395 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-06acpi/acpi_gic: Add GIC ITS subtableNaresh Solanki
Add support for generating GIC subtable ITS (Interrupt Translator Service). Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06acpi: Add IO Remapping Table structuresNaresh Solanki
Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-05acpi/acpi: make sure that table_ptr is non-NULL in acpidump_printFelix Held
While acpidump_print shouldn't be called with a NULL pointer as table_ptr argument, better add a check to not end up dereferencing the NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-05sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetreeFelix Held
Since the LPC bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the LPC bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-05mb/google/brox: Fix memory configShelley Chen
Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating the GPIOs needing to be initialized in romstage into the baseboard gpio.c file. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-04nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-04ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper casePaul Menzel
Building the Lenovo T60/T60p, iasl 20230628 shows the remark below: dsdt.asl 2099: PowerResource (FPwR, 0, 0) Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR) dsdt.asl 2118: Name (_PR0, Package () { FPwR }) Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR) Address it by making it all upper case. Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26 Fixes: 3ab13a8691cb ("ec/lenovo/h8/acpi/thermal: Add support for passive cooling") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79367 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04mb/google/rex/var/screebo: Override power limitsSubrata Banik
This patch allows variants to override the default baseboard PLx limits. Additionally, rearrange the include header files alphabetically. BUG=b:313667378 TEST=Able to boot google/screebo with modified power limits. Before: [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) After: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-04soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_SNina Wu
Update BND_NORTH_APB2_S's domain 5 permission to allow the access from APU. The APU requires certain information saved in BND_NORTH_APB2_S for voltage tuning. If this information cannot be retrieved, the APU may operate at a high frequency with low voltage. Consequently, the APU may not function as expected. Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79348 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04security/vboot: Add Kconfig option to clear recovery requestMichał Żygowski
For ChromeOS platform the recovery reason is cleared in vb2api_kernel_phase2 which is probably not called by any non-ChromeOS system. It results in the platform being stuck in recovery mode, e.g. when RW firmware verification fails. Even if the RW partition is flashed with correctly signed image, the persistent non-zero recovery reason will prevent vboot from attempting the RW partition check. Use the newly exposed vb2api_clear_recovery and VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE Kconfig option to clear the recovery reason and save it immediately to the VBNV. The idea is to let non-ChromeOS coreboot platform to clear the recovery reason when needed. TEST=Clear the recovery reason in mainboard_final function right before payload jump when RW partition is corrupted and RW partition is valid. In case it is corrupted, the platform stays in recovery mode, when valid the platform boots from RW partition. Tested on MSI PRO Z690-A DDR4. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7ffaf3e8f61a28a68c9802c184961b1b9bf9d617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74343 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04cpu/intel/model_206ax: Use macro IS_IVY_CPUPatrick Rudolph
Use existing macro instead of open coding magic numbers. No functionality change. Change-Id: If45f7f3f2b4226cedde6ff91b9848b9875f45f9f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79148 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-04mb/google/rex/variants/deku: Complete USB configurationEran Mitrani
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/variants/deku: Add basic DTTEran Mitrani
Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/deku: Enable LAN0, LAN1Eran Mitrani
google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04inteltool: memory: log PCI id of unknown devicesAlexander Couzens
Change-Id: I25396e5480c45729710b16345f997c78e8bcbccb Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-04mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14Subrata Banik
This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID which is identical to MCH ID 0x7d01 (index 1). TEST=Able to perform power limit configuration for google/ovis. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (19000, 28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-04mb/google/rex: Simplify power limit configuration usageSubrata Banik
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE configurations, relying instead on the refactored power limit flow. This flow allows for seamless overrides by the baseboard and/or by the variant board, if necessary. Specifically, this patch: - Removes PL_PERFORMANCE and PL_BASELINE configuration options from mainboard.c in the google/rex directory. - Relies on the baseboard_devtree_update() function, which is implemented by the respective baseboard, to handle power limit configuration. - Leverages the variant_devtree_update() function, which is a __weak implementation, to allow overrides by the variant directory. This simplification improves code readability and maintainability while maintaining the flexibility to handle power limit configurations as needed. Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04soc/intel/alderlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02acpi: Add PPTT supportDavid Milosevic
This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-02mb/google/rex: Enhance power limit override mechanismSubrata Banik
This patch expands the power limit override capability to include variants directories, enabling them to modify power limit settings configured by the baseboard. Previously, only the baseboard could override power limit settings. For instance, while the google/rex baseboard sets the PL1 max power limit to 15W, the google/screebo variant couldn't override this value. This enhancement empowers variants directories to override baseboard- configured power limit settings, allowing for greater flexibility and control over power limits. BUG=b:313667378 TEST=Able to call into _weak implementation of `variant_devtree_update` unless there is one override. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-02Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id eb91266f01db (2023-11-29): MDN: Update mendocino SMU to 90.43.0 to commit id 64cdd7c8ef19 (2023-12-01): Cezanne/PSP: clean up release notes This brings in 3 new commits: 64cdd7c8ef Cezanne/PSP: clean up release notes 54c45443b8 Stoneyridge: Drop PSP binaries for Bristol Ridge (BR) bfa3c44c8c Stoneyridge: Tidy up the PSP binaries folder Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79365 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-02soc/amd: Add DBG2 ACPI tableZheng Bao
Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtypeFelix Held
The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79219 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license headerNicholas Chin
Inteltool is GPLv2 licensed so all files that link to it should be GPLv2 by default. In addition, the contents of several of these headers were originally moved directly from gpio_groups.c, which is explicitly marked as GPL-2.0-only. Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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