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2023-10-06cpu/intel/model_206ax: Only use supported C-statesPatrick Rudolph
When advertising C-state using the ACPI _CST object, make sure to only advertise those that are supported by the CPU. Downgrade if it's not and make sure to not advertise duplicate states. Add debug prints for the finally selected mapping of ACPI C-state vs Intel CPU C-state. Test: Tested on Lenovo X220. All C-states are still advertised as all are supported. Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-10-06cpu/intel/model_206ax: Use haswell cstate_mapPatrick Rudolph
Make the code look like on newer platforms. This doesn't change functionality. Test: Lenovo X220 still boots and advertises all C-states as before. Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78193 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-06cpu/intel/model_206ax: Print supported C-statesPatrick Rudolph
According to the BWG C-states are processor specific and BIOS must check if a C-state is supported at all. Print the supported C-states in before ACPI _CNT generation. Test: Tested on Lenovo X220 using Intel i5-2540M. All C-states are reported as supported. Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78133 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-06arch/x86/cpu_common: Add cpu_get_c_substate_supportPatrick Rudolph
Add a function to get the number of substates supported by an Intel CPU C-state. Test: Can read out the supported C-state substates. Change-Id: Ie57e87609ea5d6ec6f37154e8b84f1e9574aa4a9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-10-06cbfs: Restore 32-bit padding in cbfs_headerIvan Jager
It was changed from a fixed size-1 array to a flexible array in commit 242bac0e162c ("…: Use C99 flexible arrays") which resulted in a change to the serialized format as the header size was no longer the same. That broke other tools that read CBFS files, like diffoscope https://github.com/NixOS/nixpkgs/issues/256896 Change-Id: I4199dcc4823469c5986ac967a55b1c85cc62f780 Signed-off-by: Ivan Jager <aij+git@mrph.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78239 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-06mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timingCong Yang
Based on the power sequence of the panel [1], the power on T3 sequence VSN to RESET should be larger than 1ms. Because the Power IC descending slope takes 2ms, actual measurement needs 3ms to meet the timing of panel sequence. [1] HX83102-J02_Datasheet_v03.pdf BUG=b:302212730 BRANCH=corsola TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78185 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-05Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id ae822f2d0db7 (2023-09-21): MDN: Restore SMU fw version 90.41.0 to commit id b1741d184add (2023-10-04): PCO: Update SMU firmware to 4.30.77.200 This brings in 1 new commit: b1741d184a PCO: Update SMU firmware to 4.30.77.200 BRANCH=zork BUG=b:299603947 Change-Id: I0ce75b762bda90a5fa3bc546de42bc5d55637e17 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-05soc/intel: separate slp-s0 residency counter frequency in LPIT tableSukumar Ghorai
Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Whereas slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created after kernel boot cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-05MAINTAINERS: Add Brya maintainerEric Lai
Add myself :p Change-Id: Ib2bd5d9e9c93cf09ce4bca6a55cb5fab137f1bbc Signed-off-by: Eric Lai <ericllai@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-05spi/winbond: Use spi_flash_bpbits in winbond_bpbits_to_regionDaniel Gröber
This consolidates the bp, tb, cmp, srp0 and srp1 variables under the new spi_flash_bpbits struct to allow treating them as one unit in the refactoring to follow. Change-Id: I2a1a77fb73047df733498c0fa8b8de1153c3b09e Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42113 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05spi: Add new struct spi_flash_bpbits for block protection bitsDaniel Gröber
Currently the block protection bits are being passed around as individual arguments. We will use this new struct to replace the corresponding arguments in the winbond_bpbits_to_region and winbond_set_write_protection functions. Change-Id: I02828b1f764aea29374e794001e74cdc86a94c92 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-10-05cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kBArthur Heymans
This fixes building lenovo/x200 with VBOOT. All supported CPUs have enough L2 cache to support this. Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-10-05mb/google/nissa/var/quandiso: Change camera fw_config feildRobert Chen
Quandiso reserve bit 11 for mipi camera usage. BUG=b:300574047 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78213 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05mb/google/nissa/var/quandiso: Add ALC1019 amp supportRobert Chen
BUG=b:300573763 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Iff8167695c302f7b58976516d651a81f1a429bee Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-05mb/google/nissa/var/uldren: Remove fw_config probe for TS and TPDtrain Hsu
When service center repair touchscreen or touchpad will change compatible device not specific one, the fw_config probe mechanism is not convenient for service center. Removing touchscreen and touchpad fw_config probe for the purpose. BUG=b:297840605 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77538 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05configs: Clean up config.google.skyrim.with_binaries defconfigMatt DeVillier
Drop the Cezanne FSP binaries (which were just placeholders), as well as all other defaults removed when running 'make savedefconfig' Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78195 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ixSeunghwan Kim
Turn off GPP_H13 (EN_PP3300_SD_X) in s0ix for power saving. It reduces about 3mW of power consumption in s0ix on pirrha proto board. BUG=b:300845527 TEST=Built and verified GPP_H13 voltage was 0V in s0ix. Also verified SD card worked after s0ix for 20 times. Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04mb/google/rex: Configure ISH UART TX/RX as NCBernardo Perez Priego
This patch reverses ISH UART pin configuration to allow ISH to enter into suspend mode. This UART port is for debugging purposes. BUG=b:302612549 TEST=On Google/rex platform with ISH enabled, do suspend_stress_test This test must pass Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I8aba45420744a3990e1f9637c3b31ea2e0f78f87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78049 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cmn/gfx: Add API to report presence of external displaySubrata Banik
This patch implements an API to report the presence of an external display on Intel silicon. The API uses information from the transcoder and framebuffer to determine if an external display is connected. For example, if the transcoder is attached to any DDI ports other than DDI-A (eDP), and the framebuffer is initialized, then it is likely that an external display is present. This information can be used by payloads to determine whether or not to power on the display, even if eDP is not initialized. BUG=b:299137940 TEST=Build and boot google/rex Scenarios: Booting with eDP alone: has_external_display value is 0 Booting with eDP + HDMI: has_external_display value is 0 Booting with HDMI alone: has_external_display value is 1 Booting with USB-C display alone: has_external_display value is 1 Change-Id: I77436940978c7fa9368d79394b46a5e794c32e42 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78080 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04{commonlib, libpayload}: Add "has_external_display" in coreboot tableSubrata Banik
This patch introduces a new coreboot table entry named "has_external_display" to understand if external display is attached. This information is useful to prevent graceful shutdown by payload when the LID is closed but an external display is present. This piece of the information will be gathered by coreboot and passed into the payload using this new entry aka external_display because payload (i.e., deptcharge) doesn't have any other way to determine if external display is available. BUG=b:299137940 TEST=Able to build and boot google/rex. w/o this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > System is powered off by depthcharge w/ this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > Booted to OS and device is alive/usable Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77796 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defsSubrata Banik
Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04drivers/intel/gma: Update port select bit definitionsSubrata Banik
This commit updates the port select bit definitions for the TRANS_DDI_FUNC_CTL registers in the Intel GMA driver to accommodate the changes introduced since TGL SoC. Specifically, the following changes were made: - Updated the DDI select bit definitions from 3-bits (bit 28-30) to 4-bits (bit 27-30). - Introduces `INTEL_GMA_VERSION_2` config to accommodate the port and pipe related differences between previous generation GMA register (TRANS_DDI_FUNC_CTL) to the current generation GMA register. This commit backports the change from the following upstream patch: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-3- lucas.demarchi@intel.com BUG=b:299137940 TEST=Able to build and boot google/rex. Change-Id: I815ffa90c2e235afd70baa7e3837e1f9af89b1b0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-04mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plugJoey Peng
Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/google/dedede/var/taranza: Enable wake on USB2/3 (un)plugSheng-Liang Pan
Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. The physical USB slot is 6, USB2 port5 for Bluetooth, total USB2 port num is 7, USB3 keep 6. BUG=b:300844110 TEST=Verify USB-A device could wake up Taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78068 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-10-04soc/intel/jasperlake: Enable wake from USBReka Norman
Use the common UWES ACPI method to enable wake from USB. The only difference to other SoCs is that JSL only has 8 USB2 ports, so the USB3 PORTSC register offset is different. BUG=b:300844110 TEST=When enabled on taranza, all USB2 and USB3 ports can wake from suspend Change-Id: Ibc90246965d5d809123e954847543d28d78498a5 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78086 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2023-10-04soc/intel: Move USB wake methods to a common ASL fileReka Norman
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-04mb/google/geralt: Remove SAMSUNG_ATANA33XC20 panel supportYidi Lin
This panel is never actually enabled on Geralt. The derived project won't use this panel either. Therefore, remove this panel support. BUG=none BRANCH=none TEST=emerge-geralt coreboot Change-Id: I97ed5b341724ed42098b2c17d0eb75eab881dbb1 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-04mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD IDYidi Lin
The tolerance of ADC voltage table is too small. Update the table values accordring to the suggestion from the hardware team. The patch is prepared for the derived projects. There is no actual issue now. BRANCH=none BUG=b:301908091 TEST=check firmware screen Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-04mb/google/brya/var/yavilla: Add VCM power control sequenceSerin Yeh
Add VCM power control to configure 2.8V and reset pin, and VCM can be powered on/off properly. BUG=b:292907385 TEST=Run ITS test Change-Id: I242025836fd50076a40ffcc4e5d4a5d5bc6fb4d0 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78170 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes
Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78198 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/starlabs/starbook/{adl,rpl}: Enable the CNVi deviceSean Rhodes
Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78197 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/starlabs/starbook/rpl: Update the VBT to 251Sean Rhodes
Updating FSP to v4301.01 caused a strange flicker when connecting an external display. Update the VBT to 251 from 242 with the exact same settings to resolve this. Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-04ec/starlabs/merlin: Update the Q EventsSean Rhodes
Simplify the Q events for the battery and charger to just notify when a status has changed. The EC will trigger these events when either has changed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3300be5254549fe5cd3b3490d9191240c6d36b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77405 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/amd: rework SPL file override and SPL fusing handlingFelix Held
The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a way to override the default SPL file configured in the SoC's fw.cfg file by passing the '--spl-table' parameter to amdfwtool which will then use the override instead of the SPL file from the fw.cfg file. When SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix call in the makefile will result in no '--spl-table' parameter being passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In order to not pass an SPL override by default, remove the default from the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the same SPL file as in fw.cfg file anyway. Now only when a mainboard sets this option to point to a file, that file will be used as an override. This override is used to include a special SPL file needed for the verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an empty string by default, neither the SPL_TABLE_FILE Kconfig option nor it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE, so remove the dependency in the Kconfig and the ifeq in the Makefile. Before this patch, the HAVE_SPL_FILE option controlled two things that shouldn't be controlled by the same Kconfig option: Only when HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into account, and it also controls if spl_fuse.c got added to the build which when added will send the SPL fusing command to the PSP. So the case of needing an SPL file override, but not updating the SPL fuses wasn't supported before. The SPL file in the amdfw part will be used by the PSP bootloader for the anti-rollback feature which makes sure that the SPL file version isn't lower than what is in the SPL fuses. For this the SPL file needs to be present in the PSP directory table. The SPL version check happens way before we're running code on the x86 cores. The SPL fusing PSP command that can be sent by coreboot will tell the PSP to update the SPL fuses so that the fused minimal SPL version will be updated to the current SPL version. Since the former HAVE_SPL_FILE option now only controls if the SPL fusing command will be sent to the PSP mailbox, rename it to PERFORM_SPL_FUSING to clarify what this will do and update the help text correctly describe what this does. TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman with Phoenix APU and Skyrim result in identical binaries. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78178 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for MeteorlakeKrishna Prasad Bhat
During CSE firmware downgrade, data is cleared. To preserve PSR data during downgrade, it needs to be backed up. Select SOC_INTEL_CSE_LITE_PSR config to ensure PSR backup related flow is executed on CSE Lite SKU. BRANCH=None BUG=b:273207144 TEST=Verify CSE firmware upgrade/downgrade on rex. Change-Id: I39af029a5f0c018a5db3ac68191764abfa9518ac Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76115 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/cse: Add entries to eventlog on PSR backup eventsKrishna Prasad Bhat
This patch adds eventlog entries for the below scenarios: 1. To indicate success or failure of PSR data back-up command 2. To indicate the loss of PSR data when CSE update is corrupted, and data clear command is issued to clear the data. 3. To indicate the loss of PSR data when CSE boot partition info response is corrupted and data back-up is not initiated. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-06-27 06:44:49 UTC Change-Id: I2459a2b941d28a87b6c78f75dbe8779d73328d7a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cse: Check PSR bit before issuing PSR backup commandAnil Kumar
Get PSR bit state using MKHI_FWCAPS_GET_FW_FEATURE_STATE HECI command Use this bit info to check if SKU supports PSR and consequently issue PSR_HECI_FW_DOWNGRADE_BACKUP command for PSR data backup during downgrade. BUG=b:273207144 TEST=build CB image and boot on google/rex board. Check for "PSR is supported in this SKU" message in coreboot logs to confirm that PSR bit is set in SKU Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cse: Back up PSR data during CSE FW downgradeAnil Kumar
During CSE FW downgrade we erase CSE data. This would result in Platform Service Record(PSR) data also to be erased. To avoid losing PSR data we need to make a backup before data clear. This patch sends PSR_HECI_FW_DOWNGRADE_BACKUP HECI command to CSE, informing the CSE to backup PSR data before a data clear operation during downgrade. CMOS memory is used to track the backup status. PENDING is the default state, it is updated to DONE once PSR_HECI_FW_DOWNGRADE_BACKUP HECI command is sent. PSR data can be backed up only post DRAM is initialized. The idea is to perform cse_fw_sync actions in ramstage when PSR is enabled on a platform. As part of the cse_fw_sync actions, when a firmware downgrade is requested the command to back-up data is sent. Once the backup has been done, trigger the firmware downgrade. BRANCH=None BUG=b:273207144 TEST=build CB image for google/rex board and check PSR backup command is being sent during a CSE FW downgrade. Also check PSR data is not lost/erased after a downgrade using intel PSR tool. Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74577 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/cse: Implement APIs to access PSR backup status in CMOSKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data. Since firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. So adding a CMOS variable for the same. This patch implements API to access PSR backup status stored in CMOS. The get API allows to retrieve the PSR backup status from CMOS memory. The update API allows to update the PSR backup status in CMOS. BRANCH=None BUG=b:273207144 TEST=Able to retrieve PSR backup status across resets. Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSETKrishna Prasad Bhat
CSE firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. In the subsequent patches, a CMOS structure to store PSR back-up status will be added. The current SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET of 68 can only store cse_specific_info, as ramtop is at offset 100 and PSR back-up status structure will not be able to fit within the range. This patch overrides the SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET to 161 to accommodate all CSE related info in adjacent CMOS memory. BUG=b:273207144 TEST=Verify CSE RW FW versions are stored in CMOS memory in rex. Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78054 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/mtl: Call cse_fill_bp_info early in romstageKrishna Prasad Bhat
Intel Platform Service Record(PSR) will be enabled on Meteor Lake platforms. cse_fw_sync actions happen in ramstage when PSR is enabled. To avoid the boot time penalty of sending the cse_get_bp_info in ramstage, call cse_fill_bp_info to get cse_bp_info response early in romstage and store in cbmem. This data can be later used in ramstage. BUG=b:273207144 TEST=Verify cse_bp_info is filled in romstage in rex. Change-Id: Ic0e8fb34f21ff07e182a7b848d38e9d329010028 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-04soc/intel/cse: Add function to get cse_bp_info earlyKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. Sending cse_get_bp_info command in ramstage takes additional boot time of ~45-55ms on rex. To avoid the boot time penalty, this patch provides an API to get the cse_bp_info in early romstage. The response data is then migrated to cbmem once memory is initialized. The same data in cbmem can be utilized in ramstage to perform other cse_fw_sync actions. This patch also adds check to validate cse_bp_info in cbmem and avoids sending the command again if the data is valid. BUG=b:273207144 TEST=Verify the command works in early romstage, data is migrated to cbmem and valid data is available in ramstage on rex. Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78053 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/google/nissa/var/yaviks: Add probe in devicetree for USB C1/A0 portWisley Chen
Add probe fw_config to USB C1/A0 port on daught_board for DB_1A sku. BUG=b:294456574 TEST=emerge-nissa coreboot Change-Id: I2261b0e4d2b673b6186a435cce8dc6a4ccacb0a7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-03util/docker: Fix setting SDK_VERSIONTim Crawford
The `SDK_VERSION` was incorrectly set to itself instead of keeping the `COREBOOT_IMAGE_TAG` variable, leaving it as an empty string. Test: Run `make coreboot-sdk` and see `SDK_VERSION` matches the tag. Fixes: d3a89cdb749a ("util/docker: Replace use of sed with build args") Change-Id: I4c8be7d0f7c1ac82da397e720d13a7075f22ec4d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03util/docker/coreboot-sdk: Remove superfluous NASM packageFelix Singer
Since commit 9b186e0ffef4 ("util/xcompile: Add NASM to xcompile") NASM from the coreboot toolchain is properly hooked up to the build system. So it's not needed to install the distro package. Remove it. Change-Id: I2ab0317531e25ae6d5baa8be8ac4d41dc145658f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/google/brya: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I1439f785cb9ceeefab9d24caa88e35bd43f68315 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/asus/p8x7x-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5ff9170ac6a3f50830a707dacf4f941587e531ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75076 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/prodrive: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iface0fd1d44649c6d9773940818e028e3d3a4292 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/amd/mayan: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5a321680b1b84ca0b2598d2446ff10257947a733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03dell/snb_ivb_workstations: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I80bd87aa2f97da74a1bbcf05b16f0d5980e142f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/lenovo/t520: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I6b71c7c5c9e32e21c757c0ed0e9c6bd9d58a4f75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78131 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/asus/h61-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I6a78efa4be2ee34e7dac06a8b8014da12b21fbdc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/intel/glkrvp: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I817faab0438a35d2e8859342e7c2b2dbaa0afeeb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78129 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/gigabyte/ga-h61m-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iec0829ba80d3d4b4bc79e14a97d085930c4c5202 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78128 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/intel/mtlrvp: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: If6b666478e15a8e843b50b60be490593349240bd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03soc/intel/alderlake: Hook up FSP repo for RPL-P/SMatt DeVillier
Now that Intel has publicly released FSP headers/binaries for RaptorLake-P/S client platforms, set the defaults accordingly if FSP_USE_REPO is not selected. This does not change any existing defaults as the RaptorLake headers in vendorcode are only used when FSP_USE_REPO is not set. TEST=build/boot google/brya (osiris) Change-Id: Ida92d269fcaf6f323599ec174f4dcedbbe65f03c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78190 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-10-03mb/google/dedede: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5527d5968be35f52b912d9d6e1d9f46f24569bbc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/siemens: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Ic199a60013ceedfd15b191a5fe707be6654ad3a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75078 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-10-03mb/google/rex: Fix ISH I2C pad for suspendCliff Huang
During suspend, the ISH I2C transactions cannot go through because the GPIO pads remain the pervious value. The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus active and functional during suspend. BUG=b:302612549 TEST=on Google/rex platform with ISH enabled, do suspend_stress_test and check that no i2c failure. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/78179 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Li1 Feng <li1.feng@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02security/tpm: Enable Hibernate on setup failureJon Murphy
Set default to enabled for hibernate on setup failure for all devices using a Google EC. This will have no impact on devices that don't bring the GSC down on hibernate, but will provide a recovery path for all devices that do. BUG=b:296439237 TEST=Force error on Skyrim with custom build, boot normally with normal build Change-Id: I2d9e8f75b25fb6c530a333024c342bea871eb85d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78098 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punctJonathon Hall
Librem 11's volume keys act as a PS/2 keyboard with only those two keys. Reduce the minimum number of top-row keys to 2. Make the "rest of keys" (alphanumerics, punctuation, etc.) optional. Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-02util/intelp2m: Support Jasper LakeJonathon Hall
Support generating Jasper Lake GPIO configuration from inteltool logs Change-Id: I519d27e0c91c8d9159224d9bc1c6e49c83270b7a Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2023-10-02drivers/pc80/pc: Split up PS/2 keyboard/mouse ACPI definitionsJonathon Hall
Separate these so a mainboard can describe a PS/2 keyboard without a PS/2 mouse or vice-versa. Librem 11 has a PS/2 keyboard for the volume keys, but does not have a PS/2 mouse, and the presence of a mouse device can cause the cursor to appear on the desktop incorrectly. ps2_controller.asl remains since many boards include it, it now just includes the two new files. Change-Id: I13a4c2caf8dc9e5004b775dc0a9ac2488e39f184 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78096 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bitsFelix Held
Simplify the code a bit by returning 0 early in the function when the SYSCFG_MSR_SMEE bit isn't set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78176 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/amd/common: use common physical address bit reservation codeFelix Held
Instead of having the get_usable_physical_address_bits function that only got used in the data fabric domain resource reporting code, drop this function, select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT in the common AMD non-CAR CPU and rename get_sme_reserved_address_bits to get_reserved_phys_addr_bits so that the common cpu_phys_address_size function will return the correct number of usable physical address bits which now can be used everywhere. The common AMD CAR CPU support is only selected by Stoneyridge which doesn't support secure memory encryption, so RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT isn't selected by the SOC_AMD_COMMON_BLOCK_CAR Kconfig option. Before only the MMIO region reporting took the reserved physical address bits into account, but now also the MTRR calculation will take those reserved bits into account. See the AMD64 Programmers Manual volume 2 (document number 24593) for details. Chapter 7.10.5 from revision 3.41 of this document was used as a reference. The MTRR handling code in older Linux kernels complains when the upper reserved bits in the MTRR mask weren't set, but sets them after complaining and then continues to boot. This issue is no longer present in version 6.5 of the Linux kernel. The calculation of the TSEG mask however still needs to take all physical bits into account, including the ones reserved for the memory encryption. When not setting the reserved bits in the TSEG mask, the Mandolin board with a Picasso APU won't boot to the OS any more due to not returning from SeaBIOS calling into the VBIOS. Haven't root-caused what exactly causes this breakage, but I think previously when something else was wrong with the SMM initialization, also something went wrong when calling into the VBIOS. TEST=Ubuntu 2023.10 nightly build boots on Mandolin via SeaBIOS and EDK2 and Windows 10 boots on it via EDK2. TEST=On Ubuntu 2022.04 LTS, the kernel complained with the following warning, but it still continues the boot process as described above: mtrr: your BIOS has configured an incorrect mask, fixing it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-02x86/include/arch/cpuid.h: Fix inline assemblyPatrick Rudolph
In the cpuid helper functions eax is always written to by the cpuid instruction, so add it to the output clobbered list. This prevents GCC from generating code with undefined behaviour when the function is inlined. Test: Verified that the generated assembly is sane and runtime tests showed no "strange" behaviour when calling cpuid functions. Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78192 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-10-02Update fsp submodule to upstream master branchMatt DeVillier
Updating from commit id a72794810884 (2023-09-07): IoT ADL-N MR1 (4172_00) to commit id 481ea7cf0bae (2023-09-19): Move to RaptorLakeFspBinPkg.dec This brings in 9 new commits: 481ea7cf0b Move to RaptorLakeFspBinPkg.dec 55e25b819e Raptor Lake FSP C.1.BD.40 2b0aac4f64 Raptor Lake FSP C.0.BD.40 3fa75657aa Add Client Raptor Lake FSP 8d24189361 Add Alder Lake and Raptor Lake to README.md 98f4a1fe2f Rename to AlderlakeSiliconPkg c78a6784cb Add FvLateSilicon for Alder Lake 849ce8261b Tiger Lake FSP A.0.7E.70 4b0b1eb4e3 Update SplitFspBin.py to latest from edk2 Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78189 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-10-02mb/google/corsola: Move common selects to BOARD_GOOGLE_CORSOLA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CORSOLA_COMMON. Thus, move all selects to the latter option. Change-Id: I498c6671b2dfc72820fc522744af7ce3b0a62930 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-02soc/mediatek/mt8188: devapc: Add SCP domain settingJason Chen
Configure the SCP to operate within domain 8, allowing it to access only the necessary registers. Any unauthorized access will be prevented by the DAPC. - Set SCP domain from domain 0 to domain 8. - Lock register settings down to prevent unexpected modification. BUG=b:270657858 TEST=scp bootup successful with dapc settings Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-02soc/mediatek/mt8188: devapc: Set master domainsNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch sets domains for masters: SSPM - domain 3 CPUEB - domain 14 PCIE0 - domain 2 SPM - domain 9 Change-Id: Ie3e1d5055e72824257b66d6257982652eeb05953 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77862 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/mediatek/mt8188: devapc: Update permission for master domain setupNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch updates the permission settings for domains 2, 3, 4, 5, 7, 8, 9, and 14, as these domains will be assigned masters in the upcoming patch. BUG=b:270657858 TEST=build pass Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77861 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-29arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORTFelix Held
Since also some AMD CPUs have reserved physical address bits that can't be used as normal address bits, introduce the RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT Kconfig option which gets selected by CPU_INTEL_COMMON, and use the new common option to configure if the specific SoC/CPU code implements get_reserved_phys_addr_bits or if the default of this returning 0 is used instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0059e63a160e60ddee280635bba72d363deca7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-29*/include/cpu: use unsigned int for number of address bitsFelix Held
The number of physical address bits and reserved address bits shouldn't ever be negative, so change the return type of cpu_phys_address_size, get_reserved_phys_addr_bits, and get_tme_keyid_bits from int to unsigned int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e67db6bf0c38f743b50e7273449cc028de13a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-29payloads/edk2: Update default branch for MrChromebox repo to 2023-09Matt DeVillier
Update the default branch used for MrChromebox's edk2 fork from 2023-06 to 2023-09. This updated branch has been rebased on the latest upstream stable tag (edk2-stable202308), and fixes some USB detection issues, as well the coreboot Kconfig for prefering internal or external boot devices. TEST=build/boot google boards link, panther, lulu,reef, ampton, akemi, banshee, zork, frostflow with edk2 payload selected. Change-Id: I7c5f9ae1ca4edd8211f55f4ecf2b3b495f473a43 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-29payloads/edk2: Move TPM disable to separate KconfigMatt DeVillier
Disabling TPM support in edk2 can actually cause problems booting from USB on some Intel-based boards with a CR50 TPM when using the edk2 GOP driver option, so rather than disable the TPM for all CR50 boards, restrict the default to only AMD boards, where the boot hang with TPM enabled was originally observed. TEST=build/boot Win11, Linux from usb on google/fizz when built with edk2 payload and edk2 GOP driver option selected. Change-Id: I01509fea2dd42b741c00abcf9fb8b936e895b932 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78031 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-29mb/google/guybrush: Disable WLAN ASPMTim Van Patten
ASPM on the WLAN PCIe bus introduces large latency spikes, which can be measured with cyclictest: $ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec down to 35-65 usec. These latency spikes can impact the user when real-time processes like Audio (cras) are starved of CPU time, leading to buffer underruns resulting in crackling/distorted audio. ASPM is already disabled for Nipperkin devices (CB:63537), so this CL disables it for both in the shared declaration of guybrush_czn_dxio_descriptors. Power impact for Dewatt: * ASPM enabled power_VideoCall.FDO_25min_webrtc w_energy_rate 7.425043688811071 power_Idle.default20min wh_energy_used 1.4164200000000022 * ASPM disabled power_VideoCall.FDO_25min_webrtc w_energy_rate 8.779998551703423 power_Idle.default20min wh_energy_used 1.4860800000000012 When using Google Meet over WiFi, power increases by ~1.5W. BUG=b:297970318 TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-29mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreenShon Wang
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. Support G2 TS have different slave address by fw_config BUG=b:295272539 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-29mb/asrock/b75m-itx: Order Kconfig selects alphabeticallyFelix Singer
Change-Id: I28a90c236e17d1ea15f5416fab8be7360494e92e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-28util/cbfstool: Revise lex/yacc (bison) generationHung-Te Lin
Revise the Makefile.inc rules for generating FMD parser files. - lex: If --header-file is supported then the lex (usually flex) should also support '-o' so we don't need to do redirection (-t). - yacc: Bison is already required by bincfg and sconfig so we can change the default parser compiler to Bison. That also allows us to use -o and --defines to override the output files. - both: Line directives are only helpful when debugging the scanner and the parser, so we should remove them to get better git diff results (-L for lex, -l for bison). Also regenerated the shipped files with latest version of flex (2.6.4) and bison (3.8.2). Change-Id: I15b58ff65dcd9f3f3a6095aa004091ff733ffec3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-28include/acpi/acpi_pld.h: Remove comment on PLDElyes Haouas
Remove comment on PLD horizontal position as ACPI spec 6.5 define that field: https://uefi.org/specs/ACPI/6.5/06_Device_Configuration.html?highlight=pld%20horizontal#buffer-0-return-value Change-Id: I228e0780699c223f1e3227fd45ec094e0c46205e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-28checkpatch.conf: Remove non-existent warningsElyes Haouas
Change-Id: I05ed882990c45625ad5f08a2bff21a7fda2055db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-28soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabledKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. This patch ensures SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE is selected when PSR is enabled. BUG=b:273207144 Change-Id: I7c9bf8b8606cf68ec798ff35129e92cd60bbb137 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78055 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/skyrim: Enable hibernate on TPM errJon Murphy
Enable hibernate on TPM setup error for Skyrim devices. BUG=b:296439237 TEST=Force the error by hard coding the return code and observe the device entering hibernate. BRANCH=None Change-Id: Ibf96b830f07dac98035d3152c8ec220685a912bc Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77668 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28drivers/tpm: Add tpm failure handlingJon Murphy
Add additional failure mode logic for the TPM to enable an automated recovery mode for GSC hangs. BUG=b:296439237 TEST=Force the error by hard coding the return code and observe the device entering hibernate. BRANCH=None Change-Id: Ieec7e9227d538130354dea8b772d0306cdda1237 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77667 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28drivers/tpm: Add return codes to TPM driverJon Murphy
Add additional failure mode reporting to the TPM driver to provide additional visibility into what failures are occurring. BUG=b:296439237 TEST=Verify code paths on Skyrim, ensure behavior is unchanged. BRANCH=None Change-Id: I77a653201acf1bddc1ed1e2af701c8d3dd4f0606 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77491 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-09-28treewide: convert to tpm_result_tJon Murphy
Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28treewide: convert to %#x hex printsJon Murphy
Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Enable ECAM MMCONF supportArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I70db8bf9f553fa9bfd2a5c20a1393119786047f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-28soc/amd/genoa/reset.c: Add reset methodsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifb4d7dda5fcf1ccacb901b24e4f7cf6945ee16e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76503 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa/southbridge.h: Add PM related macrosArthur Heymans
All verified with PPR. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: If288079310ba74333f04173978f6a123ce95f4d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-28soc/amd/genoa: Add timer & tsc supportArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add function to fetch common code dt configurationArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I5d5d3ff27ab0953844f9bbef30b6487fb480e29b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76500 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-09-28soc/amd/genoa: Deal with memory map for 32M or larger flashArthur Heymans
Only the lower half of the flash gets memory mapped below 4G in the current setup. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/76499 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add Kconfig/Makefile to generate PSP imageArthur Heymans
TESTED: AMD onyx reaches x86 code Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/rex/var/ovis: Add DPTF configurationJakub Czapiga
Configure PL1 and PL2 are configured for powerformance. Based on values from Intel Meteor Lake UH Power Map document ID:640982 BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add chipset.cbvbpandya
Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362 Signed-off-by: vbpandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78082 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-09-28mb/google/nissa/var/craask: Correct the USB setting by fw_configRen Kuo
Modify the settings: 1)Add fw_config probe on USB type C for "DB_1C_LTE". 2)Add fw_config probe on USB type A for "DB_1A_HDMI". BUG=b:296791122 TEST=build and check USB functions on craask Change-Id: I2775098ab380995e62f264bc51a430762c256c4b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/intel/alderlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/redrix with 32MB (W25Q256JWEIM) SPI-Flash. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-27Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id c6e5fba929ef (2023-09-02): MDN: Update ABL to version WABLMDN3516B01A to commit id ae822f2d0db7 (2023-09-21): MDN: Restore SMU fw version 90.41.0 This brings in 3 new commits: ae822f2d0d MDN: Restore SMU fw version 90.41.0 d4f752a6fa MDN: Restore MP2 fw version 0A.0D.00.06 7b7b04723b CZN: Update VBIOS to version 021 BUG=b:301109173 BRANCH=none Change-Id: I02b39ea94a23f7c25533347f06cd8488711c37cd Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-27Documentation: Update 4.22 release notes with x86 .data sectionJeremy Compostella
Change-Id: I2d6d611df8930ad0c473489eacee9019cbdacb9e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78000 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>