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2021-10-13mb/google/fizz: use SaGv_FixedHighMatt DeVillier
No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-13mb/google/wyvern: use SaGv_FixedHighMatt DeVillier
No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-13mb/google/guybrush: Override SPI Fast speedsKarthikeyan Ramasubramanian
Add support to override SPI fast speeds based on board version from both bootblock and verstage. Overrides apply for Guybrush only and SPI speed is overridden from 66 MHz to 100 MHz starting board version 4. This will help to improve the boot time on board version by ~60 ms and still allow the old boards to boot with 66 MHz. BUG=b:199779306 TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/spi: Support fast speed overrideKarthikeyan Ramasubramanian
Add support to override SPI ROM fast speed based on board version. This will allow boards to start at lower speeds during bringup and then switch to higher speeds after assessing the signal integrity. Also implement a default no-op override. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common: Add support to read and set SPI speeds from verstageKarthikeyan Ramasubramanian
Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock. BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I281531e506b56173471b918c746f58d1ad97162c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/*: Enable ACPIMMIO decode first in fch_pre_initFelix Held
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13mb/google/guybrush/var/nipperkin: update fw_config fieldKevin Chiu
update fw_config for nipperkin BUG=b:196909635 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Icd2c5509450e70aed158f146179f3a7fa24b547a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-13soc/mediatek/mt8192: add tracker dumpZhenguo Li
Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: I82f8e6e5f8ccb7f8246cae45a01a3ddd5f2966f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58244 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13soc/mediatek/mt8195: add tracker dumpZhenguo Li
Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13drivers/pc80/tpm: Fix wrong debug messageWerner Zeh
There is the wrong register offset printed in the debug log when the data register is written: 'lpc_tpm: Write reg 0x18 with 0xnn' should be 'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access. This can be confusing when searching for issues with the help of the TPM debug messages since the code itself is correct. Fix this error. Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-10-13mb/google/poppy: set SMBIOS enclosure type for all poppy variantsMatt DeVillier
Some poppy variants did not select a system type, which led to the default desktop type being set. Select the best fit enclosure type for each variant. Alphabetize the variant-specific options for improved readability. Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-13soc/amd/cezanne,soc/intel/common: rework CPPC table generationMichael Niewöhner
Make use of the newly introduced ACPI macros for CPPC table generation that currently exists of a bunch of confusing assignments of structs that only get partially filled. Test: dumped SSDT before and after do not differ. Change-Id: I844d191b1134b98e409240ede71e2751e51e2159 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-12mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh
Since the DRAM population is fixed to both channels on all mc_ehl boards there is no need to have this 'half_populated' variable at all. Simply use a fixed 'false' in the call of 'memcfg_init()' and delete this variable here. Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh
The preferred location for the SPD data on mc_ehl based boards is the HW-Info data structure. Inside this structure there is a field of 128 bytes available for the SPD data. So in order to use it construct a buffer in memory which is 256 bytes long (as FSP requests minimum 256 bytes for the SPD data) and where the upper 128 bytes are taken from HW-Info holding the needed timing parameters for LPDDR4. If there is a case where HW-Info is not accessible or where the contained SPD data is not valid (by checking the CRC in HW-Info SPD) fall back to fixed SPD data set in CBFS. Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCLZhi Li
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=b:202480992 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I811f32defd50a940a09f238d38c962d2caf42855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12soc/amd/common/block/include/psp_efs: use unsigned type for bitfieldFelix Held
For 1 bit long bit fields an unsigned type should be used. In this case uint32_t is used instead of a generic unsigned int for both consistency reasons with the rest of the file and to clarify that the bits will be packed into a 32 bit memory location. TEST=Resulting image of a timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic630d1709174d90336746bc37da504437c12643c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-12util/autoport/bd82x6x.go: Fix includesNicholas Chin
Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>, removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused includes), as the generated early_init.c uses pci_write_config16(). Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSRAngel Pons
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-12soc/intel/*/cpu.c: Add missing space in commentAngel Pons
Add a space before the `*/` C-style comment ending. Change-Id: Ic8928286c8237808b9e380e4393078792589615d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-12mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360APatrick Huang
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A" BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Cq-Depend: chromium:3195465 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-11mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO DescriptorMatt Papageorge
coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume. BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for CezanneMatt Papageorge
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as specified in the DXIO descriptors. This change requires FSP version 1.0.4 revision 2 otherwise setting this value does affect any FSP behavior. BUG=b:199780346 TEST=Verify toggling this value is reflected in FSP Cq-Depend: chrome-internal:4170351 Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11mb/google/guybrush: drop printk in bootblock_mainboard_early_initFelix Held
bootblock_mainboard_early_init gets called before console_init. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5a1da336e8dfc451177a5319a656c407c9fef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF writeFelix Held
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS updateFelix Held
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can remove the clearing of that bit. This is split off from the previous patch to be able to use timeless build to verify that the previous patch didn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: Use register and bit defines for eSPI setupRaul E Rangel
It's hard to understand what this code is doing because it uses hard coded values, so use the register and bit defines instead. BUG=none TEST=Timeless build for guybrush results in identical binary. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11soc/amd/cezanne/include/southbridge: add some more PM register definesFelix Held
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11soc/amd/common/include/lpc: add definitions for LPC LDRQ control bitsFelix Held
The definitions of bit 9 and 10 somehow got swapped between Picasso and Renoir/Cezanne, so put those in the Cezanne-specific header file. The reference code writes the same values to the raw bits in both, so we probably would still get away with putting this into the common header, but it's better to keep the defines consistent with the documentation in all cases. Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03 and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11libpayload: Add mock architectureJakub Czapiga
Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-11Makefile: Add src/soc/* to subdirsFurquan Shaikh
This change adds src/soc/* to subdirs before src/soc/*/* to allow Makefile in src/soc/* to provide any common helpers that will be useful for any src/soc/*/*. This is done to primarily ensure that the helpers are defined before being invoked by the SoC Makefile.inc. This is utilized by Intel CSE stitching mechanism in following changes. BUG=b:189177580 Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11mb/google/fizz: Drop broken USB ACPI codeMatt DeVillier
Fizz's USB ACPI code is intended to allow the OS to control port charging power, but since Fizz's ports are dumb (vs smart), it controls power to the port itself. The end result is that active ports become disabled when rebooting from Windows (10/11), and power is not restored until the device is powered down (a warm reboot is not sufficient). Subsequent Chromebox models (eg, Puff-based variants) don't bother with EC-controlled USB port power, so just drop it since it's problematic and provides no benefit. Test: boot Windows 10/11, reboot, observe active USB ports still functional (eg, USB KB still works) Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-11nb/intel/sandybridge: Populate meminfo when using MRCMatt DeVillier
Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older Sandy Bridge MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-11tests: Fix JUNIT_OUTPUT=y to write to files instead of stderrJakub Czapiga
CB:57144 broke JUNIT_OUTPUT=y, and unit-tests were writing to stderr instead of selected XML files, because test name used for XML file creation contains test path. Build system did not create necessary directiories, which CMocka required to create output files. This commit fixes writing to XML files with JUNIT_OUTPUT=y, but had to sacrifice path in test name, as it was causing a lot of problems (because CMocka does not know, how to write multiple test groups to one XML file, so it uses test group name [here __TEST_NAME__(test_group)] as part of output filename). Example: Test: tests/lib/rtc-test Output file: `build/tests/junit-tests_lib_rtc-test(tests).xml Change-Id: I09891aca923bf1271cafeaa09f89b6539022709c Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-10-11purism/librem_bdw: add support for ACPI brightness controlsMatt DeVillier
Test: build/boot Purism Librem 13v1, verify brightness controls work under Windows 10/11 with Tianocore payload. Change-Id: I27d04655adcd4a5dd42b025cfccb508cfd7aaeae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/caroline: Update _HID for digitizerMatt DeVillier
Caroline uses a Wacom digitizer, so adjust the ACPI HID so that the proper drivers attach under Windows/Linux. Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Build chromeos.c in verstageHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds chromeos.c in verstage to call get_ec_is_trusted() in vboot verstage_main(). Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Add GPIO EC in RW to early GPIO tablesHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in verstage. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-11mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198713670 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Iaba136a836b89f42411474ae733380e345cce687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/ocp/deltalake: Fix SMBIOS type 9 bugsJohnny Lin
1. Fix PCIe slot capabilities not being really read from an IIO root port device. The Hot-Plug capability of IIO root port cannot be enabled due to FSP limitation (v2.1-0.2.2.0), but the code should reflect the true capabilities by reading the root port device's CSR. 2. Initialize the characteristics flags to 0 in the for-loop to fix the issue of the flags values persists to the next iterations. Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results. For example without the fix it shows 'Hot-plug devices are supported' but in fact it's not: System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Hot-plug devices are supported Bus Address: 0000:00:1d.0 With the fix it shows the correct result: Handle 0x0016, DMI type 9, 19 bytes System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Bus Address: 0000:00:1d.0 Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7. The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# TEST: - Boot into system software Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer
In upcoming patches, we need mainboard specific adjustments. Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer
Enable LPC ComB on this mainboard. TEST: - Boot Linux and check with 'dmesg | grep tty' Change-Id: I7ec58685a723c177df18144011934b206e6425d0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
This mainboard uses an eSPI-to-LPC bridge for console output. For this reason, the internal LPSS UART must be disabled. Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer
Set the GPIOs according to the circuit diagram for this mainboard. Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer
This mainboard has only SATA Port 1 available with no device sleep feature. Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer
This mainboard has SD slot available and therefore it should be enabled. Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC only supports the standard speed. TEST: - Console Log shows no errors for RX6110SA during I2C2 init - Finalize device for I2C 00:32 shows correct date and time Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer
Since this variant uses different DDR4 devices compared to mc_ehl1 in a memory down configuration, the SPD data file must be adapted. In a first configuration we use Micron MT53D512M32D2NP modules. Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself: - SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1 - SPD Byte 5 - different Row and Column Address Bits - SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab - SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/google/dedede/var/pirika: Add Synaptics I2C touchpad deviceAlex1 Kao
Add Synaptics touchpad device support in devicetree. BUG=b:201043984 BRANCH=dedede TEST=Touchpad device function is OK Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11drivers/intel/dptf: return package with valueSumeet Pawnikar
Return the package with a value for the dptf user space service. This is required in write tpch method for pch device under dptf driver. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao
The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology. The OS is informed to reduce latency for upstream ports while connecting USB4/TBT devices. BUG=b:199757442 TEST=It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11drivers/intel/dptf: Add support for PCH methodsSumeet Pawnikar
Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAMEWisley Chen
Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name. BUG=b:197076844 TEST=build and check SSDT. Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS supportIan Feng
Add ALC5682-VS codec support in corori. ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of ssfc. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:201372531, b:194436265 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2021-10-11mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMeKevin Chiu
nipperkin has different H/W topology to guybrush that the eMMC device is on a different GPP: guybrush: GPP3 nipperkin: GPP2 Hence we need to enable RTD3 for nipperkin additionally which refers to this one: https://review.coreboot.org/c/coreboot/+/54967 BUG=b:200246826 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage run suspend test on eMMC sku Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11soc/intel/dnv_ns: drop redundancies from soc_fill_fadtMichael Niewöhner
Drop overrides from `soc_fill_fadt` that do not differ from what common ACPI code already sets. Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09payloads/tianocore/Kconfig: Extend help for bootsplash fileFelix Friedlander
Add more detail as to why a smaller-than-screen-size image is to be preferred, in contrast to other payloads' bootsplash images. Signed-off-by: Felix Friedlander <felix@ffetc.net> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-09mb/system76: tgl-u: Add gfx register for GMA ACPITim Crawford
Add gfx register to System76 TGL-U boards so GMA ACPI data is generated. Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZMichael Niewöhner
Reference: Intel doc#558579 rev2.2 Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-08mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tablesTim Wawrzynczak
Before attempting another commit 6260bf71 ("vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants all program EC_IN_RW as an input GPIO in bootblock so that it can be read from in verstage. Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2021-10-08Documentation: Explain how to join SlackPatrick Georgi
Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-08acpi: add macros for MSR and `unsupported` register resource typesMichael Niewöhner
These will be used in the follow-up change. Change-Id: I4723ffaf0adff8cb5b1717600ed4d1634768e2b7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-08mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVPBora Guvendik
This patch enables eNEM flow for ADL-M TEST=Able to build and boot ADL-M RVP using eNEM mode. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-08mb/prodrive/hermes: Enable SATA power optimizerAngel Pons
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD is still detected correctly by SeaBIOS (version 1.14.1). Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-08vc/mediatek/mt8195: fix misleading-indentation errorRex-BC Chen
Fix misleading-indentation error in dramc_pi_calibration_api.c. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-08payloads: Allow selecting UefiPayload on ARM64 platformsRex-BC Chen
Some ARM64 platforms (e.g., MT8195) are now able to compile and run EDK2 (UefiPayload). As a result, we should allow selecting PAYLOAD_TIANOCORE for ARM64 platforms. TEST=show strings correctly. 1. make menuconfig 2. select Mainboard -> Vendor=Google, model=Cherry 3. select Payload -> Add a payload -> Tianocorepayload 4. make -j 5. build/cbfstool build/coreboot.rom extract --name fallback/payload --file out.elf -m arm64 6. file out.elf # ELF 64-bit LSB executable, ARM aarch64 7. strings out.elf | grep tianocore # lots of tianocore stuff Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I10777a341d46240b91ceeeb1be26c33a0c5db839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58054 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-07mb/google/brya: Disable unused i2s pins for BT offloadSugnan Prabhu S
BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07mb/google/dedede/var/bugzzy: Update GPP_D5 configurationSeunghwan Kim
As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Doan <edoan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-07mb/google/brya: Add PsysPmax setting to 145WRyan Lin
This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-07libpayload: cbgfx: Clear screen by memcpyYu-Ping Wu
Instead of setting each pixel in the framebuffer, use memcpy() to clear screen faster. As this method should be fast enough, remove the fast path using memset(). The speed of clear_screen() on brya (x_resolution = 1920, bytes_per_line = 7680): - Using memset(): 15ms - Setting each pixel: 25ms - Using memcpy(): 14ms Also remove set_pixel_raw() since it's now used in only one place. BUG=none TEST=emerge-brya libpayload TEST=Saw developer screen on brya BRANCH=none Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-07soc/intel/tigerlake: Hook up GMA ACPI brightness controlsTim Crawford
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-07soc/intel/cannonlake: Enable x86_64 supportPatrick Rudolph
Select HAVE_EXP_X86_64_SUPPORT. Tested on prodrive/hermes: Boots into Linux. Change-Id: I033ccd5dc793b637a2ac4271b450335464564885 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-07security/vboot: Remove vb2ex_hwcrypto stubsYu-Ping Wu
Now that the vb2ex_hwcrypto_* stub functions are included in vboot fwlib (CL:2353775), we can remove the same stubs from coreboot. BUG=none TEST=emerge-brya coreboot TEST=emerge-cherry coreboot BRANCH=none Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-07soc/intel/dnv_ns: correct size of GPE0 registers in FADTMichael Niewöhner
There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC code sets a GPE0 block size of 4 byte length instead of 32 byte. The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit instead of 256 bit). Drop the overrides and let common ACPI code set the correct values based on `GPE0_REG_MAX`. Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-07soc/intel/denverton_ns: Always enable SpeedStepDmitry Ponamorev
When "SpeedStep" is disabled on an Intel Atom C3538, the maximum CPU clock speed is always 800 MHz(min CPU clock). Оperating system cannot change the frequency. Avoid this issue allow "Intel Speed step" technology for processors that do not have "Intel Turbo Boost". Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com>
2021-10-06sc7280: Enable UART driverRajesh Patil
Enable common Uart driver on sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06libpayload: Enable UART driver for sc7280Roja Rani Yarubandi
Add Qualcomm's QUPV3 serial driver for herobrine board BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335 Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06sc7280: Enable bootblock compressionRavi Kumar Bokka
This patch enables bootblock compression on SC7280. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Ref link: https://review.coreboot.org/c/coreboot/+/45855 BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06ec/google/chromeec: Register USB-C mux operationsDerek Huang
Register USB-C mux operations to the generic interface. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06ec/google/chromeec: Update google_chromeec_usb_pd_get_info()Derek Huang
google_chromeec_usb_pd_get_info() is used in ec.c only. Make it static and drop from ec.h. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06ec/google/chromeec: Add new API for USB-C mux handlingDerek Huang
Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux related information. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06ec/google/chromeec: Add APIs for USB-C DP ALT modeDerek Huang
Add API to allow AP to send the command to EC to enter DP ALT mode and API to wait for DP HPD event. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build coreboot and update your system. Boot the system you will find below message in the coreboot log with or without USB-C display connected: 'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06ec/google/chromeec: Update some PD and DisplayPort APIsDerek Huang
1. Update google_chromeec_pd_get_amode() to return bitmask. 2. Update google_chromeec_wait_for_displayport() to handle the updated return value of google_chromeec_pd_get_amode(). 3. Drop google_chromeec_pd_get_amode() from ec.h and make it static because it's not used outside of ec.c. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06ec/google/chromeec: Update google_chromeec_usb_pd_control()Derek Huang
Add parameter `active_cable` to obtain the cable type (active or passive) which is needed for USB-C configuration for some SoCs (at least Intel TGL and ADL), change the function name to google_chromeec_usb_pd_get_info() for better understanding. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06include/device: Generic interface for USB-C mux operationsDerek Huang
Create a generic interface to allow any of the EC or other drivers to provide set of USB-C mux operations. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06soc/intel/alderlake: Skip setting D0I3 bit for HECI devicesSubrata Banik
This patch skips setting D0I3 bit for all HECI devices by FSP. BUG=b:200644229 TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06soc/intel/alderlake: Perform `heci_finalize` prior to booting to OSSubrata Banik
`heci_finalize` ensures to put all heci devices to D3 by setting the D0i3 bit prior to booting to the OS. BUG=b:200644229 TEST=Verified D0i3 bit is set for all HECI devices prior to booting to OS. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06soc/intel/common: Helper function to check CSE device `devfn` statusSubrata Banik
This patch creates a helper function in cse common code block to check the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and CSE_4. Currently cse common code is only able to read the device state of `PCH_DEVFN_CSE` CSE device alone. Additionally, print `slot` and 'func' number of CSE devices in case the device is either disable or hidden. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P with this patch where the serial message listed the CSE devices that are disabled in the device tree as below: HECI: CSE device 16.01 is disabled HECI: CSE device 16.04 is disabled HECI: CSE device 16.05 is disabled Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devicesSubrata Banik
This patch ensures to pass cse device function number as argument for `set_cse_device_state()` to allow coreboot to perform enable/disable of D0i3 bit for all CSE devices to put the CSE device to Idle state or Active state. BUG=b:200644229 TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is able to put the CSE device toidle state or active state based on `devfn` as argument. Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-05lib/thread: Remove thread stack alignment requirementRaul E Rangel
CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer need to leak through to thread.c. This allows us to remove the alignment requirement. BUG=b:179699789 TEST=Reboot stress test guybrush 50 times. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05Revert "soc/amd/cezanne: Disable Co-op multitasking"Raul E Rangel
This reverts commit 5f80e7c764b9a1cb46beeaa490a4f60be04abcd4. The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2 into this patch to satisfy the dependency. BUG=b:194391185, b:179699789 TEST=reboot stress test guybrush for 50 iterations. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05lib/thread: Switch to using CPU_INFO_V2Raul E Rangel
CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1 cpu_info struct per cpu. This means that we no longer need to allocate it at the top of each threads stack. We can now in theory remove the CONFIG_STACK_SIZE alignment on the thread stack sizes. We can also in theory use threads in SMM if you are feeling venturesome. BUG=b:194391185, b:179699789 TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05arch/x86,cpu/x86: Introduce new method for accessing cpu_infoRaul E Rangel
There is currently a fundamental flaw in the current cpu_info() implementation. It assumes that current stack is CONFIG_STACK_SIZE aligned. This assumption breaks down when performing SMM relocation. The first step in performing SMM relocation is changing the SMBASE. This is accomplished by installing the smmstub at 0x00038000, which is the default SMM entry point. The stub is configured to set up a new stack with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point of smm_do_relocation located in RAMSTAGE RAM. This means that when smm_do_relocation is executed, it is running in SMM with a different sized stack. When cpu_info() gets called it will be using CONFIG_STACK_SIZE to calculate the location of the cpu_info struct. This results in reading random memory. Since cpu_info() has to run in multiple environments, we can't use a compile time constant to locate the cpu_info struct. This CL introduces a new way of locating cpu_info. It uses a per-cpu segment descriptor that points to a per-cpu segment that is allocated on the stack. By using a segment descriptor to point to the per-cpu data, we no longer need to calculate the location of the cpu_info struct. This has the following advantages: * Stacks no longer need to be CONFIG_STACK_SIZE aligned. * Accessing an unconfigured segment will result in an exception. This ensures no one can call cpu_info() from an unsupported environment. * Segment selectors are cleared when entering SMM and restored when leaving SMM. * There is a 1:1 mapping between cpu and cpu_info. When using COOP_MULTITASKING, a new cpu_info is currently allocated at the top of each thread's stack. This no longer needs to happen. This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so reviewers can feel more comfortable knowing most of the CL is a no-op. I would eventually like to remove most of the guards though. This CL does not touch the LEGACY_SMP_INIT code path. I don't have any way of testing it. The %gs segment was chosen over the %fs segment because it's what the linux kernel uses for per-cpu data in x86_64 mode. BUG=b:194391185, b:179699789 TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct %gs segment. Verify cpu_info looks sane. Verify booting to the OS works correctly with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05drivers/intel/fsp2_0: don't force-use `python2`Michael Niewöhner
Some distributions (e.g. NixOS, Debian) are actively working on getting rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and Python 3 as of upstream commit 0bc2b07, use whatever version is present by utilizing `python`. Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-05src/acpi to src/lib: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 05:37:18 +0000