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Remove the FADT from the individual mainboards and select and
use COMMON_FADT in the SOC instead. Set the ACPI revision to 5.
Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17138
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The STABLE build of FILO does not build anymore with the
current HEAD of coreboot. However, the current HEAD of FILO
does build with the current HEAD of coreboot. Update FILO
STABLE to FILO HEAD.
Change-Id: I4eece3aaada0dfdf4da106d5d260b5b361537558
Signed-off-by: Kevin Paul Herbert <kph@platinasystems.com>
Reviewed-on: https://review.coreboot.org/15195
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Actual build was missing libpayload path.
Change-Id: I519869d2d64c66b3d1d557595c7d13c22cd40819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17114
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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BUG=chrome-os-partner:57846
Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:57846
Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17092
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17111
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17110
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Also drop an odd comment about the resource allocator which seems to
work fine, with the right id.
Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17095
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Three things are required to enable wake-on-usb:
1. 5V to USB ports should be enabled in S3.
2. ASL file needs to have appropriate wake bit set.
3. XHCI controller should have the wake on attach/detach bit set for the
corresponding port in PORTSCN register.
Only part missing was #3.
This CL adds support to allow mainboard to define a bitmap in
devicetree corresponding to the ports that it wants to enable
wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in
PORTSCN would be set by xhci.asl for the appropriate ports.
BUG=chrome-os-partner:58734
BRANCH=None
TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb
attach/detach.
Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use intel common infrastructure to enable support for write-protecting
SPI flash range. Also, enable this protection for RW_MRC_CACHE.
BUG=chrome-os-partner:58896
TEST=Verified that write to RW_MRC_CACHE fails in OS using
"flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin"
Change-Id: I35df12bc295d141e314ec2cb092d904842432394
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:58896
Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17116
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.
BUG=chrome-os-partner:58896
Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17119
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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According to: "Intel ® 4 Series Chipset Family datasheet"
the IGD only has 1 IRQ pin.
Change-Id: I974f002f5a213056f4593a1eab10772527bb241d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17098
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This fixes an instability on 945gc where the IGD completely locks
up the system, when for instance tasked to do something with
compositing (like GNOME or GDM).
TESTED on ga-945gcm-s2l and d945gclf
TEST: launch GDM (gnome display manager)
Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17094
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Add support for Kaby Lake RVP3.
Use kunimitsu at commit 028200f as base.
Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel
LPDDR3 DIMM.
* Update board name to kblrvp
* Remove fsp 1.1 specific code( As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.
This is an initial commit does not have full support to boot.
Will add more CLs to boot Chrome OS with depthcharge.
Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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- Add comments dividing the payload sections.
- Move separate TINT and Memtest sections that were intermingled.
Change-Id: If0bbd6e182359c5186a8b958dd2c9ab9f0e0a3f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17046
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This reverts commit a52f883b100f3229dd4d86c81c08781993861f73
(https://review.coreboot.org/16587).
The above commit caused another sever kernel boot regression upwards
of 2 minutes to get through kernel init on quad core systems.
BUG=chrome-os-partner:58994
Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17121
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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CQ-DEPEND=CL:379684
BUG=chrome-os-partner:58064
TEST=verified on hana rev0
Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8
Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/379504
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia40543e5585845e5e6c178a620052c6a25927a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There are some sdram configurations that are no longer used. Drop them.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c
Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/399122
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17103
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It has nothing to do with git configuration, but is one of our
convenience scripts. It also has nothing to do with rebases (except that
it can be comfortably used through git rebase --exec)
Change-Id: Icc60c4de486a0027fe2230e93b441e62ba022193
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17101
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The relevant data is gone in Chrome OS depthcharge's master branch, and
so the script outlived its usefulness.
Change-Id: I04f3f168e23d4bc7c31692263a8eec3f97ee50de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17100
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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We found sdram may fail in pctl_cfg(), so we check the status in this
function. If it exceeds 100ms still in this function, we will restart
the system. We also found there are rare chances DDR training fails,
so also restart system in that case.
BUG=chrome-os-partner:57988
BRANCH=None
TEST=coreboot resets on failure and eventually the system comes up
Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11
Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/397439
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17045
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It's a better default than QEMU-armv7, which is currently the default
board when coreboot is configured for the first time, because most
coreboot development targets x86.
With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU
become:
git clone https://review.coreboot.org/coreboot.git && cd coreboot
make crossgcc-x86
make olddefconfig && make
qemu-system-x86_64 -bios build/coreboot.rom
Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16987
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Currently, the only supported DSM type is I2C
HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required
callbacks for generating ACPI AML codes for different function
identifiers for I2C HID.
BUG=chrome-os-partner:57846
Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add acpigen_write_dsm that generates ACPI AML code for _DSM
method. Caller should provide set of callbacks with callback[i]
corresponding to function index i of DSM method. Local0 and Local1
should not be used in any of the callbacks.
BUG=chrome-os-partner:57846
Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17090
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Export i2c_generic_fill_ssdt to allow other device-specific i2c
drivers to share and re-use the same code for generating AML code for
SSDT. In order to achieve this, following changes are required:
a. Add macro I2C_GENERIC_CONFIG that defines a structure with all
generic i2c device-tree properties. This macro should be placed by the
using driver at the start of its config structure.
b. Accept a callback function to add any device specific information to
SSDT. If generic driver is used directly by a device, callback would be
NULL. Other devices using a separate i2c driver can provide a callback
to add any properties to SSDT.
2. Allow device to provide _CID.
BUG=chrome-os-partner:57846
Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17089
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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1. If (LEqual (Op1, Op2))
2. ToBuffer (src, dst)
3. ToInteger (src, dst)
4. Buffer (n) { op1, op2 .... }
5. Return ( )
BUG=chrome-os-partner:57846
Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17088
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Define reset_gpio and enable_gpio for touchscreen device so that when
kernel puts this device into D3, we put the device into
reset. PowerResource _ON and _OFF routines are used to put the device
into D0 and D3 states.
BUG=chrome-os-partner:55988
Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
BUG=chrome-os-partner:55988
Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17082
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add support to allow a device to define PowerResource in its SSDT AML
code. PowerResouce ACPI generation expects SoC to define the
callbacks for generating AML code for GPIO manipulation.
Device requiring PowerResource needs to define following parameters:
1. Reset GPIO - Optional, GPIO to put device into reset or take it out
of reset.
2. Reset delay - Delay after reset GPIO is de-asserted (default 0).
3. Enable GPIO - Optional, GPIO to enabled device.
4. Enable delay - Delay after enable GPIO is asserted (default 0).
BUG=chrome-os-partner:55988
Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17081
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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Change-Id: I627338505fe1273366bc8f6f528d829b3162b371
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16916
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I7515288190ca57a321fb8ffe57a1181b638c336a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I2fae9e02e2fccaff97f2441fd17f8960e8ab9786
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ife9c0b8a1ab55fe683c88e34239d7f5806e1ff9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16971
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I765814450b82755f84c010f63bc8f919bb0cd4c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16970
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I48ae27c5460020b9118e6ade1a3e610b542999c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17040
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload,
entering main() with no supporting assembly code for startup. The Harvey port
is not complete so it just panics but ... it gets started.
We provide a standard payload function that takes a pointer argument
and makes the jump from machine to supervisor mode;
the days of kernels running in machine mode are over.
We do some small tweaks to the virtual memory code. We temporarily
disable two functions that won't work on some targets as register
numbers changed between 1.7 and 1.9. Once lowrisc catches up
we'll reenable them.
We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual
memory setup code.
We now use the _stack and _estack from memlayout so we know where things are.
As time goes on maybe we can kill all the magic numbers.
Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17058
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Since reading/toggling of GPIOs is platform-dependent task, provide an
interface with common functions to generate ACPI AML code for
manipulating GPIOs:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
Provide weak implementations of above functions. These functions are
expected to be implemented by every SoC that uses ACPI. This allows
drivers to easily generate ACPI AML code to interact GPIOs.
BUG=chrome-os-partner:55988
Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17080
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add functions to support generation of following AML operations:
1. PowerResource
2. Store
3. Or
4. And
5. Not
6. Debug
7. If
8. Else
9. Serialized method
BUG=chrome-os-partner:55988
Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17079
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Instead of using hard-coded values for emitting op codes and prefix
codes, define and use enum constants. With this change, it becomes
easier to read the code as well.
BUG=chrome-os-partner:55988
Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17078
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Return config->name if it is not NULL.
BUG=chrome-os-partner:55988
Change-Id: I9ae229949b73de6f991383daae8d962d6cf457a7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17077
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16967
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I4e628cbe11da32d291c4b8e4c7be91e9b0a86ad9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch adds a Makefile rule for mvmap2315 to install a BDB and
bootblock code in the BOOTBLOCK region. The resulting BDB has a
header and data both signed by a RSA-4096 key.
BUG=chrome-os-partner:57889
BRANCH=none
TEST=emerge-rotor coreboot and examined the output binary. Booted
coreboot.rom.
Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/16747
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This pulls in the bdb support for futility so that rotor can build.
Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17061
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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amdfwtool currently gets built for a specific size of ROM chip. This
should be updated to be passed in on the amdfwtool command line, but
until that's done, stop sharing the tool between builds.
This caused a problem for abuild when we tried changing the default
rom to one that used a 256KB rom chip. That wasn't large enough for
all of the files included by amdfwtool on several platforms, causing
build failures.
Change-Id: Ib08f3283e5be956f995a4a416a70b12a32462882
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17070
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Id42a2901cf76e6b867f62a752a38bbd6f6e5f54e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17059
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I9d27c276053c51021166f4b22d150060e415d08f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17025
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Add choice to select between FSP 1.1 & FSP2.0 driver to be used.
Change-Id: Ied7eab6f4a2191e0bcf220cde5ca519a3c3e2d76
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create the initial Snappy variant which refers to the Reef device.
Snappy, an Apollolake-platform, is deviated from reference board Reef.
BRANCH=master
BUG=None
TEST=Built & booted
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6
Reviewed-on: https://review.coreboot.org/17043
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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While we stub out free(), tools like coverity scan have no idea, and it
might change in the future. So free it.
Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260716
Reviewed-on: https://review.coreboot.org/17055
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17049
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Enable mainboard Kconfig to select between FSP 2.0 & 1.1 driver to be
used.
If mainboard Kconfig selects MAINBOARD_USES_FSP2_0 the FSP2_0 driver is
used else FSP1_1.
Change-Id: I724aaa87c2b0b8f6ddb18f61af9c37176ef632f2
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/17044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect.
The result is that 800MHz FSB CPUs now properly work with 667MHz RAM.
Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas
Elyes.
Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17038
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Previously the 945gc raminit only worked for 533MHz FSB CPUs.
This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are
taken from the vendor bios of Gigabyte ga-945gcm-s2l.
The result is that 1067MHz FSB CPUs now boot without problems.
800MHz FSB cpus still don't get past romstage.
Change-Id: I13a6b97d2e580512155edf66c48405a153121957
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17034
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Change-Id: Ib1aa4ad04dc8a584a751677aac5652cfa2e457df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This removes writes to FDI related registers since there is no FDI
link on these targets. This is likely a remainder from copying code from
later targets.
TESTED on Thinkpad x200 (gm45)
Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16993
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
This issue was found by Coverity Scan, CID 1364118.
Change-Id: Iba3c0f4f952729d9e0987d928b63ef8b8fe8841e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16992
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
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According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express
Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the
dotclock is below 225MHz and 5 when its above 225MHz.
Change-Id: I363039b6fd92051c4be4fdc88788f27527645944
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16991
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with
MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have
the option to be able to select SEABIOS_VGA_COREBOOT.
This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and
MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT
by default when SeaBIOS is chosen.
Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16981
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I19db898a5e76bf9c151934c7979316fb3737e881
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16965
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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This refactoring was already carried into RK3288 with commit 6911219
(edid: Add helper function to calculate bits-per-pixel dependent values)
but it seems that the code for RK3399 was copy&pasted from it too early
to pick this up. Fix that so that future Rockchip SoCs can copy&paste
the right thing.
Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17050
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The stack pointer (SP) is already printed in print_trap_information.
Don't print it again in handle_misaligned_{load,store}.
Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16996
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This reverts commit 2c8f3bd91b54e85b4d2e24894ee8bbbfb9ad8a31.
I mistakenly commited a WIP, sorry.
Change-Id: I3c66c688dbfd903ecf5303abcdf6b5ded84585c7
Reviewed-on: https://review.coreboot.org/17028
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Change-Id: I3f99190401d8df1415328da9c3b928194593901c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16989
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST
during s0ix entry.
BUG=chrome-os-partner:55877
TEST=S0ix functional on DVT
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875
Reviewed-on: https://review.coreboot.org/17030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Chrome OS builds always have some inherent differences to "standard"
libpayload configurations: they don't want to use curses or things like
storage drivers, they always use the coreboot framebuffer and USB, etc.
This patch reintroduces CONFIG_LP_CHROMEOS as an option that only
affects Kconfig defaults. This allows Chrome OS builds to select most of
what they need in one go and reduces board-specific .config files to
only the options that are really specific to that board.
Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on
x86 boards, which probably makes sense for all of libpayload (some but
far from all ARM boards use 8250-compatible UARTs, and we should
probably not default a platform option unless it's going to be correct
with very high probability).
BRANCH=None
BUG=None
TEST=Built and booted Jerry and Oak.
Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: e558f59
Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Currently every non-x86 platform supported by libpayload needs to
provide its own timer driver. Most of the ones we have accumulated there
look almost identical: For the frequency, return a preset constant. For
the value, read a 32-bit register, possibly read another 32-bit register
and shift+OR it with the previous one, then return that.
Let's replace this with a single .c file that can easily handle all of
those cases. Menuconfig convenience can still be maintained by providing
several presets that select different defaults for the driver's
configuration options (register address(es) and frequency).
Removes an "enabled" check from Samsung MCT driver since coreboot always
unconditionally enables that timer anyway.
CQ-DEPEND=CL:344809
BRANCH=None
BUG=None
TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s
Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770acd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: a036af6
Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347749
Reviewed-on: https://review.coreboot.org/17023
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Change-Id: Ib60061fa60e81e36234355aeecd6fefad8f5fed1
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/17037
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Ic5a3be1128f2f9a53d21e0a2c577192962260df6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17018
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Add a --force/-F option and enable it for cbfstool write, where it has
the effect of not testing if the fmap region contains a CBFS or if the
data to write is a CBFS image.
Change-Id: I02f72841a20db3d86d1b67ccf371bd40bb9a4d51
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16998
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Skip FSP initiated core/MP init as it is implemented and initiated
in coreboot.
Add soc core init to set up the following feature MSRs:
1. C-states
2. IO/Mwait redirection
BUG=chrome-os-partner:56922
BRANCH=None
TEST= Check C-state functioning using 'powertop'. Check 0xE2 and
0xE4 MSR to verify IO/Mwait redirection.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767
Reviewed-on: https://review.coreboot.org/16587
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Reef is using APL SoC SKU's with 6W TDP max. We've done
experiments and found the energy calculation is wrong with
the current VR solution. Experiments show that SoC TDP max
(6W) can be reached when RAPL PL1 is set to 12W. Therefore,
we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:56922
TEST=webGL performance(fps) not impacted before and after S3.
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0
Reviewed-on: https://review.coreboot.org/17029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch sets the package power limit (PL1) value in RAPL MSR
and disables MMIO register. Added configurable PL1 override
parameter to leverage full TDP capacity.
BUG=chrome-os-partner:56922
TEST=webGL performance(fps) not impacted before and after S3.
Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16884
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In FSP1.1 all the platform resets including global was handled
on its own without any intervention from coreboot.
In FSP2.0, any reset required will be notified to coreboot
and it is expected that coreboot will perform platform reset.
Hence, implement platform global reset hooks in coreboot. If Intel
ME is in non ERROR state then MEI message will able to perform
global reset else force global reset by writing 0x6 or 0xE to
0xCF9 port with PCH ETR3 register bit [20] set.
BUG=none
BRANCH=none
TEST=Verified platform global reset is working with MEI
message or writing to PCH ETR3.
Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16903
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
As per ME BWG, there are two mechanism to generate a Global
Reset (resets both host and Intel ME), one is through CF9h
IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set,
PMC PCI offset ACh[20]. Another is to issue the Global Reset
MEI message. Because any attempts to cause global reset without
synchronizing the two sides might cause unwanted side effects,
such as unwritten flash data that will get destroyed if the
host were to cause a global reset without informing Intel ME
firmware, the recommended method is to send a Global Reset MEI
message when the following conditions are met:
The PCH chipset firmware just needs to complete the Intel ME
Interface #1 initialization and check the Intel ME HFSTS state
if Intel ME is not in ERROR state and is accepting MEI commands
then firmware should be able to use Global Reset MEI message to
trigger global reset.
Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9
write of 0x06 or 0x0E command with PCH ETR3 register bit [20]
to perform the global reset.
BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message is able to perform platform
global issue in ME good state.
Change-Id: If326a137eeadaa695668b76b84c510e12c546024
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16902
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch programs and enables BAR for ME (bus:0/
device:0x16/function:0) device to have early ME communication.
BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message can able to perform platform
global reset during romstage.
Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17016
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
VBOOT_EC_SLOW_UPDATE should be selected if EC_GOOGLE_CHROMEEC is used as
building coreboot with Chrome OS support & without Chrome EC gives a
build error in coreboot.
Change-Id: I77eed0e1bdc1ba49381b72e21b0e18f573cadff0
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17020
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The clearing of the PMC registers was not being called resulting
in state persisting across reboots. This state is queried and
events are added to the eventlog like 'RTC reset' events. However,
the RTC reset event is a one time thing so it should only be logged
once. Without the clearing of the state the event was logged on
every boot.
BUG=chrome-os-partner:58496
Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17027
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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According to "G45: Volume 3: Display Register Intel ® 965G Express
Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the
VSYNC end should start at bit 16. This is also how Linux (at least 4.4)
sets this register, which can be seen with intel-gpu-tools.
TESTED on Lenovo thinkpad X60 (it does not change anything).
Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17015
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Change-Id: I53ba5ba790ae683082e712dc0b92f1ac5bf27ddb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16990
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16988
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I81ced8c6e02b00a3835e3b42c9cf2669b1b2bd3e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
[jn: Added XGCC_BIN variable to avoid requiring the tools in $PATH]
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16955
Tested-by: build bot (Jenkins)
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The pointers printed on unaligned memory accesses are now aligned to
those printed at the end of print_trap_information.
Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16983
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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On other architectures, the serial ports aren't mapped at 0x3f8.
WIP: I'm not sure how exactly the dependency should be encoded in
Kconfig.
Change-Id: Ia1de545325a53607f62d08e76b2f61b25edbe6ef
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16982
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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TEST=Compiled for and ran on spike; it booted as before.
Change-Id: Id173643a3571962406f9191db248b206235dca35
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16995
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Id30463d1809d0a31c9d3825642dce66f3ab2750d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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spike_util.h:
- (LOG_)REGBYTES and STORE are already defined in
arch/riscv/include/bits.h.
- TOHOST_CMD, FROMHOST_* are helper macros for the deprecated
Host-Target Interface (HTIF).
qemu_util.c:
- mcall_query_memory now uses mprv_write_ulong instead of first
translating the address and then accessing it normally. Thus,
translate_address isn't used anymore.
- Several functions used the deprecated HTIF CSRs mtohost/mfromhost.
They have mostly been replaced by stub implementations.
- htif_interrupt and testPrint were unused and have been deleted.
spike_util.c:
- translate_address and testPrint were unused and have been deleted.
After this commit, spike_util.c and qemu_util.c are exactly the same and
can be moved to a common location.
Change-Id: I1789bad8bbab964c3f2f0480de8d97588c68ceaf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16985
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I277cc9ae22cd33f2cd9ded808960349d09e8670d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There is no code which uses the backup space in TPM created for vboot
nvram.
All chromebooks currently supported at the trunk store vboot nvram
in flash directly or as a backup.
BUG=chrome-os-partner:47915
BRANCH=none
TEST=emerge-samus coreboot
Change-Id: I9445dfd822826d668b3bfed8ca50dc9386f2b2b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5cee2d54c96ad7952af2a2c1f773ba09c5248f41
Original-Change-Id: Ied0cec0ed489df3b39f6b9afd3941f804557944f
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/395507
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/16997
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch adds '--includes' option to 'git config --global' command
to allow user name and email to be defined in a file included from
the global gitconfig (~/.gitconfig) file.
BUG=none
BRANCH=none
TEST=make gitconfig with ~/.gitconfig including another file which
defines user.name and email.
Change-Id: I4fe61078b143c3a2e26b0be69c3ca8e6f069d8b0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/16912
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This enables viewing more than ~20 files in the file list on the left.
Arrows are added to indicate that more items are available off-screen.
This mimics what was done in pci_module.
Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14546
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Regardless of the payload chosen a file etc/ps2-keyboard-spinup
is added to cbfs. With this fix this file is only added to cbfs when
seabios is choses as a payload.
Change-Id: I37cf4c998856db2d297356776752643dba46a8f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16146
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Some devices have no LVDS output but if no VGA is connected or
no EDID can be found, it will try to init LVDS.
This patch detects the presence of an LVDS panel and makes sure that
LVDS is not initialized when it is absent.
Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16513
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The CPU_MICROCODE_BLOB_CBFS_LOC should only be specified for COREBOOT CBFS,
not for other CBFS.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu
Change-Id: I58bb289e6c9add2647876ef817b7920f6e7b427a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16932
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This reuses linux code (at least 4.1) to compute the graphic clock
divisors for LVDS displays on the gm45 northbridge.
The divisors m1, m2, n, p1, p2 need to be such that
"BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)
/ (p1 * p2)" is as close as possible to the target_frequency.
On g4x hardware the BASE_FREQUENCY is 96000kHz.
This potentially increases LVDS display compatibility.
Change-Id: I2323af5756431e89769f95059790f5a922af14b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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