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2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: pchandri <preetham.chandrian@intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13138 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29arch/arm64: Override bl31 timestamp with coreboot build timestampPatrick Georgi
If coreboot's build process is reproducible (eg. using the latest git timestamp as source), bl31 is, too. This requires an arm-trusted-firmware side merge first (in progress) and an update of our reference commit for the submodule, but it also doesn't hurt anything because it merely sets a variable that currently goes unused. Change-Id: If139538a2fab5b3a70c67f4625aa2596532308f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13497 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-29superio/winbond/w83667hg-a: Add support for W83667HG-ATimothy Pearson
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While the Nuvoton NCT5572D is effectively the same core, and a close enough match to get things working initially, the W83667HG-A has a different LDN mapping and several extra features that require a separate support driver. Clone the Nuvoton NCT5572D and modify according to the W83667HG-A datasheet, version 1.4. Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13156 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-29southbridge/amd/sb700: Add missing DMA setup step from AMD RRGTimothy Pearson
Change-Id: I412a0e5f2e0686b10a295dd7c0e9b537dc1a0940 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13154 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL fileTimothy Pearson
Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13153 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Enable ASUS MIO audio optionTimothy Pearson
The KGPE-D16 supports an optional MIO audio card, which connects to the on-board HDA interface of the SP5100. Enable the HDA interface for use with the MIO card. Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13152 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Move memory test before IMD setupTimothy Pearson
Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13151 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29nb/amdmct/mct_ddr3: Enable mainboard voltage setTimothy Pearson
The existing code used an incorrect macro name to check for mainboard DRAM voltage set support, and as a result no voltages were actually set. Furthermore, the existing code did not contain a centralized voltage assumption for boards that did not have a DIMM voltage set implementation. Use the correct macro name to test for boards with voltage set implementation, and provide a basic fallback to 1.5V operation for boards without a voltage set implementation. Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13150 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson
The existing code generated an incorrect boot APIC ID from node and core number for single node packages, leading to a boot failure when the second node was installed. Properly generate the boot APIC ID from node and core number. Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13149 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.Damien Zammit
Fixed incorrect comment regarding port 80 LPC route. Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstatesDamien Zammit
Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13465 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000Damien Zammit
Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13129 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-01-29nb/intel/x4x: Move to early cbmemDamien Zammit
Previously with errors in the ram init, early cbmem was disabled. Now that the ram is working correctly, set as early cbmem platform and update all (1) boards to use it. Tested on GA-G41M-ES2L Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13131 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29nb/intel/x4x: Cleanup gma.cDamien Zammit
Tidy up the code and move vga_textmode_init() later Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13128 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29nb/intel/x4x: Tidy up raminit and fix msbpos() functionDamien Zammit
- Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13127 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29nb/intel/x4x: Tidy up northbridgeDamien Zammit
- Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29nb/intel/x4x: Fix memory hole with both channels populatedDamien Zammit
Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13125 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-28src/: give scripts a .sh extension for easy identificationMartin Roth
Just rename the two scripts that are in the src/ tree to give them a .sh extension. Since we generally expect files in the src directory to be source files, this allows to identify these as scripts easily. Change-Id: I0ab20a083880370164488d37a752ba2d5a192fdc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28via/cx700: Use zeroptr over 0Patrick Georgi
This eliminates all "ud2" instances from romstage disassembly. Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/13488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Provide a gcc-safe zero pointerPatrick Georgi
zeroptr is a linker object pointing at 0 that can be used to thwart GCC's (and other compilers') "dereferencing NULL is undefined" optimization strategy when it gets in the way. Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12294 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Add interface to program USB2_COMPBG registershkim
Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Tested-by: shkim <sh_.kim@samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen@intel.com> Signed-off-by: shkim <sh_.kim@samsung.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.Freddy Paul
TEST=Plug/Unplug AC Adapter multiple times and make sure device is charging properly. Original-Reviewed-on: https://chromium-review.googlesource.com/303990 Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Original-Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Freddy Paul <freddy.paul@intel.com> Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12748 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi/DPTF: Write TCHG state on AC connect.Jenny TC
DPTF should update the charger cooling device state during boot time and every 3 seconds after boot. But 3 seconds polling doesn't seems to be working with current version of DPTF. This impacts charging since DPTF writes states 4 when charger is not connected at boot time. On connecting the charger, DPTF doesn't write 0 to enable charging. This issue is addressed by calling the PPPC function to read cooling device state and passing the value to SPPC to set cooling device state. This doesn't compromise safety since DPTF can override this value later based on the platform thermal condition. Also this provides additional safety measure in the unlikely event that DPTF crashes and is not re-spawned by OS. With this patch even after DPTF crashes, if the power adapter is plugged it would still allow the system to charge correctly. Original-Reviewed-on: https://chromium-review.googlesource.com/288460 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Jenny Tc <jenny.tc@intel.com> Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12729 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Update DPTF parameters to higher temperature.Divagar Mohandass
Fish bowl HTML5 graphics benchmark with 250 fish is not reaching 60 FPS. This change will update the DPTF parameters to accommodate this test. TEST=Run fish bowl benchmark with 250 fish and check for 60 FPS. Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302208 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi: Fix CID1 offset in commentHannah Williams
Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 Reviewed-on: https://review.coreboot.org/13483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix for auto wake from S5Hannah Williams
Disabling S5 wake from touch panel and trackpad TEST=Build and boot the platform. TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid Plug AC in -> EC boots up and AP will shutdown the platform and open Lid -> platform boots to OS. Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://review.coreboot.org/13425 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Fix for Crossystem "wpsw_cur" statusKumar, Gomathi
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-on: https://review.coreboot.org/13424 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix issues found during static code analysisRavi Sarawadi
TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Get Boot Flash Write Protect statusHannah Williams
Read GPIO to get the status Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13186 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Enable CA MirrorShobhit Srivastava
Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12749 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/cyan: Disable SD Card Detect Simulation in FSPHannah Williams
CQ-DEPEND=CL:12742 Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Disable SD Card Detect Simulation in FSPHannah Williams
CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 Reviewed-on: https://review.coreboot.org/13035 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Disable SD card detect simulation in FSPDivya Sasidharan
CQ-DEPEND=CL:13038 Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Original-Reviewed-on: https://chromium-review.googlesource.com/311850 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Set max frequency to be turbo frequencyHannah Williams
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12736 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Remove support for older rev boardsHannah Williams
Cleaning up code to remove support for early revs of Strago board Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13434 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Configure Boot Flash Write Protect status GPIOHannah Williams
Set up the GPIO(MF_ISH_GPIO_4) to read WP status. TEST=Use crossystem to read the WP status Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff Original-Reviewed-on: https://chromium-review.googlesource.com/302424 Original-Tested-by: John Zhao <john.zhao@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13185 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Enable native mode on sd card cd lineJagadish Krishnamoorthy
Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12741 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Disable unused lines on Gpio North BankJagadish Krishnamoorthy
The unused lines leads to spurious interrupts on few of the systems. TEST=run suspend_stress test and make sure that kbd is working. Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313417 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13176 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix DSP clockfdurairx
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28util/cbfstool: add 'compact' commandAaron Durbin
While assembling CBFS images within the RW slots on Chrome OS machines the current approach is to 'cbfstool copy' from the RO CBFS to each RW CBFS. Additional fixups are required such as removing unneeded files from the RW CBFS (e.g. verstage) as well as removing and adding back files with the proper arguments (FSP relocation as well as romstage XIP relocation). This ends up leaving holes in the RW CBFS. To speed up RW CBFS slot hashing it's beneficial to pack all non-empty files together at the beginning of the CBFS. Therefore, provide the 'compact' command which bubbles all the empty entries to the end of the CBFS. Change-Id: I8311172d71a2ccfccab384f8286cf9f21a17dec9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13479 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28util/cbfstool: add machine parseable printAaron Durbin
In order to more easily process the output of 'cbfstool print' with other tools provide a -k option which spits out the tab-separated header and fields: Name Offset Type Metadata Size Data Size Total Size ALIGN_UP(Offset + Total Size, 64) would be the start of the next entry. Also, one can analzye the overhead and offsets of each file more easily. Example output (note: tabs aren't in here): $ ./coreboot-builds/sharedutils/cbfstool/cbfstool test.serial.bin print -r FW_MAIN_A -k Performing operation on 'FW_MAIN_A' region... Name Offset Type Metadata Size Data Size Total Size cmos_layout.bin 0x0 cmos_layout 0x38 0x48c 0x4c4 dmic-2ch-48khz-16b.bin 0x500 raw 0x48 0xb68 0xbb0 dmic-2ch-48khz-32b.bin 0x10c0 raw 0x48 0xb68 0xbb0 nau88l25-2ch-48khz-24b.bin 0x1c80 raw 0x48 0x54 0x9c ssm4567-render-2ch-48khz-24b.bin 0x1d40 raw 0x58 0x54 0xac ssm4567-capture-4ch-48khz-32b.bin 0x1e00 raw 0x58 0x54 0xac vbt.bin 0x1ec0 optionrom 0x38 0x1000 0x1038 spd.bin 0x2f00 spd 0x38 0x600 0x638 config 0x3540 raw 0x38 0x1ab7 0x1aef revision 0x5040 raw 0x38 0x25e 0x296 font.bin 0x5300 raw 0x38 0x77f 0x7b7 vbgfx.bin 0x5ac0 raw 0x38 0x32f8 0x3330 locales 0x8e00 raw 0x28 0x2 0x2a locale_en.bin 0x8e40 raw 0x38 0x29f6 0x2a2e u-boot.dtb 0xb880 mrc_cache 0x38 0xff1 0x1029 (empty) 0xc8c0 null 0x64 0xadf4 0xae58 fallback/ramstage 0x17740 stage 0x38 0x15238 0x15270 (empty) 0x2c9c0 null 0x64 0xd2c4 0xd328 fallback/payload 0x39d00 payload 0x38 0x12245 0x1227d cpu_microcode_blob.bin 0x4bf80 microcode 0x60 0x17000 0x17060 (empty) 0x63000 null 0x28 0x37cf98 0x37cfc0 Change-Id: I1c5f8c1b5f2f980033d6c954c9840299c6268431 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28mb/intel/d510mo: Use SATA AHCI by defaultDamien Zammit
Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-28mb/intel/d510mo: Use native gfx initializationDamien Zammit
Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13034 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDTDamien Zammit
Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13453 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-28mb/intel/d510mo: Add missing GPIO and GPENDamien Zammit
Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13452 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28nb/intel/pineview: Native VGA init (CRT)Damien Zammit
VGA grub console works but display wobbles left/right drm/i915 driver reports one error: - [drm:i915_irq_handler] *ERROR* pipe A underrun - Monitor does not display 1920x1080 after modeset - Other resolutions look out of sync Cause: suspect single bug in raminit (chipset init) Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12921 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28drivers/intel/fsp1_1: Remove extra include referencesLee Leahy
Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-28Move object files to $(obj)/<class>/Nico Huber
Instead of tagging object files with .<class>, move them to a <class> directory below $(obj)/. This way we can keep a 1:1 mapping between source- and object-file names. The 1:1 mapping is a prerequisite for Ada, where the compiler refuses any other object-file name. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13181 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-28Makefile: Make full use of src-to-obj macroNico Huber
There were several spots in the tree where the path to a per class object file was hardcoded. To make use of the src-to-obj macro for this, it had to be moved before the inclusion of subdirs. Which is fine, as it doesn't have dependencies beside $(obj). Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.Kane Chen
LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage TEST=Test on Strago and make sure the leakage is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352 Original-Reviewed-on: https://chromium-review.googlesource.com/317020 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13175 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: EC_IN_RW gpio input configuration.Divagar Mohandass
Configure EC_IN_RW signal as gpio input. TEST=Boot to Chrome OS in normal mode and enter recovery mode use ctrl-d to switch to Dev mode. Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304040 Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/13124 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Clean up DDR configuration.Divagar Mohandass
This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13122 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Disable unused devices.Divagar Mohandass
This change will disable unused devices in device tree to improve boot performance. TEST=Build/Flash CB and boot to OS. verify Touch screen, Audio, WIFI and Track pad functionality. Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/300943 Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Gomathi Kumar <gomathi.kumar@intel.com> Reviewed-on: https://review.coreboot.org/13423 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27soc/braswell: Fix leakage on V1P8S railShobhit Srivastava
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27soc/braswell: Add macro NATIVE_INT_PU20KHannah Williams
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13054 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27intel/strago: Fix GPIO configHannah Williams
Fix GPIO config for this board: - SD card detect to GPI - SATA GPI to not used - GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination - I2C4 SDA and SCL from not used to Native Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13431 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEnHannah Williams
Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27drivers/intel/fsp1_1: Enable builds without MRC cacheLee Leahy
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27intel/sklrvp: Remove mainboardMartin Roth
The Intel Skylake RVP3 mainboard is not building, and according to Intel, there is no plan to continue working on it for coreboot. The intel/kunimitsu board is the Skylake reference design for coreboot.org. Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13469 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-01-27ectool: fix NetBSD compilationAndrey Korolyov
Since NetBSD does not support uname -o, push check for CygWin inside separate non-failing condition in Makefile. Change-Id: Ibd264384f49b33412f0ef8554bd9c9fb8f60a892 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-27chromeos: vpd: Avoid reading uninitialized VPDsJulius Werner
This patch adds a check to the VPD parsing code to avoid reading the whole thing if the first byte ('type' of the first VPD entry) is 0x00 or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types which should never occur as the first entry, so this usually means that the VPD FMAP section has simply never been initialized correctly. This early abort avoids wasting time to read the whole section from SPI flash (which we'd otherwise have to since we're not going to find a Google VPD 2.0 header either). BRANCH=None BUG=None TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to 1.5ms. Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720 Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322897 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/13467 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27chromeos: Add timestamps to measure VPD read timesJulius Werner
This patch adds three timestamps to coreboot and the cbmem utility that track the time required to read in the Chrome OS Vital Product Data (VPD) blocks (RO and RW). It's useful to account for these like all other large flash accesses, since their size is variable. BRANCH=None BUG=None TEST=Booted Oak, found my weird 100ms gap at the start of ramstage properly accounted for. Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234 Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322831 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27cbfstool: Fix broken alignment because of flashmapWerner Zeh
With the introduction of flashmap cbfs alignment of files gets broken because flashmap is located at the beginning of the flash and cbfstool didn't take care about that offset. This commit fixes the alignment in cbfs. Change-Id: Idebb86d4c691b49a351a402ef79c62d31622c773 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13417 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-27build system: Fix UPDATE_IMAGEPatrick Georgi
A quote was missing in a command. Change-Id: I04148538007e5c450c6be113aab8a7fbb534db26 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reported-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13474 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-26arch/x86: Drop arch/pciconf.hStefan Reinauer
It's unused, so get rid of it. Change-Id: I28c6dc0208686edc3aabaf624773ea70350c1c8f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13177 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26xcompile: fill in power8 64bit LEPatrick Georgi
Change-Id: Id0316042f665ec9c095887cf6a37a7949ed8e861 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13421 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-01-26xcompile: also look for *-linux compiler tripletPatrick Georgi
Not just *-linux-gnu. Change-Id: Ib817c6d207d3b69ce7595505f2b45f3be35b7d2f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13420 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-01-26xcompile: document all the variables!Patrick Georgi
What's the exact difference between TARCH, TSUPP and TBFDARCHS? Fear no more, it's documented. Change-Id: I18717eb1e20b1c0a82a485d391de2794a77c59ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13419 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-01-26cbfstool: provide buffer_offset()Aaron Durbin
Instead of people open coding the offset field access within a struct buffer provide buffer_offset() so that the implementation can change if needed without high touch in the code base. Change-Id: I751c7145687a8529ab549d87e412b7f2d1fb90ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13468 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-01-26crossgcc: Enable powerpc64-linux target without ppc64-linux headersPatrick Georgi
It may still fail on non-Linux, and the compiler may do fancy things, but it builds. Change-Id: If3456f5fef8d01082a49978dc7cda5450f96f5cc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13416 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-26cbfstool: Fix compile issue for older gcc versionsWerner Zeh
gcc 4.4.7 fails to compile due to the missing initializers for all struct members. Add initializers for all fields. Change-Id: If1ad4fff0f965ccd7e821820c0703853c1e5c590 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13418 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26Braswell: Implement Gpio library functions to read RAMIDSubrata Banik
Added GPIO library code to allow all BSW board specific code to use memory configuration GPIOs in GPIO Input mode and read them to determine which memory type is on the board. Also added other GPIO related APIs to support GPIO access in BSW. Original-Reviewed-on: https://chromium-review.googlesource.com/294893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26nb/intel/pineview: Increase MMCONF decoding to 256 bussesDamien Zammit
Linux kernel detects 256 busses but previously only 64 were allocated. Removes warning in OS. Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13033 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-26Makefile.inc: error if UPDATE_IMAGE is enabled with no coreboot.romMartin Roth
Instead of just failing with the statement: 'mv: cannot stat ‘coreboot.rom’: No such file or directory', fail with an error that helps the user understand the issue. Change-Id: Ie693d45710f599991514e0803a7c444636e473c9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13065 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-26superiotool: fix out-of-box NetBSD Makefile supportAndrey Korolyov
Add NetBSD-specific locations under pkg/ and missing linker flag for libpciutils. Change-Id: I812817a374aaba561b28d8a22f20d238c9dca32b Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12830 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26buildgcc: Help GMP build with 32-bit NetBSDNico Huber
GMP's configure tries to build for 64-bit with a 32-bit userspace on NetBSD too. Help it by forcing ABI=32. Change-Id: I290ea0ef1626fdd88dc3ff74fadb9578ef6a1c9c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13067 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26src/arch: Update license headers missing paragraph 2Martin Roth
For the coreboot license header, we want to use two paragraphs. See the section 'Common License Header' in the coreboot wiki for more details. Change-Id: I4a43f3573364a17b5d7f63b1f83b8ae424981b18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13118 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-26ga-g41m-es2l: Instead of forcing native VGA, make it selectableMartin Roth
This allows the native VGA to be disabled for debug, or if someone wants to use the vbios. Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12848 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-01-26mainboard/intel/d510mo: Licence fixes and azalia verb tableDamien Zammit
Azalia verb table replicated from vendor bios. Licence headers added where appropriate. Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12621 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-26arch/x86: move SetCodeSelector to .text segmentPatrick Georgi
It ended up in .data, and that doesn't seem to be actually necessary. Change-Id: Ib17d6f9870379d1b7ad7bbd3f16a0839b28f72c8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-26util: Look for python2 binary instead of pythonNico Huber
Make the requirement of python2 explicit in scripts that are incompatible with python3. Change-Id: I77f150bdb3aab316fc3c3a21b911db397fa0106f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13286 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-25Revert "util/crossgcc: Build Ada frontend by default"Nico Huber
This reverts commit 89798bcb0cee369cd2aaeda8704d23d347dbe192. Disable building gnat again as it turned out that many distros don't ship with a sufficient recent version of gnat. We'll have to find a reliable way to check for the installed gnat version and query the user or bootstrap gcc in that case. Change-Id: Ife7cf7c9d1567aca898ce308b120a7b9e146e5f5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/13422 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2016-01-25Makefile: Don't copy thin archives aroundNico Huber
We can't just copy archives around as they may be thin archives which contain relative paths. Using ar to create another thin archive should result in the same archive with fixed paths. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Ic5743da2f4b5eb246fafd02181d66c5d40e7f00c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13179 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-25mc_tcu3: Enable auto generated attributes in cbfsWerner Zeh
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position and alignment attributes in cbfs. Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13123 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-01-25util: Use /usr/bin/env as wrapper to look up pythonNico Huber
This way users are not constrained to have it installed as /usr/bin/python. Change-Id: I822b6c402004aad8f2353e71afbd8ee3f9d26d45 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13285 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24nb/amd/mct_ddr3: Properly set MR0 WR valueTimothy Pearson
The existing code accidentally truncated the MSB from the MR0 WR value. While this probably had a minimal effect in reality, it should be configured correctly for maximal system stability. Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13147 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-24nb/amd/mct_ddr3: Add additional verbose-level debug statementsTimothy Pearson
Change-Id: Ie91c990d9c2bcab8292a75d87523a46d5694a34a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13146 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24nb/amd/mct_ddr3: Update drive strength configurationTimothy Pearson
The existing drive strength calibration code did not strictly follow the BKDG-defined setup process. Bring the calibration code in line with the BKDG recommendations. Change-Id: I122eeb93958d88de59d0c3b2979f607afa2c52c3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13145 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devicesTimothy Pearson
When an Extended Temperature Range DIMM is installed on a channel the refresh rate should be increased per the BKDG recommendations to allow correct operation at higher temperature ranges. Set fast refresh on a channel if an ETR DIMM is installed on that channel. Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24cpu/amd/family_10h-family_15h: Move CBMEM storage out of CC6 save regionTimothy Pearson
The existing CBMEM TOM calculations did not account for the CC6 save region (when enabled); this resulted in CBMEM storage being placed on top of the CC6 save region, which resulted in corrupt CBMEM data and a boot hang. Change-Id: I32399da0438d7b16e05192449be625f9aa675b18 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13143 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 socketsTimothy Pearson
The existing code unconditionally cleared the LDT tristate enable bit, which was incorrect for C32 sockets. Update the code to be in line with the BKDG recommendations. Change-Id: I8095931973ea10f1467a6621092e88c6c494565a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13142 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-24northbridge/amd/amdmct: Add termination and timing values for C32 socketsTimothy Pearson
The existing MCT initialization code was largely missing C32 socket- specific configuration data. Add C32 socket-specific timing and ODT values as specified in the BKDG. Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13141 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24northbridge/amd/amdfam10: Update DRAM speed limits for C32 socketsTimothy Pearson
The existing code applied G34-specific speed limits to all socket types. Update G34 and C32 specific speed limits to be in line with BKDG recommendations. Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13140 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24purism/librem13: Fix select of EC_PURISM_LIBREMMartin Roth
This was misspelled as EC_PURISM_LIBEM, causing the EC to not get included in the build. Change-Id: Iffbfb504926e1b90070c2dbf61c0c44ca8fb46bc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13178 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-23Makefile.inc: Comment some 'else' and 'endif' statementsMartin Roth
Help figure out which 'else' or 'endif' is attached to which 'if'. Change-Id: I5ad068eb7c69f2dae57856f0e886f786563f7783 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13064 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-23arch/x86: link bootblock like other stages for C_ENVIRONMENT_BOOTBLOCKAaron Durbin
When C_ENVIRONMENT_BOOTBLOCK is selected link bootblock using the memlayout.ld scripts and infrastructure. This allows bootblock on x86 to utilize all the other coreboot infrastructure without relying romcc. Change-Id: Ie3e077d553360853bf33f30cf8a347ba1df1e389 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13069 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-23lib/memrange: allow stack allocated free listAaron Durbin
Instead of solely relying on malloc for building up an address space for the range_entry objects allow one to supply a list of free entries to memranges_init_empty(). Doing this and only calling malloc() in ramstage allows a memranges oboject to be used in a malloc()-free environment. Change-Id: I96c0f744fc04031a7ec228620a690b20bad36804 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13020 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-23cpu/amd: remove .intel_syntaxPatrick Georgi
Replace with the more familiar AT&T syntax. Tested by sha1sum(1)ing the object files, and checking the objdump that the code in question was actually compiled. Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13133 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-23arch/x86: remove .intel_syntaxPatrick Georgi
Replace with the more familiar AT&T syntax. Tested by sha1sum(1)ing the object files, and checking the objdump that the code in question was actually compiled. Change-Id: Ie85b8ee5dad1794864c18683427e32f055745221 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13132 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 21:48:33 +0000