summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2015-06-24Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUIDLee Leahy
Add new GUID for FSP. BRANCH=none BUG=None TEST=Build and run on strago Change-Id: I539a59b513f67535436f581e0a79ab53f05682ca Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10587 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24pcengines/apu1: Remove unused ide.aslTobias Diedrich
The APU1 board has no IDE port, remove ide.asl. Change-Id: I76b926969748de79ac1281ed50b37e9ade1a6771 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24crossgcc/Makefile: Allow making toolchains using multiple coresMartin Roth
I looked for a way to pass the 'make crossgcc -j8' on to buildgcc, but didn't find a way to get that value directly. MAKEFLAGS turns -j8 into a jobserver variable. Instead, this patch allows the number of CPUs to be set on the command line through a variable instead. Example: 'make crossgcc BUILDJOBS=8' Change-Id: I37608cdb4549226cb7ff8c3ff6d9f4773acf6b0b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24crossgcc/Makefile: clean more, add distclean targetMartin Roth
Update the clean target to remove the intermediate files. These should get removed automatically, but if the build stops in the middle, or if the -t command is used for buildgcc, they can be left in the directory. Add a distclean target that removes the downloaded tarballs as well as everything else. Change-Id: I6ea19e7a499b0c313c1d2eff7e36386204ec834e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10621 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-24autoport: Include 'default_irq_route.asl' into DSDTStefan Reinauer
After commit with Change-Id Ia1839ed3 (sandy/ivy: Include IRQ routes from platform), update autoport to include that file into the DSDT. Change-Id: I14534438d0b433895f384539c8b413eaa53d943a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10612 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-24sandy/ivy: Include IRQ routes from platformKyösti Mälkki
The default route does work for all Chromebooks and is replaced with platform-specific one in follow-up. Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10442 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-23msi/ms7135: move power_on_after_fail out of RTC century byteJonathan A. Kollasch
Change-Id: I0796b6e7adad0151c5aa6271d62a2cf4abeedb1e Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23nvidia/tegra: expose more registersTom Warren
This is in preparation for t210 Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10632 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23tegra: Move pinmux enum constants from tegra/pinmux.h to soc-specific pinmux.hFurquan Shaikh
Since pinmux register format has changed completely for t210, move the constants to pinmux.h in soc-specific folders. BUG=chrome-os-partner:37546 BRANCH=None TEST=Compiles successfully for ryu and foster. Change-Id: Ic1680ac50fc2619657d0c610a5dfc3fb51df7286 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7844c941a6187f884b31a8f7cc52e64268d2c732 Original-Change-Id: Icd3b2a72f3698e0772e888d9209e1fcd5d10e77d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10631 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23southbridge/intel: Create common IFD Kconfig and MakefileMartin Roth
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10613 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23vendorcode: Use cross archiver for libagesa.a on AMD f14Stefan Reinauer
Change-Id: I61a9f65a1ac4c95096d0ff071a95984cf219caa8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10593 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-06-23arm-trusted-firmware: update markerStefan Reinauer
Change-Id: I8dddeead3c23a03803e7d8d5b2bfb8a15c5c2807 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10645 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-23lippert/frontrunner-af: 64bit fixesStefan Reinauer
Change-Id: Ia764798c8b58497e2b453bd000dd06816c28f98f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10600 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23lippert/toucan-af: 64bit fixesStefan Reinauer
Change-Id: I9e7f78587b9d6e87cf77757654da9145d4187625 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10599 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23acpi: bring back ability to link DSDT into ramstagePatrick Georgi
Bring back the ability to link in the DSDT. This is to help Chrome OS to switch over to a new upstream quickly (because some of the custom built mechanisms are a pain with tons of files). This is supposed to be temporary (famous last words), but I'd rather fix the lack of CBFS awareness in CrOS bit for good in the time I usually spend on keeping upstream and CrOS branches close. Change-Id: I7fa5540bbf5c568c4adca56a09c83b6c7e358ad5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-23drop unneeded IRQ_SLOT_COUNTsStefan Reinauer
This is only needed on boards that still provide old style PIRQ tables. Change-Id: Ie299de2937e5b91b7b3e1d1110e40be23c6d9f52 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10508 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23pcengines/apu1: 64bit fixesStefan Reinauer
Change-Id: Iacad070f43534a8b27a2473a6a2854bc2f6e607a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10598 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23gitconfig: set up hooks and target for 3rdparty/blobsStefan Reinauer
Otherwise per default git will attempt to push to the blobs repository directly instead of sending commits to gerrit. Change-Id: I2ba241e0040a9c749c5bedc3d45d00b0b0dbe9e9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10537 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23AMD Kern: Fix path of PspSecureOs BLOBWANG Siyuan
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin. PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7. Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10639 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23Kconfig: Move CBFS_SIZE into Mainboard menuMartin Roth
The CBFS size is really mainboard specific, since it really depends on size of the chip on the mainboard, so it makes sense to have it in the mainboard menu along with the ROM-chip size. - Move the CBFS_SIZE definition up in src/kconfig - Move the Mainboard Menu markers out of src/mainboard/kconfig into src/Kconfig so CBFS_SIZE can live in the mainboard menu. - Add a long list setting default values to do what the chipset directories were previously defaulting the values to. This will be trimmed down in a following patch that creates a common set of IFD routines. (Who knew that kconfig supported line wrapping?) - Update the help text. Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10610 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23SeaBIOS: fix reproducible build by defining our own version stringAlexander Couzens
SeaBIOS uses a version string which is derived from hostname. Defining our own version strings drops this dependency. This only works in versions newer than rel-1.8.0-36-g624e812. Change-Id: Ie800deffd3706d1b2dabf5258e2e48bfcd2929b7 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/10515 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-23SeaBIOS: Clean up build command line.Martin Roth
- Move IASL up with the other tools. - Remove OUT= which is no longer used in the payloads/external/SeaBIOS Makefile. Change-Id: I211ddcf3496b533151936fa5cbfa7a92986ec28f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10606 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23intel/broadwell: Fix refcode handlingPatrick Georgi
Allow adding and executing a refcode binary. Change-Id: I00e91a088a5695b42528e246d0ed642d988603e3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23broadwell: fix typoPatrick Georgi
It's guarded by a non-standard configuration option, so didn't trigger. Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10623 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23veyron_mickey: Apply differences between Brain and Mickeyhuang lin
Mickey: - Does not have power key - Does not have an audio codec(all audio goes thru HDMI) - VCC18_LCD moved to VLDO8 and needs to be turned on (was connected to VSWOUT2 earlier) BUG=none BRANCH=none TEST=Boot from mickey board, and hdmi work normal Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1 Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274876 Reviewed-on: http://review.coreboot.org/10630 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23veyron_danger: Fix #include guardDavid Hendricks
Cosmetic change only. BUG=none BRANCH=none TEST=it compiles Change-Id: Ibe86f624606e365457e03c50c005400d4b335536 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7dfc7002fbf5c100ae65458b33f5aa007dc8d60b Original-Change-Id: Ibc03b028a7918d90cfab9614e800f6df463d86db Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280851 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10628 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-06-23chromeos: vpd: properly null terminate valuesStephen Barber
VPD strings are not null terminated, so we can't use strcpy on them in cros_vpd_gets. BUG=none BRANCH=none TEST=add serial_number followed by cam_calib_data to VPD on smaug; make sure that smaug boots and serial number matches exactly (no garbage) Change-Id: Id72885517b3d0b1934ba329c1ef0d89a67bd2bb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 56bbe6688b11043360a046a250d1ea93db4d9f0e Original-Change-Id: I811dfc2f0830a91410eb69961a6565080ff78267 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280836 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/10627 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23libpayload udc: add interface to add string descriptorsPatrick Georgi
They're ASCII only, with only one language at a time, but they should be good enough to report device names and serial numbers. BUG=none BRANCH=none TEST=with depthcharge CL, check dmesg on the host device Change-Id: If888e05b2f372f7f0f43fadb108ca7ef4ed3b7c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f0bc4242057d3edc4f4796ebeed2d98d89d60a1d Original-Change-Id: Ibe42f1b49f412e5482cebb7ebe20f6034352fd12 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278300 Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10626 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-06-23rockchip/rk3288: add support for hdmi displayYakir Yang
this is an brief hdmi driver which config with simple display parameter, const encoder input & output color format and 8bit color depth, and only 48KHz audio support. what's more to prevent TV have not show an right things before coreboot switch to kernel space, we have to add an terrible 2s delay to driver (2s come from test many times), cause we have to wait TV to respond (we got no flag to check whether it is ready). BUG=chrome-os-partner:40337 TEST=Booted Veyron Jerry and display normal BRANCH=None Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8 Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272565 Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10625 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23submodules: add arm-trusted-firmware third-party repositoryPatrick Georgi
Change-Id: I080c0a5954d3e4b2d6debdf2a77f32df7329841c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10565 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23Revert "arm64: remove assembly code string functions"Furquan Shaikh
This reverts commit 00263d0d8ee23bbe60ea359ea9cb33d551688980 to reintroduce optimized string handling functions. BUG=chrome-os-partner:41185 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on Smaug Change-Id: I47f8d8afa5c9ff3fca67d4d0f393336fef03402b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eeb38afea828a2727d815e4fb5762cfdd09a2b3a Original-Change-Id: Id053cbcea8b5e7ae29bdd6bb8b6f5e5011c42b00 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/275865 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10564 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23libpayload: Parse MTC and fill mtc_start and mtc_sizeFurquan Shaikh
Parse coreboot table and fill in mtc_start and mtc_size values in sysinfo structure. BUG=chrome-os-partner:41125 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: If210ea0a105f6879686e6e930cb29e66bc5e6cd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b70d0d35c85fa1a2317b0239276d5d9e7a550472 Original-Change-Id: I60b6f8ed4c704bd5ad6cce7fce2b9095babe181e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276778 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10563 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23ddr3: add missing newlinePatrick Rudolph
Add missing newline to SPD CRC verification error message. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Id1a0a2329507975c3f66ab884f6e26d99003318e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10636 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23ddr3: Fix SPD CRC calculationPatrick Rudolph
Use the correct SPD size for crc calculation. sizeof(*spd) returns 4 while sizeof(spd_raw_data) returns the expected value of 256. Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10629 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interfaceWANG Siyuan
PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h /// PCIe PSPP Power policy typedef enum { PsppDisabled, ///< PSPP disabled PsppPerformance = 1, ///< Performance PsppBalanceHigh, ///< Balance-High PsppBalanceLow, ///< Balance-Low PsppPowerSaving, ///< Power Saving MaxPspp ///< Max Pspp for boundary check } PCIE_PSPP_POLICY; Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10461 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-23Move same Kconfigs to northbridge/amd/pi/KconfigWANG Siyuan
Bettong, Lamar and Olivehill Plus have many same Kconfigs. Move them to northbridge/amd/pi/Kconfig. Change-Id: I758d5a09f27eee7a7bd60268a2aaed6f16fd0294 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10421 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23AMD Bettong: Add a new AMD FP4 socket mainboardWANG Siyuan
Add a new mainboard based on AMD's Family 15h Model 60h processor. TEST: Bettong can boot Ubuntu 14.10, Windows 7 and Windows 8. Change-Id: Id807369ff0f04ba303383c65ddd1bd512f184e6a Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10420 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22AMD Merlin Falcon: Add northbridge files for new AMD processorWANG Siyuan
Tested on Bettong. Windows 7, Windows 8.1 and Ubuntu 14.04 can boot. Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10419 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22AMD OemS3Save: refactor for Merlin FalconWANG Siyuan
Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with S3_DATA_BLOCK. Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10526 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22buildgcc: Add list of valid platform to the help text.Martin Roth
Change-Id: Ic48a08d1067c850555cf04ad29e65e9bdb7c4243 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22Remove incorrect Kconfig expressionsMartin Roth
The symbols used in these expressions were not correct and would never evaluate as true. Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10437 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-22lenovo/x60: Enable VESA framebuffer mode (native graphics)Francis Rowe
At present, no option exists for "Keep VESA framebuffer", which means that text-mode will be used. Add the appropriate Kconfig option. Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/10553 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-22lenovo/x60: Enable brightness controls (native graphics)Francis Rowe
On i945 legacy brightness control is enabled by a single bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one reverses polarity). Set the bit to enable brightness controls. Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/7048 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-22superio: use common x86 code on x86-64Stefan Reinauer
Change-Id: I2ddb5a8b183b21cbd3c3b22c537b815e86bd4738 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10592 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22device: DDR3 generic code 64bit fixStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I5ff309948c36289eedeb8a18030cdd2b4c337690 Reviewed-on: http://review.coreboot.org/10595 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22oprom: Fix for 64bitStefan Reinauer
Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10591 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22device: Use x86 specific code on x86-64Stefan Reinauer
Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10584 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22x86: make PCI MMIO CFG functions 64bit proofStefan Reinauer
Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10577 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-21Remove obsolete EARLY_CONSOLE usageMartin Roth
The EARLY_CONSOLE Kconfig symbol was removed in commit 48713a1b - console: Drop EARLY_CONSOLE option The arm64 and mips directories don't even have early_console.c to include. Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10615 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21superio/fintek/Kconfig: add newline at end of file.Martin Roth
Kconfig sometimes fails to parse the last line of a file if there's no newline at the end. Add one to be safe. Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10614 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21Reorder arch & vendorcode in KconfigMartin Roth
Because Kconfig uses the first valid default that it comes across, the 'source' commands to load sub-Kconfigs should be ordered from the most specific (mainboards) to less specific (chipsets) to least specific (architectures). This allows the mainboards to override chipsets and architecture Kconfig files. Because the architecture files were getting loaded ahead of the chipset and cpu Kconfigs, the preferred defaults values for things such as NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set. Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10609 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-06-21Remove old HAVE_UART_MEMORY_MAPPED select statementsMartin Roth
The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these don't actually select anything. Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10608 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-20buildgcc: Update clang search stringMarc Jones
buildgcc fails if g++ or clang isn't found on the host. This was failing on OSX due to the string used to check for clang doesn't match "Apple LLVM". Add an additional search string for clang "LLVM". Change-Id: I05e36cfc690061b3233376d57f44f197cab933ea Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10569 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-20cpu: x86 port to 64bitStefan Reinauer
Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10580 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20x86: Make ACPI 64bit cleanStefan Reinauer
Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10578 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20x86: Make reading / writing of CRx registers 64bit proofStefan Reinauer
Change-Id: I782007fe9754ec3ae0b5dc31e7865f7e46cfbc74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20x86: make memcpy 64bit safeStefan Reinauer
This does not optimize memcpy for 64bit, it merely makes it compile. Change-Id: I69ad6bd0c3d5f617d9222643abf7a2ba7c2a0359 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10575 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20xcompile: x86-64-elf wants -Wa,--divide, tooStefan Reinauer
Change-Id: I03eb1c0f1e0b0c6213ec6b26cf41dadd4df9b910 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10574 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-203rdparty/blobs: Move submodule marker forwardMarc Jones
Pick up the latest from blobs. 34b0926 AMD Merlin Falcon: remove build warnings e581a5c AMD pi: replace LocateModule with agesawrapper_locate_module c5ddfb6 AMD PI: remove unuseful code Change-Id: I2b9d2b61cb00aa651b90dc76368d215077e27cad Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10603 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-17buildgcc: Don't build iasl with gccStefan Reinauer
There's a separate target -P iasl for that now. Change-Id: I95c0fe8fc266859d8a31b7bea890775dc9f19694 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10567 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-17buildgcc: enable biarch support for x86_64-elfStefan Reinauer
With this change, the x86_64-elf-gcc can compile i386-elf binaries by specifying -m32. The patch against GCC is needed to enable building the 32bit libraries when building x86_64-elf-gcc Change-Id: Ic86a009eccfdf3e33a398bcdcc13b15c8dfc0d31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10497 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-17winent/mb6047: initialize hardware monitor CPUTIN configurationJonathan A. Kollasch
Change-Id: Ic36727104e5c2f620f9b2b7b340de8548b467397 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17mainboard/bap: Add support for BAP ODE E20XXFabian Kunkel
Adding new board based on AMD Kabini. Most of the code is copied from gizmosphere/gizmo2 Board is developed by BAP - Bruhnspace Advanced Projects: http://www.unibap.com/ (Site is under construction) Special on this board is: -Soldered down memory -SuperIO Fintek F81866D Known bugs: -S3 doesnt work -Serial ports only works for the first boot. Needs power cut. Tested with: -SeaBios as Payload -Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1 -Windows 8 64Bit Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10288 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17pcengines/apu1: Add ACPI led, button and GPIO devices.Tobias Diedrich
Provide ACPI devices with devicetree-compatible annotations for the three leds and the button of the APU1, as well as the GPIO driver. This will cause the Linux kernel to automatically load the following modules: leds_gpio (CONFIG_LEDS_GPIO) gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED) gpio_sb8xx (CONFIG_GPIO_SB8XX) See http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf and https://lwn.net/Articles/612062/ for some more information on how the PRP0001 HID works. To make this usable a Linux GPIO driver for the AMD chipset is also required, which I am currently working on, but have not submitted upstream yet. Leds have been named after the convention in Documentation/leds/leds-class.txt: LED Device Naming ================= Is currently of the form: "devicename:colour:function" For comparison, on an OpenWRT device: GPIOs 0-21, ath79: gpio-1 (tp-link:green:usb ) out hi gpio-2 (tp-link:green:system) out lo gpio-3 (reset ) in hi gpio-5 (tp-link:green:qss ) out lo gpio-7 (qss ) in hi gpio-9 (tp-link:green:wlan ) out lo gpio-18 (rtl8366rb ) in hi gpio-19 (rtl8366rb ) in hi On the apu1: GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver: gpio-475 (switch1 ) in hi gpio-477 (apu1:green:led1 ) out hi gpio-478 (apu1:green:led2 ) out hi gpio-479 (apu1:green:led3 ) out hi Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10540 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17coreboot_tables: Add CBMEM ID and tag for MTCFurquan Shaikh
BUG=chrome-os-partner:41125 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276779 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10562 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17x86 cpu: Allow some cpuid functions during romstageLee Leahy
Allow calls to cpu_phys_address_size and its support functions during romstage. This enables the proper display of MTRRs during romstage without duplicating this code. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0 Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277392 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10561 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-17stddef: Add macro for member_sizeFurquan Shaikh
Add macro to calculate size of a structure member BUG=chrome-os-partner:41125 BRANCH=None TEST=Compiles successfully Change-Id: I71bcefe1c3b32ad559d7764e77369c67d09422a0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b425a310c14eabad79caf97649db6469380bd602 Original-Change-Id: I377fff062729aa664f7db469b86764b0ad941c38 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276809 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10560 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-17PCIe : Adding some error/not-null condition checkingPratik Prajapati
This patch checks for following conditions (1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found then don't enable LTR. (2) 2.1) set_L1_ss_latency is member if ops_pci, which could be NULL. so confirm ops_pci is not NULL before calling its member function. 2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency. BUG=none BRANCH=none TEST=build and boot coreboot with L1 substate enabled on sklrvp3. Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181 Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17arm64: Move enabling floating point ahead of dev initJimmy Zhang
This CL is in preparing for tegra mtc that is invoked by dev init. mtc currently requires floating point instructions support. BUG=chrome-os-partner:40999 BRANCH=none TEST=Build and boot smaug Change-Id: I470dfcd86026812d617f9ff4f4fcdce601195857 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e3f7336fc7cedf96dab4eff204616519856f831 Original-Change-Id: I14c0003ce76ddf4b4ebb0cf171ea3c62cab55ef9 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/275112 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10558 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17buildgcc: Check for dependencies after printing bannerStefan Reinauer
For consistency in user output, move the check for all required utilities after printing the banner and parsing options. Change-Id: I5bf31368885c73e35f18b02d53d099f3f3871acc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10566 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-17buildgcc: Clarify required user actionStefan Reinauer
When required tools are missing, try to give the user more detailed information on how to solve the problem. Change-Id: Ifa21c1af38a036a7d4f5a786041a87a7d45f4ec5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16kconfig: allow specifying the target for savedefconfigPatrick Georgi
Change-Id: Iee5ab0d3bdc8b754669356f2046d290d9ca555c2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10511 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-16xcompile: Don't print error messagesStefan Reinauer
Don't print error messages if an unpatched clang is detected. Change-Id: If77722a40a59e99f01d121a0c43999f05f3c4421 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16buildgcc: Define $CMAKE only if clang package is builtDavid Hendricks
This moves the CMAKE definition down into the case statement for $PACKAGE so that it is only required when the user wants to build clang. With this approach, "./buildgcc -P clang" will error out with the "ERROR: Missing tool:" message if cmake is not installed. Change-Id: I1e5c1bd67ade8f93ba0390df7f234deb47b9b18a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/10556 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-16xcompile: add support for x86-64Stefan Reinauer
Add support for detecting an x86-64 cross compiler in xcompile. Change-Id: Icd2c9af7903956216db1fd54902eab6da0fe3e21 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16x86: Make stdint.h x64 proofStefan Reinauer
Change-Id: Ibcfdc08c9aac02fe263afd629fc262f71da80e9a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8695 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16cpu: add x64 class for cpu_microcodeStefan Reinauer
Change-Id: I1535fea97c676ed6465d777f444b0a1a0e023474 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8694 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16x86: Make x86 architecture makefiles x64 awareStefan Reinauer
Almost all of the code between x86 and x64 can be shared, so select it for either architecture. Change-Id: I681149ed7698c08b702bb19f074f369699cef1bf Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8693 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16Add x64 support to src/arch/x86/KconfigStefan Reinauer
Change-Id: I81f6d8a21ea0d8218f5a4aab2feb39be32f88e01 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8692 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16toolchain.inc: Add x86-64 supportStefan Reinauer
For now, share code with x86, and use the "large" code model. Also align the architecture specific CFLAGS in toolchain.inc for cosmetics. Change-Id: Ie84893d3460115802fbd70c28b10e709029c6b4e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-153rdparty/blobs: Move marker forwardStefan Reinauer
Change-Id: I2a9304a6b573a10e896f9ff77bfb09f20b21eb50 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10541 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-15ck804 ACPI: set duty width in FADT correctlyJonathan A. Kollasch
Change-Id: I12ef633009b5c63b08fbeb76d58cb08c776485ac Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10546 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-14pcengines/apu1: Remove unused smbus.aslTobias Diedrich
The smbus.asl operation regions prevent the Linux i2c driver (i2c_piix4) for this chipset from claiming the ioport ranges and thus it fails to load. The methods defined in smbus.asl are not used in the DSDT and also don't exist in the DSDT of the vendor firmware. In particular due to the following check in i2c-piix4.c will fail unless acpi_enforce_resources=no is explicitly set on the Linux kernel parameters: if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) return -ENODEV; Depending on kernel options the only error message printed is ACPI Warning: SystemIO range 0x0000000000000B00-0x0000000000000B07 conflicts with OpRegion 0x0000000000000B00-0x0000000000000B0B (\SMB0) (20150410/utaddress-254) ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver However since it does not implement a standard interface there is no native ACPI driver for smbus.asl. Change-Id: Id8401e8b36f0e2412d490a92c20540a04d853125 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10539 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14winent/mb6047: Remove redundant P-State generationJonathan A. Kollasch
Recently ck804/lpc.c started generating pstates for us. Change-Id: Ie47fff0516e0e838fdcd5084074ce2cabfe7e290 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8318 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14mainboard/lenovo/t400: Fix HDA verbs to match hardware layoutMichał Masłowski
The same values are used on my Lenovo R400 as reported by Francis Rowe from his T400 and T500. TEST: Read /proc/asound/card0/codec#0, see that the jack locations correspond to the board layout, e.g. headphone and microphone connectors are on front of the laptop, not right. Read /sys/class/sound/hwC0D0/init_pin_configs, see that it has the same content as with factory firmware. Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Reviewed-on: http://review.coreboot.org/10431 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-14asrock/e350m1: Remove unused file `acpi/smbus.asl`Paul Menzel
Commit 8d80a3fb (ASRock DSDT: Split the ASRock DSDT) creates the file `acpi/smbus.asl` in the board directory, but includes the identical southbridge file in `dsdt.asl`. So, the file is actually unused. Therefore remove it. Change-Id: I26c5a2eaf3822d37da2402da65b278a3ee6d42f0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10544 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14amd/cimx/sb800/acpi/smbus.asl: Align commentsPaul Menzel
Change-Id: I1ea1b1efedfea2926a24f06beeb8d7d0464057e5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-13Move remap_bsp_lapic to AMD specific codeStefan Reinauer
It's not used outside of very old AMD CPUs. Change-Id: Ide51ef1a526df50d88bf229432d7d36bc777f9eb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10538 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13google/auron: Add mainboardMarc Jones
Add the Google Auron Broadwell Reference Mainboard. It is based on the Google Peppy mainboard. It was merged from the following chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10500 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13southbridge/amd/pi: Add support for new AMD southbridge KernWANG Siyuan
Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13AMD Merlin Falcon: Add CPU subdirectory files for new AMD processorWANG Siyuan
This adds the AMD Family 15h model 60h CPU. S3 suspend/resume currently is not supported. Tested on the amd/bettong platform. Change-Id: I5dea55a5664d29c07a54937ed1e5c2f84715d8ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10417 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13vendorcode/amd: unify amdlib for binary piStefan Reinauer
Instead of having three copies of amdlib, the glue code for Agesa, let's share the code between all implementations (and come up with a versioned API if needed at some point in the future) Change-Id: I38edffd1bbb04785765d20ca30908a1101c0dda0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10507 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13AMD Merlin Falcon: Add binary PI vendorcode filesWANG Siyuan
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10416 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12bimgtool: initialize data headerPatrick Georgi
Otherwise dummy contains uninitialized data, which leads to non-reproducible builds (and a leak of 4 bytes of stack data). Change-Id: Iaaf846580ec436fdd4f0800c7576b544f50d6ae0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12superio/fintek: Add support for Fintek F81866AD-IFabian Kunkel
This patch adds support for the Fintek F81866AD-I SuperIO, which is very similar to the fintek/f81865f. This code adds some fan control support, inspired by fintek/f71869ad. Furthermore its possible to change the temp sensor type (thermistor or diode). Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10287 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-12pistachio: add DDR3 initialization codeIonela Voinescu
Initialization for the Winbond W631GG6KB part using Synopsys DDR uMCTL and DDR Phy. This code adds a separate function for DDR3 initialization and moves all the necessary defines in a separate header file. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. It was tested on Pistachio bring up board where DDR was initialized properly and ramstage executed correctly Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12pistachio: Use passive windowing as DQS gating schemeIonela Voinescu
Switching from active windowing DQS gating scheme to passive windowing mode resolves boot stability issues on chips found to have memory corruption issues during boot or memory tests. It was tested on Pistachio bring up board where DDR is initialized properly and ramstage executed correctly; We have cycled units over 12,000 times with no boot errors. This option was chosen over the alternative of using passive windowing mode for DQS training and after switching back to active mode, as this option was recommended by Synopsys. Using the alternative would give different timing values during training that were not longer accurate during normal activity. Change-Id: Ie604eddc0a9a982b2f89198f44deb88a01b7b322 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12google/jecht: fix MAC address programming when VPD not presentMatt DeVillier
Fix by checking the actual function return value (the search address pointer), rather than the search length value (which isn't guaranteed to be sane or useful). Change-Id: I226c635ddbbc916b02494fcd97df27d141cc2c7f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10516 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 15:02:48 +0000