Age | Commit message (Collapse) | Author |
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registers
- Add several more test cases.
- Bump the version number to .32
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- Fix a last couple of structure related bugs
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I set USE_FALLBACK_IMAGE to 1 in the top-level Config, but when it is tested
in arima/hdama/Config.lb, it is acting as though it is zero.
Also added a print command so it is easier to trace 'if' behavior.
Usage:
print "string"
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more fixes to various Config.lb
one last problem and we're there
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we need to get rid of yappsrt.pyc
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Config.lb:0: Error: Option USE_FALLBACK_IMAGE Undefined.
might happen (i.e. missing 'use' command)
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- Register allocator bug fixes.
* coalesce_live_ranges now also updates the interference graph of live instructions
* resolve_tangle now avoids copies to phi
* correct_tangles is now called in a loop so that all tangles get fixed
- Bug the version of romcc to 0.30
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- Add an additional consistency check to romcc and fix the more obvious problems it has uncovered
With this update there are no known silent failures in romcc.
- Update the memory initialization code to setup all 3 of the memory sizing registers properly
- In auto.c test our dynamic maximum amount of ram.
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- Minor romcc fixes
- In smbus_wail_until_done a romcc glitch with || in romcc where it likes
to run out of registers. Use | to be explicit that I don't need the short
circuiting behavior.
- Remove unused #defines from coherent_ht.c
- Update the test in auto.c to 512M
- Add definition of log2 to romcc_io.h
- Implement SPD memory sizing in raminit.c
- Reduce the number of memory devices back 2 to for the SOLO board.
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with older ones...
- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
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so the worst case runtime of romcc is much more predictable
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code that runs without ram and code that runs with ram.
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The goal is to have the same interface with or without romcc.
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- Implementation of fallback/normal support for the amd solo board
- Minor bugfix in romcc
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pci definitions
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fewer registers, and is easier to hardcode.
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__builtin_wrmsr in romcc
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I need a very early Hypertransport setup to get anything more going.
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