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The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the kunimitsu
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296302
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11554
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the glados
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11553
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable only the USB ports that are connected on-board or to an
external port, all others will be disabled.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested
Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f
Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296036
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11549
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable only the USB ports that are connected on-board or to an
external port, all others will be disabled.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=build and boot on glados, ensure expected USB ports still work
Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163
Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296035
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11548
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The USB port enable/disable settings were never getting applied to
the UPD configuration and so were not getting used by FSP.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=build and boot on glados
Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296034
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove dead code not called by any part of coreboot.
BRANCH=none
BUG=None
TEST=Build and run on skylake
Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef
Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294953
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11544
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There's no need to add any typedefs nor guard code with
ENV_ROMSTAGE. The linker will garbage collect unused functions.
Additionally there were a few errors in the code including
the operation mask wasn't wide enough to clear out old operations
as well as component size decoding was incorrect.
The big difference in the code flow is that the operation
setup is now in one place. The stopwatch API is also used in
order to not open code time calculations.
BUG=chrome-os-partner:42115
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted. Suspended and resumed. event log is populated
for all.
Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489
Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295980
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11543
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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I missed this in code review. This should be under the soc
directory.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built glados.
Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c
Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295239
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11542
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The spi_init() routine needs to be called in all boot paths to allow
writes to the SPI part. The reason is that the write enable is done
in spi_init(). Moreover, this is also required for a writing a firmware
update after a resume.
BUG=chrome-os-partner:42115
BRANCH=None
TEST=Built and booted glados. Suspended and resumed. Eventlogs show
up in resume path.
Change-Id: I187baa940bb45ef90ab82e67c02f13d8855d364e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8813ab227395cfcba46ad4109730a1eb5897e538
Original-Change-Id: Ida726fc29e6d49cd9af02c4e57125e09f2599c36
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295238
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11541
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The timer_monotonic_get() function wasn't being compiled for
romstage. To simplify the implementation don't keep track of
partial microsecond ticks and just return the MSR value divided
by 24 (24MHz clock).
BUG=chrome-os-partner:42115
BRANCH=None
TEST=Build and booted glados. Used monotonic timers in romstage
in subsequent patches.
Change-Id: I8294c74abe09947fb4438bf5c1d0fc5265491694
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6d60ef204fc92c26748ab57d4ff37830cd8dc664
Original-Change-Id: Ibdb6b9e20b9f2d48ff0f8a8c782f5c1f7ddde4f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295237
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11540
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Switch the GPIO controller to use the PCR functions that are
defined in pcr.asl.
Have the default memory regions declare a size of zero and
be fixed up in the _CRS in order to fix compile issues on
some versions of iasl.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ic82fcb00285aeb2515e24001ef69a882c3df1417
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: be24d9ccd9db62ca694f3a67436af25a73f59c5a
Original-Change-Id: I13acd891427f467e289d5671add5617befef4380
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295951
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11538
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Remove the old workarounds for XHCI from broadwell
- Add PMC device to expose bits needed for XHCI workarounds
- Implement the new workarounds for XHCI, the first will set
a bit in the XHCI MMIO and the second will send a message
to the PMC if a bit is set indicating the workaround is available.
- Clean up the HS/SS port defines and remove unnecessary
methods to determine the port count since we only support SPT-LP.
BUG=chrome-os-partner:44622,chrome-os-partner:44518
BRANCH=none
TEST=build and boot on glados, verify that D0 and D3 can be
made to work (by disabling unused USB and the misbehaving camera)
Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88
Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11537
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Skylake moves back to having SerialIO devices be enumerated
as PCI devices instead of putting them all in ACPI mode.
There is currently no code that populates the device_nvs
fields so all the ACPI code to support that is dead.
Additionally because it contains _PS0/_PS3 methods that
causes the kernel to not use the standard PCIe PME handlers
and results in confusing messages at boot about not being
able to transition to a non-D0 state from D3.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados and ensure I2C devices work
Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b
Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295909
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11536
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the storage controller devices out of serialio.asl
and into a new scs.asl file and implement the power
gating workarounds for D0 and D3 transitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529
Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295908
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11535
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the itss.asl code that was exporting PIRQ routing
control registers into irqlinks.asl and use the PCR access
methods to find the appropriate address. At the same time
clean up the code in irqlinks.asl to follow formatting rules.
Also now that the GPIO code in itss.asl is unused the file
can be removed.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I1af7d730542fd0e79b9f3db9f0796e7c701c59e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39a96063d01d00ab768db1c723f78b5af9ed6513
Original-Change-Id: Iafa03c276cb276ec8c00c24ed2dba48d0dc9612b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295907
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11534
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the now unused RCBA base and size from iomap.h
and fix a trivial typo that doesn't seem to get used
anywhere.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emege-glados coreboot
Change-Id: If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee7b1a8a75a9e9dc191c16ddc32b6a38acec398c
Original-Change-Id: I0c49803d47105c3c55121caedaffaa249c4f0189
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295906
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11533
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the PCR Port ID for the storage controllers and
reformat to put the PCR PIDs in increasing order.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11532
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There are a few places in ACPI that touch PCR registers,
either to read a value or to set some magic bits.
Expose some functions for this that will keep all the PCR
access in one location instead of spread throughout the code.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1
Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11531
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Clean up the code in pch.asl:
- move all the C header includes into here instead of duplicated
in various ASL files included from here
- move the trap field definition into platform.asl with the method
- alphebetize the includes
- move gpio.asl include into pch.asl
- remove duplicate irqlinks.asl include from lpc.asl
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11530
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work
Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable 1866 timings in the 4GB Hynix SPD.
BUG=chrome-os-partner:44394
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423
Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295174
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11528
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The platform ID is an 8 character ASCII string, so our config should
take it in as a string, rather than a set of two 32-bit integers.
Change-Id: I76da85fab59fe4891fbc3b5edf430f2791b70ffb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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Now that cbfstool supports file alignment, we can use the conveniently
available <filename>-align handler, and remove the need to have a
separate rule in src/Makefile.inc just for adding the microcode.
We can also get rid of the layering violation of having the
CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
Note that we still have a layering violation by the use of the
CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
for the time being.
Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11526
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We don't build-test with native VGA init, so if the code is broken by
a commit, we won't see it when it's guarded by #ifdefs. This has
already happened in the past. Instead of gurading entire files, use
the IS_ENABLED() macro, and return early. This at least enables us to
build-test the code to some extent, while linker garbage collection
will removed unused parts.
BONUS: Indenting some blocks also makes the difference between
framebuffer init and textmode init clearer.
Change-Id: I334cdee214872f967ae090170d61a0e4951c6b35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11587
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Native VGA init no longer compiles from commit:
* 7dbf9c6 edid: Use edid_mode struct to reduce redundancy
Tested on a single X60 machine.
This patch basically copies 11491 which does
the same for north/intel/sandybridge.
Change-Id: I0663f3b423624c67c2388a9cc44ec41f370f4a17
Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Reviewed-on: http://review.coreboot.org/11585
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Native VGA init no longer compiles from commit:
* 7dbf9c6 edid: Use edid_mode struct to reduce redundancy
Change-Id: I51a4f4874ce77178cab96651eb7caf2edd862aa2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11491
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.
Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.
Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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coreboot has no CREDITS file.
Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Whenever we want to add a file to CBFS with a specific alignment, we
have to do two cbfstool invocations: one to find a place for the file,
and another to actually add the file to CBFS. Get rid of this nonsense
and allow this to be done in one step.
Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Several USB timing fixes for USB controllers on real hardware
Initial support for USB3 hubs
Initial support for SD cards (on QEMU only)
Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only)
SeaVGABIOS improvements:
Added cursor emulation to coreboot native init vgabios (cbvga)
Added support for read character calls when in graphics mode
Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/11479
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Commit "7dbf9c6 edid: Use edid_mode struct to reduce redundancy" moved
some fields from "struct edid" to "struct edid_mode". Adapt the bochs
and cirrus drivers to that change.
Change-Id: I9ec82a403d0264955d4b72496219036c7775c758
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/11502
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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In order to prepare for more unification of the linker
scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
ecpu_drivers with an underscore.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built different boards includes ones w/ and w/o relocatable
ramstage.
Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11506
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The #include path during compilation already has '-I src'.
Don't encode the src part of a path.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built amd/thatcher while compiling romstage.c with C compiler..
Change-Id: If4fb1064a246b4fc11a958b07a0b76d9f9673898
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11512
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Current code written in C is calling a function implemented
in assembly. However, the symbol's visibility is not set
for such usage. Of course this works because MAINBOARDDIR/romstage.c
is being processed into an assembly file currently.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built digitallogic/msm800sev while not changing romstage.c
into an assembly file.
Change-Id: I84c3af0026f3f98bc64af007aa7cc196429f4e5f
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11511
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
the current state of the header meant bad build errors in non-ramstage.
Therefore, people had to #ifdef in the source. Remove that requirement.
Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11492
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add support to the Intel common firmware Kconfig and Makefile.inc to
allow the Gigabit Ethernet (GBE) blob to be added to the final
binary.
Change-Id: Id5fab3061874dad759750b67d3339eb8c99a62d6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10875
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.
Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Some of the Chrome OS boards were directly calling vboot
called in some form after contorting around #ifdef preprocessor
macros. The reasoning is that Chrome OS doesn't always do display
initialization during startup. It's runtime dependent. While
this is a requirement that doesn't mean vboot functions should be
sprinkled around in the mainboard and chipset code. Instead provide
one function, display_init_required(), that provides the policy
for determining display initialization action. For Chrome OS
devices this function honors vboot_skip_display_init() and all
other configurations default to initializing display.
Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11490
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Adjust gpio settings due to hardware change.
Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11489
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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1. Update hwinfo.hex (add dummy data and update checksums).
2. Delete version.hex from mainboard directory. It can be added
in site-local if needed.
Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Drop old incomplete, broken and hardcoded sata.asl properties.
The new sata acpi generator only needs a proper defined device.
Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9710
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Drop old incomplete, broken and hardcoded sata.asl properties.
The new sata acpi generator only needs a proper defined device.
Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9709
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Since more boards are starting to use the EC provided keyboard
backlight interface move the code to a common place and allow
it to get included in mainboards.
Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/11478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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According to https://gcc.gnu.org/gcc-4.6/changes.html it's only in gcc 4.6,
not 4.5, which I mistakenly believed.
Change-Id: I8212e7921bd9d1436a0ba491cbe6c4d473228956
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11476
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Tested-by: build bot (Jenkins)
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This isn't required for correct execution, and doesn't need to be tested
on every single compiler out there.
Since GCC < 4.5 has no idea about _Static_assert, hide it there. Our
build tests will make sure that the test is run before changes are
submitted to master.
Change-Id: I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11475
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
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Change-Id: I5142b03d3c3e028eeb179f225848f762186f94a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11363
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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... and document the interface.
Change-Id: I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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cbfstool extract also needs it.
Change-Id: I8302bb18c5f797eb0a43ec4e4269790f3d49a896
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11361
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Display compressed and decompressed sizes, as well as the compression
algorithm used, when a compressed file is encountered.
Change-Id: I13c2332702c4a5bec379e1ebda72753e06f8e135
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11359
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Currently, compression is only allowed at subheader level (e.g. cbfs_stage,
cbfs_payload_segment). This change adds compression field to each file's
header so that any cbfs file can be compressed.
With the necessary additions in coreboot and libpayload, the following sample
code can load a compressed file:
const char *name = "foo.bmp";
struct cbfs_file *file = cbfs_get_file(media, name);
void *dst = malloc(ntohl(file->uncompressed_size));
dst = cbfs_get_file_content(media, name, type, file, dst);
cbfs_stage and cbfs_payload_segment continue to support compression at
subheader level because stages and payloads have to be decompressed to the load
address, which is stored in the subheader. For these, file level compression
should be turned off.
Change-Id: I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10935
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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cbfs_file_first_attr(struct cbfs_file *) and
cbfs_file_next_attr(struct cbfs_file *, struct cbfs_file_attribute *)
help navigate through extended attributes.
cbfs_add_file_attr(header, tag, size) adds a new file attribute to
header.
Change-Id: I325965286c44f31abd95df684d340cebb0e68b75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10934
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In the gm45 code, IOMMU is always selected to be enabled. Instead
this patch removes the Kconfig symbol and its dependencies. This leads
to the same effect without the need for the symbol.
The symbol is still used in the K8 code as it's not selected, simply
defaulted to being enabled, and one of the mainboards disables it.
Change-Id: Ibc5939cd1e297d497bf71b1787d852f7cc09a551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11345
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Iac4f275c14646b40ffe04fc5a6f6e1402cebfddf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11464
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This depends on RELOCATABLE_RAMSTAGE, and shouldn't be selected if
its dependency is not activated.
Change-Id: I8e7efc3f87e105715fe3377ed306891f0d209979
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11473
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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In order to make analysis easier provide an option (-T) to
print timestamps in a parseable format:
ID<tab>raw timestamp<tab>time from previous entry<tab>description
BUG=chrome-os-partner:44669
BRANCH=firmware-strago-7287.B
TEST=Built and tested on glados. Used the following script:
cbmem -T | awk 'BEGIN { FS="\t" } { tot += $3 } END { print tot }'
Change-Id: I06dc0487d1462b6a78924130f0ad74b0d787d3f8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add the timestamp tick frequency within the timestamp table so
the cbmem utility doesn't try to figure it out on its own. Those
paths still exist for x86 systems which don't provide tsc_freq_mhz().
All other non-x86 systems use the monotonic timer which has a 1us
granularity or 1MHz.
One of the main reasons is that Linux is reporting
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the true
turbo frequency on turbo enables machines. This change also fixes
the p-state values honored in cpufreq for turbo machines in that
turbo p-pstates were reported as 100MHz greater than nominal.
BUG=chrome-os-partner:44669
BRANCH=firmware-strago-7287.B
TEST=Built and booted on glados. Confirmed table frequency honored.
Change-Id: I763fe2d9a7b01d0ef5556e5abff36032062f5801
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As pistachio already provides timer_monotonic_get() let the
generic timestamp_get() use that instead of having around
another implementation of timestamp_get().
BUG=chrome-os-partner:44669
BRANCH=None
TEST=None
Change-Id: Iaa6db49f0055b7c2ef116f41453f838093e516e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11469
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The src/lib/timestamp.c already has an implementation using
timer_monotonic_get() for timestamp_get(). Use that instead
of duplicating the logic.
BUG=chrome-os-partner:44669
BRANCH=None
TEST=None
Change-Id: If17be86143f217445bd64d67ceee4355fa482d39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11375
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Without this change, if one USB3 device is attached when
the board is power up, the USB3 port can not be used.
Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11377
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Idf28faa26a7ea5e94495af5ff027309df444766e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11376
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ie3a44c6db9c9c186c52b4743334266ec5411ba8a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9f59a00e735f39df813b2216290da62eea3c595d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11372
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This option was removed in the following commit:
* 80f5d5b fsp1_1: remove duplicate mrc caching mechanism
Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The #error messages only say that "CONFIG_* must be defined", which
conveys no more information that the compiler or assembler failing
when it encounters an undefined CONFIG_* symbol.
Change-Id: I6058474d4cd454cfc20290650425d379f388abd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11461
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Previously, X4X was incorrectly named because it provides
support for SKUs within XX4X range. This is renamed.
This patch provides support for all X4X SKUs according to
datasheet Intel 4 Series Chipset Family Specification Update,
namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions).
Tested on Gigabyte GA-G41M-ES2L
Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/11245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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After much consideration, and many years of an EXPERT mode sitting
almost completely unused, we've seen that it doesn't work for us.
There is no standard on what constitutes EXPERT, and most of
coreboot's options Kconfig are expert-level.
We even joked that not selecting "EXPERT" should prevent coreboot
from compiling:
@echo $(shell whoami) is not permitted to compile coreboot
Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11365
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether
or not the payload will actually be SeaBIOS:
1. PAYLOAD_SEABIOS, but payload changed with cbfstool
2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS
et. cetera.
Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11293
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
|
|
Reference CL:294712
BUG=chrome-os-partner:43072,chrome-os-partner:43707
BRANCH=none
TEST=build coreboot and boot on Kunimitsu Fab3.1
Change-Id: Ic89f3bcad1f4b4b1dfe39025a51bfcb97ad87158
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 1c73c1a345bb3ac397f2da2d14b25d688cc00a92
Original-Change-Id: If38fb37c092cbf4aaa339da6a777f2ba80e8cd2a
Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295514
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11437
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
switch and SPI write protect for fill_lb_gpios() to coreboot table.
BUG=chrome-os-partner:43707
BRANCH=none
TEST=build and boot on kunimits
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680
Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5
Original-Reviewed-on: https://chromium-review.googlesource.com/295580
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
mainboard_ec_init() wasn't getting run due to an invalid
Kconfig symbol. This check isn't required as the Kconfig
option for the EC is forced to be enabled, and the function
should always be run.
BRANCH=none
BUG=none
TEST=Rebuilt glados mainboard.
Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7
Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295143
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11435
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
recovery mode.
BUG=chrome-os-partner:43683
BRANCH=none
TEST=build and boot on kunimits and successfully enter recovery mode
by pressing “Esc + refresh + Power” keys.
Change-Id: Id25b9f2195f1caaa8b46967b4b5d4abdab48d6cc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 96b1c295448b412a5662afc729fdd37294d3cb61
Original-Change-Id: I9f650b28b0a86b631ffdfe6de5d58d18e48a0a22
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295138
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11434
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=chrome-os-partner:44470
BRANCH=None
TEST=Builds and Boots on FAB3 (Kunimitsu)
Change-Id: I479fe60dcbdd51f4fa5bca857b4a166f958a54d5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: e88efdd8766e2846a650eb75709b29035c406bf8
Original-Change-Id: I9fe5697d31e188fca48b14fb76e71631f2974c2d
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295218
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11433
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Ported below patch from glados to kunimitsu:
glados: Abstract board GPIO configuration in gpio.h
Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Originally-signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Originally-reviewed-on: https://chromium-review.googlesource.com/293942
BUG=chrome-os-partner:40828
BRANCH=none
TEST=Verify that acpi interrupts are incrementing on kunimitsu.
Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad
Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295048
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11432
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The patch was ported from commit: glados: fix kepler probing
BUG=chrome-os-partner:44326
BRANCH=None
TEST=Built and booted kunimitsu. lscpi shows the device on bus 2.
Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa
Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e
Original-Originally-signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810
Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295164
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11431
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch adds the ASL files with the DPTF related settings and the
thermal devices enabled in the SOC. It also enables the DPTF setting
at the global NVS level.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7
Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293391
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11430
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch includes the DPTF specific ASL files in the main
DSDT definition and enables the CPU thermal participant device
in the device tree. It also enables the DPTF flag in the global
NVS table.It also adds the ASL settings specfic to the mainboard.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c
Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284821
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294650
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11429
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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forward port of "glados: make EC_SMI_L functional",
commit 50ed38feba58f
BUG=None
BRANCH=None
TEST=Built and booted kunimitsu.
CQ-DEPEND=CL:295012
Change-Id: I41daeb8b729f2de117b5d57c460925437460e50a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: d9308c0b8eb05c756d88dc0c3d761c9e76d07e08
Original-Change-Id: Ia90c70d21af75d0f0da2af2b4437ccf26659a157
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295045
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11428
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use the macro for GPP_E22_IRQ instead of the ACPI code so it
can be removed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot
Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5
Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295171
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11427
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
config to coreboot completely
BUG=None
BRANCH=None
TEST=Built and booted kunimitsu.
CQ-DEPEND=CL:295012
Change-Id: I78e16e8079c4ee0c4fa70cb7a74ba039ee89398f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 6f1db1a2ffdbeb7dd21b4894f74d3feb44d69c49
Original-Change-Id: I8aafb0ef7d1b77cb8d386f4e73dc46ea3d8ee3a4
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294758
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11426
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
BUG=chrome-os-partner:44336
BRANCH=None
TEST=Built and booted kunimitsu. Validation shows no regressions.
CQ-DEPEND=CL:294757
Change-Id: If4207e87cf22982162a8d5d47fa9e0509a2b2ab1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 2f43fd6b7afc426d041a242a7e03dbf5800e1eee
Original-Change-Id: Id8ce1bd2f28d32898e99008e2a602d99a5c1098c
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295012
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11425
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
This is also required for kunimitsu fab3 gpio settings.
BUG=None
BRANCH=None
TEST=Built and booted kunimitsu.
Change-Id: I61d71fe4576cd57d17f21aecb188cd5b7fdecca0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f65c2618a47c71aad277fb2a11b17ade0a97e5f8
Original-Change-Id: Iebf272b5cc3e67ec35259f5b3e9041ab4cdaa207
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294757
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)
Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Created generic library to implement SPI read, write, erase and
read status functionality for both ROMSTAGE and RAMSTAGE access.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and verify SPI read, write,
erase success from ELOG.
Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2
Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294444
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Commit-Queue: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: http://review.coreboot.org/11422
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This is needed to fix error in depthcharge:
src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up
for flag 3.
BUG=chrome-os-partner:44214
TEST=Verify depthcharge prints EC ID on boot up
BRANCH=None
Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3
Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11421
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move the gpio pad configuration prior to SiliconInit()
in case there are dependencies of the pads being configured
in prior to SiliconInit().
BUG=chrome-os-partner:43522
BUG=chrome-os-partner:43492
BRANCH=None
TEST=Built and booted glados.
Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9
Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294642
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11420
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
On proto2 boards the kepler device has its reset line pulled up
to one of its IO rails with a zener in between. This results in the
device not being visible at MemoryInit() time because for some
reason FSP is doing PCIE configuration/probing in that path. Hack
around the broken FSP logic by configuring the pads for kepler's
power and clkreq.
BUG=chrome-os-partner:44326
BRANCH=None
TEST=Built and booted glados. lscpi shows the device on bus 2.
Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2
Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294810
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Export the proper GPIO for EC_IN_RW so it can be picked up and
used by depthcharge/vboot.
BUG=chrome-os-partner:43072
BRANCH=none
TEST=build and boot on glados P2
Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56
Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294712
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The RMT flag that was attempting to disable saved training to
force a full memory train was happening too late. In testing
I was actually hitting a case where FSP was training every time
but it was not because it was properly being told to.
This moves the check of the RMT flag from devicetree to happen
ealier, before it is actually consumed by romstage_common().
BUG=chrome-os-partner:40635
BRANCH=none
TEST=do both power off+on and warm resets to ensure that FSP
is doing a full memory train every time with RMT enabled.
Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7
Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294177
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11417
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The previously driven TX state of the buffer was not
being cleared before or'ing in the new value. Fix this
oversight.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Also dumped assembly and saw the
masking happen.
Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda
Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294541
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11416
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This patch removes FixedDMA channels carryover code from BDW
as in SKL Integrated DMA is present for each serial io controller.
BRANCH=None
BUG=BUG=chrome-os-partner:40383
TEST=Build and Boot kunimitsu. Tested IDMA on UART.
Change-Id: I66c869d310febcda430809d194b53a903a21fd99
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 833a1980329fb03cf487482e9276c076ede0a0fa
Original-Change-Id: If6ce19cd8d60c727c8f2ffcd9bb232521df63f08
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293060
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11415
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.
Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The SOC handler for memory init params is only taking UPD
as an input which does not allow it to use romstage_params.
In addition the UPD input is called params which is confusing
so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a
Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294066
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11413
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The BUNIT controls the policy for read/write access to physical
memory. For the SMRAM range the policy was not allowing dirty
evictions to the SMRAM when the core causing the eviction was not
in SMM mode. This could happen when the SMM handler dirtied a line
and then RSM'd back into non-SMM mode. The cache line was dirtied
while in SMM mode, but when that particular cache line was evicted
it would be silently dropped. Fix this by allowing the BUNIT to honor
writes to the SMRAM range while the evicting core is not in SMM mode.
The core SMRR msr provides the mechanism for disallowing general access
to the SMRAM region while it is not in SMM mode.
BUG=chrome-os-partner:43091
BRANCH=None
TEST=Run suspend_stress_test and ensure there is no hang SMI handler
on suspend-path.
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2
Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f
Original-Reviewed-on: https://chromium-review.googlesource.com/292890
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: http://review.coreboot.org/11412
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TEST=Builds and boot on Cyan verified by DPTF team
BUG=None
BRANCH=None
Change-Id: I38ddf4a104eb3183d424b5df6b5eab9d406327ef
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 47cbf3893f7d5f1dfad73f57a71ade9382b0a06a
Original-Change-Id: Ide4b3987bfa5e7ec60ee4f47d0663bb71f8330b9
Original-Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291063
Original-Commit-Queue: Prince Agyeman <popagy@gmail.com>
Original-Tested-by: Prince Agyeman <popagy@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11411
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=None
Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175
Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289832
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11410
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Avoid ASSERT() when a better solution exists, avoid UPPERCASE types
when C99 types exist, and use stdlib functions where possible.
Change-Id: Ia40ec8ff34ec82994b687d517dc4b145fb58716c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We don't need the code in romstage, and it saves us a few #ifdefs.
Change-Id: I26d867566f07c7d80890cd01bf055be7497130d3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11457
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It doesn't make sense to die() when printing information. In fact the
die() are protected by DISPLAY_HOBS config option. This can get
confusing, so replace die() calls with printk().
Also since these messages are designed to be informational, keep them
at BIOS_INFO log level.
Change-Id: Id75b9a54f4aea23074a7489d12809cc2da05f1cd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11456
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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