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2020-08-13mb/google/zork: Add helper function to read DB ID bits in FW_CONFIGBhanu Prakash Maiya
Add helper function variant_get_daughterboard_id() to read daughterboard id bits (0-3) in firmware configuration table in CBI. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if daughterboard id bits (0-3) can be read from FW_CONFIG. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: Ia3c882439bfbe6da28be2df0ec0c976d5c142677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13mb/google/zork: Remove validity checks for FW_CONFIG in CBIBhanu Prakash Maiya
After confirming that all zork variants and phases have valid FW_CONFIG value in CBI, this patch is dropping FW_CONFIG validity checks like VARIANT_HAS_FW_CONFIG and VARIANT_BOARD_VER_FW_CONFIG_VALID in Kconfig and will also remove associated helper functions. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if FW_CONFIG bits can be read in coreboot and FW_CONIFG helper function do not return 0 if board has a valid FW_CONFIG in CBI. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I633dc7c500ef8759f3fffb0db6b76d96257c3c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13libpayload: cbgfx: Add color mapping functionalityYu-Ping Wu
Similar to set_blend(), add set_color_map() for mapping background and foreground colors of a bitmap. Also add clear_color_map() for clearing the saved color mappings. Note that when drawing a bitmap, the color mapping will be applied before blending. Also remove unnecessary initialization for static variable 'blend'. BRANCH=puff BUG=b:146399181, b:162357639 TEST=emerge-puff libpayload Change-Id: I640ff3e8455cd4aaa5a41d03a0183dff282648a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-13mb/intel/tglrvp: Set gpio GPP_H1 for soundcard detectionShaunak Saha
This patch sets the GPP_H1 to PAD_CFG_GPO which is general purpose output with no pullup/down. We need this GPIO for the detection of soundcard in TGL RVP's. BUG=none BRANCH=none TEST=Build and boot tglrvp successfully. From "aplay -l" output check that soundcards are listed properly. Change-Id: Ic0ef33079af7940360c986efacabd6d367aad516 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-13vc/amd/picasso/bl_uapp: Update header fileMarshall Dawson
Update to match the 0.8.6.7B release of PSP blobs. BUG=b:163857965,b:137123167 TEST=Boot Trembyle, run SST Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I728dc17ba2cfb40bc6eaaa30556a3f6bc57d18f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-133rdparty/amd_blobs: Move the pointer for picasso updateMarshall Dawson
Update PSP to 0.8.6.7B. BUG=b:163857965 TEST=none Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I634dadccc51b36f9ac25c3238a794564ce580d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44427 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13superio/*/Makefiles: Remove non-existing directory inclusionElyes HAOUAS
Change-Id: I080f5b67c6e555fcc025ec11a1d15dddfe3a546d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-13soc/intel/skylake: Refactor ternary expressionsFelix Singer
To be consistent with the rest of the tree, replace all left ternary expressions, which are used for device enablement / disablement, with `dev && dev->enabled`. Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-13mb/asus: Add Asus A88XM-E FM2+ with documentationBalazs Vinarz
The port is based on the F2A85-M, the main differences are: - 2 DDR3 dimms - 2 PS/2 ports - 2*USB2.0 and 2*USB3.0 ports - 3+2 phase VRM - 6 channel audio - 6 SATA ports - ASP1206 VRM controller - Bolton D4 chipset - no optical SPDIF/IO Successfully booted configurations: -RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0 -CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland) -OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019 -SeaBIOS: 1.12 and 1.13 Known problems: - IRQ routing is done incorrect way - common problem of fam15h boards - Windows 7 can't boot because of the incomplete ACPI implementation Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13drivers/intel/fsp2_0: don't select FSP_USES_CB_STACK on FSP 2.0 platformFelix Held
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0 based, so it doesn't reuse coreboot's stack, but sets up its own stack. In contrast to all other FSP 2.0 based platforms, this stack isn't in the CAR region, since AMD Picasso doesn't support CAR and the DRAM is already available when the x86 cores are released from reset. Selecting FSP_USES_CB_STACK ended up doing the right thing, but is semantically wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso we take the corresponding code path if ENV_CACHE_AS_RAM is false which is only the case for non-CAR platforms. BUG=b:155501050 TEST=Timeless build results in an identical binary for amd/mandolin, asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases here. Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-08-13soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processorJonathan Zhang
Add CPUID for CPX-SP A1 (also called QS) processor. DeltaLake DVT server uses CPX-SP A1 processor. TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-13mb/google/volteer/var/halvor: Update dq/dqs mappingsFrank Wu
Update dq/dqs mappings based on halvor schematics. BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Then boot Halvor successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id4ffcbd4f015afe6507ed2b1d562519c5b240409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-13mb/google/volteer/halvor: Enable card reader function on HalvorFrank Wu
Configure gpio settings for enabling card reader function. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the sd card is mount on /dev/mmcblk0 successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I51752f47bc8d31d3a11da728ce00ca754381fde9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44169 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13soc/mediatek/mt8192: Add spi driverQii Wang
Add driver for MT8192 SPI controller TEST=Boots correctly on MT8192EVB Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-13sb/intel/bd82x6x/me_8.x.c: Relocate `mkhi_end_of_post`Angel Pons
This reduces the differences between both ME source code files. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I08e07ca2691bb854682692476153a98967bf05da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-13soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitionsSridhar Siricilla
Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob into FW_MAIN_X partitions. BUG=b:145796136 Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13security/vboot/Makefile.inc: Update regions-for-file functionSridhar Siricilla
This patch updates regions-for-file function in the security/vboot/Makefile.inc to support adding a CBFS file into required FMAP REGIONs in a flexible manner. The file that needs to be added to specific REGIONs, those regions list should be specified in the regions-for-file-{CBFS_FILE_TO_BE_ADDED} variable. For example, if a file foo.bin needs to be added in FW_MAIN_B and COREBOOT, then below code needs to be added in a Makefile.inc. regions-for-file-foo := FW_MAIN_B,COREBOOT cbfs-file-y := foo foo-file := foo.bin foo-type := raw TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I1f5c22b3d9558ee3c5daa2781a115964f8d2d83b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-13mb/google/asurada: Add new MT8192 mainboard "Asurada"CK Hu
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada". Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13soc/mediatek/mt8192: Add DRAM resource in ramstageCK Hu
Add DRAM resource in ramstage to load payload. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-13soc/mediatek/mt8192: Initialize build rulesCK Hu
The first Makefile to support building minimal stage files for MT8192 SOC. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13soc/mediatek/mt8192: Add a placeholder for the EMI driverCK Hu
Add minimal function to report SDRAM size. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: If74b6b52dd6e91d1ff40cf8460b6a03b2f3bb6f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43961 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13mb/google/zork: Update PICASSO_FW_*_POSITION to match new layoutFurquan Shaikh
CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB") updated the flash layout which moved RW_SECTION_A and RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION and PICASSO_FW_B_POSITION configs need to be updated accordingly to retain the same behavior as before i.e. amdfw_a/b are placed at the start of FW_MAIN_A/B by placing them right after the CBFS header. This change fixes the value of PICASSO_FW_A_POSITION and PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS. BUG=b:161949925 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13mb/google/zork: Disable ACP I2S wake for schematic version 3.6+Furquan Shaikh
Starting with v3.6 of reference schematics, headphone jack interrupt is moved to a standard GPIO instead of using CODEC_GPI. Thus, we no longer need I2S wake to be enabled in the ACP for boards using v3.6+ version of schematics. This change sets `acp_i2s_wake_enable` and `acp_pme_enable` to default 0 in baseboard devicetrees and overrides to 1 in update_hp_int_odl() if the board is still using older version of reference schematics. BUG=b:159934887 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44403 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13drivers/intel/fsp2_0: Fill EFI_CPU_PHYSICAL_LOCATION structure informationSubrata Banik
Latest EDK2 code inside "UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c" is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence coreboot need to fill required information (package, core and thread count). TEST=Able to see package, core and thread information as part of FSP debug log. Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-08-13vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3313Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3313. Previous version was 3274. Changes Include: 1. Update comments 2. Fix comment typos 3. UPD offset updates BUG=b:163582213 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2784c5b7c8f71c1355c1c36a27cc88080c7c2647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-08-12mb/intel/tglrvp: Add interrupt _CRS under CREC scopeJohn Zhao
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15 assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as active low and level interruptible for EC sync interrupt configuration. BUG=None TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC current resource settings. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/google/volteer/halvor: Update settings for WiFi/BT functionsFrank Wu
Configure gpio/overridetree settings for WiFi/BT functions. Then WiFi/BT functions are enabled on Halvor. BUG=b:153680359, b:163004808 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that WiFi/BT can scan devices successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/google/zork: expose stop gpio for trembyleAaron Durbin
In CB:43701 the trembyle touchscreen parameters were not updated to expose the stop gpio properly. BUG=b:162973325 Change-Id: I6f5da1c556ba1c6ccabf699491d3b635aa79f7c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-12soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddressSridhar Siricilla
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with 0xfed1a000. This causes HECI transactions to fail between FSP-M call and postcar. BRANCH=puff TEST=Verified sending HECI commands before and after FSP-M call on hatch. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-12mb/google/dedede/variants/drawcia: add DTT supportSumeet R Pawnikar
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control. BRANCH=None BUG=b:161993459 TEST=Built for dedede system Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-12soc/amd/common/espi_util: rename espi_check_statusFelix Held
espi_poll_status describes better what the function actually does, since it polls the status register instead of just doing a single read to check. Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-12sb/intel/bd82x6x: Make `pch_silicon_supported` staticAngel Pons
It's not needed anywhere else. Change-Id: Ibc02e432bbc669b3fcfcb8add3c7b0c2a9f77d77 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44339 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12sb/intel/lynxpoint: Move IOBP API to its own compilation unitAngel Pons
Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41946 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons
Add the ranges of bitfields as comments on the struct. Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel/i82801jx/sata.c: Simplify constant is_mobile parameterAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: I30cdca0240afced2949639193caa2f11aca1c60d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel/i82801jx/sata.c: Drop always-false is_mobile checkAngel Pons
Also remove the meaningless `sata_traffic_monitor` devicetree option. Function parameters will be removed in a reproducible follow-up. Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12sb/intel/i82801jx: Drop is-mobile checksAngel Pons
There's no mobile ICH10 variant. This was copied from i82801ix. Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel/i82801ix/lpc.c: Align with i82801jxAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12sb/intel/i82801ix: Use macros for LPC_ENAngel Pons
Taken directly from i82801jx code. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12sb/intel/i82801jx/early_init.c: Drop double blank lineAngel Pons
Change-Id: Ia37c5feb5a61793c10496a2d9cabb7661aa758b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel/i82801ix/early_init.c: Drop unnecessary initial valueAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel/i82801ix/i82801ix.c: Align with i82801jxAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12sb/intel/bd82x6x: Remove incorrect RCBA registersAngel Pons
These were probably copy-pasted from some ICHx southbridge, and then some were corrected because native PCH init uses them. Delete the definitions which are unused and are invalid for this southbridge. Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12sb/intel/lynxpoint: Remove incorrect RCBA registersAngel Pons
These were probably copy-pasted from some ICHx southbridge. However, datasheet shows that some of these are located elsewhere, and some others have disappeared completely. As they aren't in use, drop them. Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel: Remove inexistent references to IDE controllerAngel Pons
This device doesn't exist on these southbridges. Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12volteer: Create lindar variantJulia Tsai
Create the lindar variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=b:161089195 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_LINDAR Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: I08923cde932b7304bcb01cd747530c87949e4692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-12soc/intel/common/block/sata: Add common SATA driverSubrata Banik
Enable PCI_COMMAND_MASTER for SATA controller to ensure device can behave as a bus master. Otherwise, the device can not generate PCI accesses. BUG=b:154900210 TEST=Able to build and boot CML and TGL platform. Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/prodrive/hermes: Add multifunction device for UART 2Christian Walter
On CNP-H, only four I2C controllers are available, so PCI devices 19.0 and 19.1 are missing. However, PCI device 19.2 still exists as UART 2. That function 0 is missing means UART 2 can only be used in ACPI mode. Both devices need to be marked as hidden on the devicetree so that the allocator takes UART 2 into account. Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-12soc/intel/tigerlake: Add IRQs for LPSS uartPatrick Rudolph
Values are taken from pci_irqs.asl. The common code will make use of those defines to generate ACPI SSDT code for LPSS uarts operating in "ACPI mode". Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiBFurquan Shaikh
This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-12mb/google/kukui: revise per-device memory mapping tableHung-Te Lin
In order to help identifying right DRAM info (especially in user space), we want to unify the mapping table and do the device-specific mapping by a virtual offset based on build config. BUG=b:161768221,b:159301679 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12soc/mediatek/mt8192: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12soc/mediatek/mt8192: Add gpio driverCK Hu
Add MT8192 GPIO driver. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43959 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12soc/mediatek/mt8183: Transfer ddr geometry type to dram blobHuayang Duan
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-11amd/picasso/acpi: Add power resources for UART0Kangheui Won
Follow-up for a31a769 - "amd/picasso/acpi: Add power resources for I2C and UART". Now PSP properly handles UART0 D3, we can shutdown UART0. BUG=b:158772504 TEST=suspend_stress_test for 50 cycles, * echo 1 > /sys/module/acpi/parameters/aml_debug_output * dmesg | grep FUR to check on&off for FUR0 [ 2413.647500] ACPI Debug: "AOAC.FUR0._OFF" [ 2413.736265] ACPI Debug: "AOAC.FUR0._ON" Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fxAngel Pons
With a CPUID of 10676, it is clearly model_1067x... Wait, it's already there, but the comment is wrong. This ID isn't for Core Duo CPUs. Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-11soc/intel/common/block/gspi: Recalculate BAR after resource allocationJes Klinke
The base address of the memory mapped I/O registers should not be cached across resource allocation. This CL will evict the cached value upon exiting the BS_DEV_RESOURCES stage. Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKsJonathan Zhang
CPX-SP has a CSTACK and 3 PSTACKs. Clean up the HOB header file to remove reference to non-existing PSTACKs. Adjust mainboard code accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-11xeon_sp/cpx: Enable PCH thermal device via FSPJohnny Lin
Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings. Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11soc/amd/picasso: Correct processor ACPI scopeJason Glenesk
Change namespace from _PR to _SB. Cq-Depend: chrome-internal:3208104 BUG=b:153242529 TEST=Boot a trembyle with change applied and dump SSDTs to ensure processors are in _SB scope. Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11soc/amd/common/espi_util: espi_send_command: improve error messageFelix Held
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the command failed, so we expect that one to be set. Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: espi_std_io_decode: fix edge case bugFelix Held
When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges. Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: simplify espi_std_io_decode functionFelix Held
We can just return at all places where the ret variable was written before its value gets returned at the end of the function. Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: make decode enable parameter uint32_tFelix Held
Since this is a bit mask applied to the raw value of a 32 bit register, this should be a 32 bit unsigned type. Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: make reg parameter unsignedFelix Held
Th register number passed to the low level read/write functions should never be negative. Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/stoneyridge/acpi: clean up global NVSFelix Held
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge. This patch removes the unused fields. Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-11mb/google/zork: config ddi for dirinbozKevin Chiu
dirinboz does not support native HDMI, config DDI as below: DDI0: eDP DDI1: DP DDI2: DP BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I9dffdf5654680e3c2c0b259ee82a471f8ff14f56 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11mb/google/zork: fix incorrect DRAM SPD table load for dirinbozKevin Chiu
BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Ia736b0f25824eebe4ef25a11646f82963611e3b3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11mb/google/zork: move USB OC pin mapping to trembyle base boardFelix Held
The USB OC pin mapping is similar enough to move it to the base board and just have two overrides for trembyle, which is based on an older version of the schematics, and one override for woomax, which doesn't use one USB port. BUG=b:163081097 Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-11nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph
Add comments found when testing ECC scrubbing code. This is a cosmetic change. Change-Id: I7975f6070c2002930eec407a6b101a1295495b25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph
The scrubbing method was never correct nor tested. Fix that by observations made on mrc.bin. Tested on HP Z220 with ECC memory and Xeon E3 CPU: The whole memory is now scrubbed. Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
* Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10mb/google/volteer: Pull up GPP_D16 instead of driving itCaveh Jalali
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to GPP_D16 but there is a RTS5261 requirement to pull up this pin and not drive it at power on. We can meet this requirement without breaking other boards by changing GPP_D16 to be a no-connect with an internal pull up. Other boards use this signal as an enable input, so changing this to pull up is OK. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-10mb/google/volteer/var/terrador: Update gpio settings for Proto2David Wu
Based on latest schematic and gpio table of terrador, update gpio settings for terrador Proto2. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I64b4fcbaabc487206d14d794af319e6df6f99581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-10mb/tgl: Enable SaGv for TGL-UP3 RVPShreesh Chhabbi
BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully. Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10superio/ite: allow 24 MHz clock for external sensor interfaceMichael Büchler
The interface selection register of the environment controller (EC) gives the choice between "Internal generated 32 MHz" and "24 MHz" for the "SST/PECI Host Controller Clock Selection". Previously the chip was always configured for the 32 MHz clock. Add an option that can be set from devicetree.cb to allow using the 24 MHz clock. Without this setting the automatic fan control on an Acer Aspire M3800 was slow to respond to temperature changes. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10superio/ite: configure EC for fans to full at thermal limitMichael Büchler
This applies to the automatic fan control mode of the environment controller (EC). Previously the affected bit was always cleared while the default value is 1 according to datasheets. Add a variable that can be set per mainboard in devicetree.cb. In the IT8783E datasheet that bit is marked as reserved. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-10mb/lippert: Put files under variants/Angel Pons
This isn't reproducible for some reason, but it is relatively simple. Change-Id: I507229be71ac2c589c7ecd81495d38ce363d26a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43275 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10mb/lippert: Unify mainboardsAngel Pons
Do it quick and dirty but in a reproducible manner. Variants will be set up properly in subsequent commits. Tested with BUILD_TIMELESS=1, both Lippert FrontRunner-AF and Toucan-AF remain identical. Change-Id: I71ff50099787e7806a9ab67429890a1c77061929 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43274 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10soc/intel/apollolake: Rename UART irqsPatrick Rudolph
Use the same names as on other intel socs. Will be used in intel common uart driver. Change-Id: Ia418fefb3f925fe4d000683b5028682cf0b68a9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/apollolake: Add irq.hPatrick Rudolph
Move defines from soc_int.asl to soc/irq.h. The common code uart driver expect it to exist. Change-Id: I000a041120daa8cbe1ca4e4aab48a206bb3e9245 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devicesPatrick Rudolph
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and 0:19.2 can't be detected using standard PCI probing. Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms that advertise its PCI conformance by the _ADR attribute. Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/common: Include Alder Lake SATA controller device IDsSubrata Banik
Document Number: 619501, 619362 Change-Id: Id3440b415ca80edebb6880b8b48f6094ebea4ae4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-09soc/intel/{icl.tgl,jsl}: Remove SMRAM register programmingAamir Bohra
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-083rdparty/intel-microcode: Update submodule to 20200616 releaseAngel Pons
Change-Id: Ia250765e2cb81d6a39ad00ebbab20e7b87fa42d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43758 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt socJonathan Zhang
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working. There is a change in IIO UDS Hob. TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08mb/google/zork/trembyle: comment why USB OC pin mapping is differentFelix Held
Change-Id: I68b7529733e604ac45919a54e094be7eeb044458 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08soc/intel/skylake: Enable CIO depending on devicetree configurationFelix Singer
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08soc/intel/skylake: Enable SA IMGU depending on devicetree configurationFelix Singer
Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Add IMGU definitions to pci_devs.hFelix Singer
Change-Id: Iee7393ae7e2aca94151c242894c64ac902f4d437 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Enable SDXC depending on devicetree configurationFelix Singer
Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08mb/asrock/h110m: remove unused Device4Enable from devtreeMaxim Polyakov
This option has been removed from the parameters structure for Intel Skylake CPU (commit 9c1c009). Change-Id: I9dc6649ad693d18fdc85046ebbcc730a17fed0bf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner
2020-08-08soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192CK Hu
Add MT8192 address map, memlayout and first Kconfig. MT8192 is similar to MT8183. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43957 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07mb/google/zork: Revert Don't expose reset GPIO for touchscreen to OSMartin Roth
This reverts the code from commit 728c0787f2 that removes the reset GPIO from the touchscreen ACPI interface. That patch exposes a bug which leads to an invalid opcode trap in the touchscreen code. Reverting this gets the system working again, but is not a long-term solution. BUG=b:162596241 TEST=System boots to login screen. Change-Id: I57a070d94f961cec43834c8bedd5dafc8a54171a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43078 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/skylake: Enable thermal subsystem depending on devicetreeFelix Singer
Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.hFelix Singer
Change-Id: Ic83cfbe2a715db317d94c2b9c6cdd8c58a43612f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07soc/amd/picasso/acpi: remove AOAC device enables from global NVSFelix Held
These values in GNVS are written, but never read/used. aoac.asl contains proper ACPI power management functions for the AOAC devices that directly access the state from the device's registers instead of relying on cached values in GNVS, so the corresponding GNVS entries can be dropped. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07xeon_sp/cpx: Enable HWP Intel Speed ShiftJohnny Lin
Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040 Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/broadwell/iobp: Log success in `pch_iobp_write()`Angel Pons
This reduces the differences between Lynxpoint and Broadwell. Change-Id: I759aa98b80c70c5024213bd8795375061bdbbf10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 13:09:48 +0000