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Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ife718dcec765d3b2861bce16f9ca2b6355166800
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I8903450b505701e1fd62c1a70b896a4dfb37d5a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is a copy/paste of picasso with a few things removed. With this
change we can jump into depthcharge.
Allocated resources:
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3
PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4
PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6
PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7
PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8
PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a
PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
TEST=Boot majolica and see depthcharge finally loading:
Starting depthcharge on MAJOLICA...
new_rt5682_codec: chip = 0x1A
Looking for NVMe Controller 0x3004cac8 @ 00:01:07
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This change allows VBOOT to build when the mainboard hasn't implemented
any of the VBOOT functions yet.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50341
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The same functionality is needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No PCI or PNP functions are used in here.
TEST=Timeless build results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No PCI or PNP functions are used in here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I75a816c594b326df8a4aa5458bb055fca35e1741
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Hide the detail of allocation from cbmem from the FSP.
Loading of a BMP logo file from CBFS is not tied to FSP
version and we do not need two copies of the code, move
it under lib/.
Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's not obvious how to set specific byte of a multi-byte field in the
set file. Add an example (and a template) for setting MAC address.
Change-Id: Iea983071682ffebd61757497d43c70cc8214043d
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Change-Id: I71c0b3b28979053b73f22f280ff11ba19ee0eee2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Id7110bb2229e7c8f5f49aae40cfdf50719d0fa25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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util/bincfg's Makefile already has target that generates flash
descriptor. Use it instead.
Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix a common mistake of using KB/MB where KiB/MiB is what actually is meant.
1 MB = (10^3)^2 = 1000000
1 MiB = (2^10)^2 = 1048576
Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39685
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifd4e7b4dbdd51affb5d7696b8f3d50a7a93e767b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ice6158943c61b3e2156a2ebbf96aa73e7cf87a7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use common ACPI code from ec/apple to avoid duplication between boards.
Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disable unused ports and add comments.
Used 820-3023 board schematics as a source.
Change-Id: I2862546ca6f6929a86e77fae7337368742bb9ba8
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Id50b9a0f0e3f90f5288b420280d762b8a86a6527
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I078ca86cf9e948d4dd4338fca842ae3e580228ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I71c296cdc0180a2832aeb51434de3302a54b5db8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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update telemetry to improve the performance.
BUG=b:168585079
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run AMD stardust test => pass
Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50288
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a
Fixes: commit 0322bc5ed8 (src: Remove unused <cbmem.h>)
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50375
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We can never pass memory location of dynamically loaded BMP files in the
static devicetree. The parameters passed to FSP are filled at runtime.
Change-Id: Ib835ec0d9349ec96d5635e228063f2b7000b70fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The only reference to CID1 is in common/acpi/wifi.asl and
only two braswell boards include it. Everywhere else
the value in GNVS was unused.
Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Needed to support build with ACPI_SOC_NVS=n as SMIF object inside
GNVS disappears then.
Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Add support for ME Soft Temporary Disable Mode. In this mode, ME
doesn't load its kernel and freezes at Bring UP (BUP) phase. This mode
is saved in ME NVRAM (and thus will remain for next reboots and
poweroffs).
- Add support of new CMOS option for Sandy Bridge and Ivy Bridge
ThinkPads.
HOW TO USE
To disable ME:
1. nvramtool -w me_state=Disabled
2. reboot
To enable it back:
1. nvramtool -w me_state=Normal
2. reboot
To check current status:
intelmetool -m
Tested on ThinkPad X230 and ThinkPad X220.
BACKGROUND
There's no Intel documentation that would explain how this should be
implemented, in public. Working binary sequence for MKHI command to put
ME in Soft Temporary Disable Mode, as well as a way to bring ME out of
it (by writing to H_GS register), was found and published by researchers
from PT Security:
1. To disable ME, BIOS issues the disable command (before End of Post)
and reboots. ME is supposed to be disabled on the next boot after
DID (DRAM Init Done).
My numerous tests show that issuing the command and rebooting is not
enough. If we reboot too early, ME will not be disabled. Apparently,
it is doing something in background after receiving the command. It
works with a delay of 500-1000 ms.
I also tried to dump all known (documented) registers, such as GMES
and HFS, before and during the next 2 seconds after execution of the
disable command to find a possible indication that something's
changed in ME and we're ready to reboot. Found nothing
unfortunately.
2. To enable ME back, host writes value 0x20000000 to H_GS.
PT slides don't contain any more information on it, but my tests
show, that after writing this value, GMES[31:28] is changing from
0x01 (BUP phase) to 0x03 (Policy Module) to 0x06 (Host
Communication). Then, after some more time, fw_init_complete bit of
HFS becomes 1.
This means that ME starts loading its kernel immediately, without
reboot.
On the other hand, Lenovo BIOS clearly perform a reboot after
enabling it (one reboot after saving the settings, then ThinkPad
logo appears, and then one more reboot). I'm assuming we have to
reset too.
Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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To avoid duplicating this function in ramstage, factor it out.
Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I3be3952aaba1fe2da5490b071b4e3609773e84a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix a typo and do some style improvements.
Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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<arch/cpu.h> is chain included through <cpu/cpu.h>.
Change-Id: Iad7f23080814c6606603d9472a1bd34a6b1bd1a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50304
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I740b0f3341ecc49382f44e8ccabc07148c5cad79
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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<commonlib/cbmem_id.h> is already included through <cbmem.h>.
Change-Id: I0fb22114621a52359dd876fa70d881a1379d4cc2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Old archive is not available anymore. The tint sources inside the new
archive are the same (something changed in a debian subdirectory but
we aren't using it), so a libpayload_tint.patch is still valid.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: If556fac7d1d8379a022f59ed6aee1450b7bc5aa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48616
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most hex values are already lowercase. For consistency reasons, rewrite
uppercase hex values in lowercase.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I185b448ca7822fa89c57efe788e05b582b259c37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50356
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5bcadf04b5d5b9dad3523bce98942f2792be905f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50357
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using MCHBAR32_AND_OR() in these two cases changes the order of
additions slightly. Originally, the MCHBAR offset and the base
register offset (0x5a4/0x5b4) were added first. Due to the added
parentheses in the register macros, now the complete register
offset is calculated first and then added to MCHBAR. Associativity
tells us that this doesn't change the result.
Changes in the resulting binary were verified manually on the
object file.
Change-Id: Id10882225c8e82b02583aa73e73d661c25abdef9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id5b5dc584ab93620ae58cf43fe0d47015d512f82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Clean up cosmetics after refactoring the code. Reflow long lines and
align values in the tables, and also remove a now-unnecessary scope.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I2712c1ad5404d6968d18d762e6048c5da120ff78
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The first RCOMP group (data) is programmed differently, and has its own
tables. Remove the unused first index from the other tables, and adjust
the loop bound accordingly. Cosmetics are cleaned up in a follow-up.
Tested on Asus P5QL PRO (DDR2), still boots.
Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The RCOMP data group is special and is programmed differently. Prepare
to simplify the code by programming it outside of the loop. Subsequent
commits will simplify the logic even further, then clean up cosmetics.
The special DDR3 case in the loop overwrites the command group strength
multiplier value. It doesn't need to be programmed for each RCOMP group.
Add a comment to justify not programming this register while programming
the settings for the RCOMP data group.
Tested on Asus P5QL PRO (DDR2), still boots.
Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I84d5457173598e8ff41dfb048a6858b41c5692ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These settings can be programmed with a single register write. Factor
the writes out into a single function to avoid some redundancy.
Tested on Asus P5QL PRO, still boots.
Change-Id: I3a08c255dd2b0deae650c7fe2ba4e1f4d1cef581
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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MRC uses an incorrect mask when programming this register, but the reset
default value is zero and it is only programmed once. As it makes no
difference, we can safely use the correct mask. Document this difference
in a comment to indicate the deviation from MRC behavior is intentional.
The default value for this register was dumped from Asus P5QL PRO.
Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Consistently use commas after the last element of arrays, and also align
columns of values and comments. Remove `MHz` units from DDR speed values
to avoid confusion, as the memory's actual clock speed is half of these.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Time has proven this statement to be unnecessary. Uncommenting it would
not have any effect on the existing code, thus remove it completely.
Change-Id: Iff4cdd71435e4fd69d4f3284e9fb2830fdd5b173
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
BUG=b:176213181
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ifa1e751354c644e2ad9613253b90eb5db0a1f043
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix compilation on GCC 10.2.1 and address the underlying issue. The
printf format specifier for a size_t type is z.
Change-Id: Ieb1db6c0c3eb4947bd3617e418bac238b70ec08f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Alderlake includes latest VBT (version 237 onwards),which has size of
8.5 KiB. This change is specific to alderlake so utilizing Kconfig option
to increase VBT size specifically for ADL platforms.
BUG=None
BRANCH=None
TEST=Include new VBT and boot the platform. Able to see firmware screen
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No board in tree selects a different base address, so this can be
removed from Kconfig and be treated like the other base addresses in the
I/O space that are defines in iomap.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since I'm not sure if there are non-upstream boards that change the
default of the Kconfig value and the comment says that it needs to match
the binaryPI build, I'll do that change in a follow-up patch to allow
easy local reverts of that.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic0f08c6cb951994be6db19e10f73f0c621521c70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I04dbeade44d480301c9f7d336449bc54e56cb7bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50169
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop casts to prevent pointer arithmetic and for consistency with other
platforms. These macros will be factored out in a subsequent commit.
Change-Id: I959e7378a8bf46fd1772192090a751d7a2f6f470
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49747
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Guarding the MCHBAR macro breaks reproducibility, but should not have
any functional impact.
Change-Id: I8be8d7b8a0f289d2be76d3dec43999f6b42e3265
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49746
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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smbios_type0_bios_version is only defined if HAVE_ACPI_TABLES is set.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I626ab954496833f46d6a785d92cc3b7e7d87e165
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Needed so we can reserve the memory.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We need the same functionality for cezanne.
TEST=Boot ezknil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We don't use spaces.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id617e98db5b0895071ee98265f68f6106058bd63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST=The devices on the internal buses now get resources assigned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The sub-process calls break make's dependency tracking, hence we have
to always perform the calls if we want to allow automatic, incremental
builds.
We let each rule depend on a new, phony target `force-payload`. It has
roughly the same effect as tagging all the targets as phony, but doing
so would feel wrong as some of them are actual files.
Change-Id: I1bc2406db371e8dddbfdf71f68a6665a5b558f5e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ie15aec4059fbeb99f714c3d674df5fabdb7c081c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I34bf659c1a069ccc27ca613bbf86780d4da49259
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47636
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I388d60e6f3aeb2184966152f0934845d42834de0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47634
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new `Makefile.payload` can be included by the Makefiles of pay-
loads for in-tree builds. The basic idea is to use libpayload's
build results without the `make install` step, and to ensure that
incremental builds work. For instance, if libpayload's code changes,
a `make` for the payload would automatically update the libpayload
build and rebuild the payload. But if there are no code changes in
libpayload, only updated files of the payload will be re-built.
The configuration of libpayload is supposed to be automatically
generated from a `defconfig` file. If this `defconfig` changes,
libpayload and the payload will be re-built.
Change-Id: If5319f1bf0bcd09964416237c5cf7f8e59f487a2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47633
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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coreboot's Makefile exports a lot of variables that influence make sub-
processes (e.g. for Kconfig). We don't want these variables leak into
sub-processes for (lib)payload builds, hence unexport them.
Change-Id: I8da2d8db6238d456723b9c22bee80c62e97027b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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coreboot's Makefile exports a lot of variables that influence make sub-
processes (e.g. for Kconfig). We don't want these variables leak into
sub-processes for (lib)payload builds, hence unexport them.
Change-Id: I7d65c0aa6d4550bd6600c437e838339af69496da
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48939
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I37d6cf75ee5a5cb2ff92c89178cd4469dc059403
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46238
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FILO's Makefile will check for libpayload and might not even `clean`
if it's not found.
Change-Id: If5f8f4ecce317e54cd4b5688553cc38220f6e6df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Mark TSEG as reserved, which is done on other platforms as well.
For some reason CorebootPayloadPkg crashes when using the region where
TSEG typically resides, which is basically RAM.
UefiPayloadPkg doesn't show this issue.
Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Add Kconfig option to hide the Management Engine Interface device so
the OS doesn't try to access it, if the Management Engine is in an
inoperable mode, e.g. if me_cleaner is used.
- Also hide the MEI if the ME is in Soft Temp Disable mode.
Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e
Signed-off-by: James Ye <jye836@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id a1afae4:
2019-10-02 11:47:45 +0000 - (juniper: initial setup)
to commit id a2390f3:
2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set)
This brings in 4022 new commits.
Change-Id: Ib13921aa78a60f88455223eff602296abc424ca8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48212
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode)
ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank)
BUG=b:165768895
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
2. power on test ok
Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch includes the bootblock and verstage changes for
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:178656936
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:179100924
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There has been some repeated discussion about how header includes should
be formatted, specifically on the topic of chain-including. The coding
style currently doesn't say anything about the topic but clearly people
have some basic assumptions. This patch tries to codify some common
ground rules that are supposed to reflect the existing practice.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:175143925
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50091
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:175143925
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.
This implementation also selects the respective MP services PPI version
supported for SoCs
BUG=b:169196864
Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
in preparation to allow V1 and V2 versions of MP services PPI.
TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom
Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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