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2017-05-04nb/intel/x4x/raminit: Change reset type on incomplete raminit resetArthur Heymans
The checkreset() function checks if raminit previously succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the system BOOT_PATH_RESET path will be taken. This boot path can only successfully initialize memory if the system was reset from a state where raminit succeeded, which is not the case here. This can be fixed by issuing a cold reset instead of a hot reset. Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-04mb/lenovo/x200: Make button on dock to undock workArthur Heymans
Fetched from vendor DSDT. Change-Id: Ib74408802e977d9caabcb815c9cbd06bd8dbe395 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kevin Keijzer <kevin@librepractice.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-05-04mb/google/eve: Remove code to set keyboard backlight at bootDuncan Laurie
Remove the code that was enabling the keyboard backlight at boot since this is not desired behavior for this device. BUG=b:35581264 TEST=build and boot on Eve and ensure keyboard backlight does not turn on when booting but can still be enabled in the OS. Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-04mb/google/eve: Set SUSWARN# pin to native functionDuncan Laurie
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied to SUSACK# in the schematic and and is intented to be used in Deep Sx so it should not be configured for GPIO mode. BUG=b:35581264 TEST=build and boot on Eve platform, test that Deep S3 and Deep S5 are still functional. (this change should have no visible effect) Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-04intel/skylake: nhlt: Add 48Khz 2ch 16bit config for max98927Duncan Laurie
This changelist adds the 48Khz 2ch 16bit NHLT configuration for the Maxim 98927 speaker amplifier codec. BUG=b:35585307 TEST=manual testing to ensure speaker output is functional on Eve board Change-Id: Ieda988b557ecefdace5f81b474a952af56e69315 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-03Documentation/Intel: Add vboot documentationLee Leahy
Add documentation which describes how to build and sign a coreboot image which enables vboot. TEST=None Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03google/gru: skip usbphy1 setup for Scarletphilipchen
Board Scarlet doesn't use usbphy1. BUG=b:37685249 TEST=boot Scarlet, check the firmware log, and confirm no errors about USB1 Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-03util/autoport: Add the PCI ID of the iGPU for the Intel i7 3770KOmar Pakker
This adds one of the Xeon labeled PCI IDs used in Sandy-/Ivy Bridge generation processors. This ID is used by the non-Xeon i7 3770K. Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0 Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/19516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-03drivers/{aspeed,xgi_z9s}/Kconfig: Don't override NATIVE_VGA_USE_EDIDArthur Heymans
device is run before drivers to generate .config and the first default takes precedence so this override achieves nothing. Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03nb/intel/gm45: Set display backlight according to EDID stringArthur Heymans
Add some known good values for some thinkpads displays. Known good means that at this pwm frequency the display is evenly lit on all duty cycles, the display makes minimal to no noise at lower duty cycles and the display does not flicker. This values differs from vendor (which uses an obviously wrong display clock (190MHz instead of 320MHz) resulting in frequency more than 60% off the intended value. TESTED on Thinkpad X200 with edid ascii string in list and removed from list to see if notice message is shown. Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03lib/edid: Save the display ASCII stringArthur Heymans
Change-Id: Ic31af53dcb9947e2264c809ee8f80ea4f89f347d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03nb/intel/gm45/gma.c: Decode EDID before NGI pathArthur Heymans
This allows to use EDID data outside of NGI path without needing to fetch it twice. Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03lib/edid.c: Differentiate between absent and non-conformant EDIDArthur Heymans
Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03lib/edid.c: Allow use of when not NGIArthur Heymans
Change-Id: I8709e3e61686979137b08d24efad903700d18e0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03mainboard/google/poppy: Add support for cr50 I2C TPMFurquan Shaikh
1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03mainboard/google/poppy: Update GPIO table for next buildFurquan Shaikh
Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-02cbmem: Add new command line flag to dump console for one boot onlyJulius Werner
Even though the persistent CBMEM console is obviously awesome, there may be cases where we only want to look at console output from the last boot. It's easy to tell where one boot ends and another begins from the banner message that coreboot prints at the start of every stage, but in order to make it easier to find that point (especially for external tools), let's put that functionality straight into the cbmem utility with a new command line flag. Use the POSIX/libc regular expression API to find the banner string for maximum compatilibity, even though it's kinda icky. Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-02soc/intel/apollolake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-02soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-02soc/intel/skylake: Set xtal bypass on low power idleNaresh G Solanki
When using Wake On Voice &/or DCI, it requires xtal to be active during low power idle. With xtal being active in S0ix state power impact is 1-2 mW. Hence set xtal bypass bit in CIR31C for low power idle entry. TEST= Build with s0ix enable for Poppy. Boot to OS & verify that bit 22 of CIR31C register is set. s0ix works. Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19442 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-02amd/pi/hudson: Add config option for ACPI baseMarc Jones
Add a configuration option to assign the binaryPI base address for the ACPI registers. The binaryPI's assignment is determine at build time and no run-time configuration is allowed. Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-02amd/pi/00670F00: Reserve A0000-FFFFFMarshall Dawson
Claim memory-mapped regions in the legacy area. Claim an MMIO resource for the A000 and B000 segments, and reserved resource for C000 through F000 segments. These changes allow code and information to be retained in the event unused regions get wiped. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit d612d4fe69881609d42053496409c452e1014947) Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19156 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-05-01cbgfx: Add portrait screen supportNickey Yang
cbgfx currently does not support portrait screen which height >width. so add it. Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19474 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-01arch/x86: Share storage data structures between early stagesLee Leahy
Define a common area in CAR so that the storage data structures can be shared between stages. TEST=Build and run on Reef Change-Id: I20a01b850a31df9887a428bf07ca476c8410d33e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19300 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-01soc/intel/common/block: Add Intel common FAST_SPI codeBarnali Sarkar
Create Intel Common FAST_SPI Controller code. This code contains the code for SPI initialization which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h * Implement FAST_SPI read, write, erase APIs. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-01nb/intel/sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I97c3402ac055991350732e55b0dda042b426c080 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01nb/intel/nehalem/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01nb/intel/fsp_sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19307 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01mb/*/mainboard.c: Get rid of SPI AFC registerPatrick Rudolph
The AFC—Additional Flash Control Register is set by southbridge code. Remove redundant calls and get rid of it in autoport. Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19493 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-01mainboard: add support for lenovo x1 carbon gen 1Alexander Couzens
Based on Thinkpad x230 and schematics. Verified by autoport. USB debug port is the left front usb port Thanks to Holger Levsen for the device. Change-Id: I97c8e01a3ce0577d7dc9e8df7d33db3b155fe3d6 Tested-on: lenovo x1 carbon gen 1 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16994 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-01acpi: fix FADT header version for ChromeOS devicesMatt DeVillier
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices' FADT version were incorrectly set to 3, rather than the correct ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these devices reporting compliance to ACPI 2.0, rather than ACPI 3.0. This mirrors similar recent changes to SKL and APL SoCs. Test: boot any affected device and check ACPI version reported vai FADT header using OS-appropriate tools. Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-05-01pci_device: Write vendor ID to subsystem vendor IDRizwan Qureshi
Write vendor/device id to subsystem vendor/device id if they are not provided. Change-Id: I5027331a6adf9109767415ba22dfcb17b35ef54b Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19467 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-01Documentation: Add technote/design doc for mitigating ReBAR issuePatrick Georgi
Change-Id: Icba9d7910dfd46f32a2c46b6fd064a9cc8e3beac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19242 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-01intel/kblrvp: Enable audio in RVP7 and RVP3Naresh G Solanki
Enable audio: * Add verb table for ALC286 & ALC298 * Enable virtual channel 1 for DmiVc1 & HdaVc1. TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified working of audio on both the boards. Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18875 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-01soc/intel/skylake: Add ID for Fizz i7Shelley Chen
Bug=b:35775024 BRANCH=None TEST=boot up successfully to kernel on Fizz i7 sku Change-Id: Iccf9fbef1333f3fea78091b679c2676411559987 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19486 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-01purism/librem13: Enable support for M.2 NVMeYouness Alaoui
Enable/Disable the PCIe ports to match factory BIOS. The port #6 is used for PCIe on the M.2 connector which allows for NVMe SSDs to function. Change-Id: I8058cbad3da651144545d588c0ae78c5f5e598ac Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19446 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-01util/inteltool: Add support for Wildcat Point-LP PremiumYouness Alaoui
The Wildcat Point-LP Premium is handled the same as the Wildcat Point-LP, but it wasn't supported by inteltool. Change-Id: I694514e1963f074582a3f5f81d63c20e7fa49189 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19445 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-01util/inteltool: Break long lines in supported_chips_listYouness Alaoui
Lint prevents my next commit which adds a new line to the table so it's better to break all the > 80 character lines so it will be consistent with the new line I'm about to add. Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19444 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-29libpayload/gdb: fix unused variable warningPatrick Georgi
input_underrun is defined but not used. A reasonably new compiler, enabled warnings and warnings-as-error make the build break for no good reason. Change-Id: Ibeb7ba53aad5738938093ab7b34695c9c99c9afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19482 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-04-29vboot: Separate board name and version number in FWID with a dotJulius Werner
It's standard practice in vboot that the FWID consists of <board_name>.<version_number> (e.g. Google_Kevin.8785.57.0). In fact, some tools rely on this and cut the string at the first dot to separate the two. The current Kconfig default in coreboot instead leads to ugly, parser-breaking FWIDs like Google_Kevin4.5-1234-5678abcd. This patch fixes that. Change-Id: I65cd5285c69e2e485d55a41a65d735f6a2291c16 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19487 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-29rowan: Fix default test HWID.Patrick Berny
Correct the default GBB_HWID to "ROWAN TEST 9387" BRANCH=chromeos-2016.05 BUG=b:35774871 TEST=emerge-rowan coreboot chromeos-bootimage, strings /build/rowan/firmware/image.bin | grep "ROWAN TEST" and look for 9387 in output Change-Id: I7851010305caf056958c8a6a328b0506bf2208cd Signed-off-by: Patrick Berny <pberny@chromium.org> Reviewed-on: https://review.coreboot.org/19488 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-28mainboard/google/soraka: Add support for memory configs 1,2,7 and 8Furquan Shaikh
BUG=b:37712455 Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19472 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-28mainboard/google/poppy: Add SPDs for memory config 1 and 2Furquan Shaikh
BUG=b:37712790 Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28mainboard/google/poppy: Enable separate MRC cache for recovery modeFurquan Shaikh
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:37682566 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: I4c748a316436001c5a33754084ab4a74243e21df Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28commonlib: Add ID for STORAGE_DATALee Leahy
TEST=Build and run on Reef Change-Id: I2f04a01e5e266422e3ef0d90541dc9d39471260c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19301 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-28nb/amdk8: Link coherent_ht.cArthur Heymans
Change-Id: I1ef1323dc1f3005ed194ad82b75c87ef41864217 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19367 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-28sb/nvidia/mcp55: Link early_ctrl.cArthur Heymans
Change-Id: I3a55c2e8077fdb10768df287f38efcd5e2e64bdf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19365 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-28nb/amd/amdk8: Link reset_test.cArthur Heymans
This needs some extra headers in amdk8/raminit.c that were otherwise provided by that file. Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19360 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-28vboot: Select CONFIG_{TPM,TPM2} only if MOCK_SECDATA is not selectedFurquan Shaikh
1. Select CONFIG_{TPM,TPM2} only when MOCK_SECDATA is not selected. 2. Provide tlcl_lib_init for mock TPM case. BUG=b:37682566 TEST=Verified that when mock TPM is used, CONFIG_TPM is not set anymore in coreboot config. Change-Id: If3bdd1528e153b164e9d62ee9cbcc4c3666b8b66 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19456 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-28soc/intel/skylake: Use ITSS common codeBora Guvendik
This patch uses common ITSS library to setup itss irq. Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19244 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28soc/intel/apollolake: Use ITSS common codeBora Guvendik
This patch uses common ITSS library to setup itss irq. Change-Id: Id265505cfc106668aea25ad93e114fe20736b700 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19236 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28soc/intel/common/block: Add Intel common ITSS code supportBarnali Sarkar
Create Intel Common ITSS code. This code currently only contains the code for Interrupt initialization required in Bootblock phase. More code will get added up in the subsequent phases. Change-Id: I133294188eb5d1312caeafcb621fb650a7fab371 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19125 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28soc/intel/apollolake: fix system reset eventlogAaron Durbin
The SRS bit which is supposed to indicate reset button press is non-functional. If it did work the system reset event it was associated with is overly specific. Therefore, use the warm reset status bit. BUG=b:37687843 Change-Id: I34dd09c03d2bca72da9a5cdf23121e0d0e621fa6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19484 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-28soc/intel/apollolake: work around full retrain constraints on warm resetAaron Durbin
It's come to attention that apollolake doesn't support a full retrain on warm reset. Therefore force a cold reset when a full retrain is requested in the non-S5 path. BUG=b:37687843 Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19483 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-28soc/intel/apollolake: Update default LPDDR4 CA ODT configRavi Sarawadi
Update default ODT config to have correct CA ODT settings as the current defaults are incorrect for all the current apollolake designs. All the current designs pull both A and B channels' LPDDR4 modules' ODT pins to 1.1V. Therefore, the correct impedance setting needs to be applied. In order for the settings to take effect one needs to clear the memory training cache in deployed systems. Trigger this by bumping the memory setting version for the SoC. If needed in the future support for allowing the override of this setting from the mainboard should be straight forward. It's just not necessary at this time. BUG=b:37687843 TEST=BAT test, warm, reboot, S3 cycle test Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19397 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-28drivers/intel/fsp2_0: add option to incorporate platform memory versionAaron Durbin
On Chrome OS systems a memory setting change is needed to be deployed without updating the FSP blob proper. Under such conditions one needs to trigger retrain of the memory. For ease of use provide an option, FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC and mainboard memory setting version number into the FSP version passed to the platform. The lower 8 bits of the FSP version are the build number which in practice is normally 0. Use those 8 bits to include the SoC and mainboard memory settings version. When FSP, SoC, or mainboard memory setting number is bumped a retrain will be triggered. BUG=b:37687843 Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19452 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-28google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irqJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820 Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452286 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19434 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-28rockchip: gpio: add gpio_input_irq & gpio_irq_statusJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: I5de902ab26fe768b641f69d85a5294baf6d916e3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 223257d486b026c06a1f3a7a830b829efb9932dc Original-Change-Id: I055ad5f59285cee3110d1e7cb1a53a60144712e4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452285 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19433 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-28google/oak: Configure SD card detect pin with a pull-upJulius Werner
SD card detect pins should normally have a pull-up. It seems that for micro-SD cards this doesn't really matter all that much, but for the full-size slots we have on some Oak-derivatives (like Hana) it does. BRANCH=oak BUG=b:35854317 TEST=Booted Hana, confirmed that card detect no longer seemed stuck-on. Booted Elm and confirmed that SD card behavior didn't change. Change-Id: I9b20e0f6fe310e724d191e36ca0a81ab4fe5f593 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c2781eeef50f52c6f02ee9344274ddf4dcb0a946 Original-Change-Id: I428ac92efb07f94265673b04e0e0dd452649b9fd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/452861 Original-Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/19432 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-28crossgcc: disable libsanitizer for the bootstrapped compilerPatrick Georgi
Ironically enough, libsanitizer is notorious for creating "uninitialized variable" warnings with different compiler versions than the one it's shipping with. Since we don't need it for building the real compiler, just skip it. Fixes building our compilers using the gnat-gpl 2014 compilers. Change-Id: I2130dfdf3eaf07d77cd70777419fc0ae4642b843 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19478 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-28fsp_broadwell_de: Add SMM codeWerner Zeh
Add basic SMM support for Broadwell-DE SoC. The code is mainly based on the SMM implementation of Broadwell with a few differences: - EMRR is now called PRMRR and the UNCORE part of it is not available - SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space - currently only SERIRQ-SMI has a handler Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28intel/skylake: Switch FADT to ACPI version 3.0Werner Zeh
On Apollo Lake it was discovered that our current FADT implementation is valid for ACPI version 3.0 but misses fields for ACPI version 5.0. We run into booting issues with Windows 10 using version 5 in the FADT header. In commit 2b8552f49bc3a7d0290f96a84b573669de396011 (intel/apollolake: Switch FADT to ACPI version 3.0) we go back to version 3 for Apollo Lake. Skylake is now the last platform that uses version 5 in FADT header. Change-Id: I2d0367fae5321dee4ccac417b7f99466f8973577 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19453 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28intel/apollolake: Switch FADT to ACPI version 3.0Werner Zeh
The current implementation of the FADT structure is only ACPI 3.0 compliant. Setting the version to ACPI 5.0 results in a corrupt FADT. Linux seems to be able to deal with it but Windows 10 hangs in a really early stage without any notification to the user. If ACPI 5.0 is mandatory, the FADT structure needs to be adjusted to match the specification. Therefore the members sleep_ctl and sleep_stat needs to be added to FADT structure. Change-Id: I51c7a7a84d10283f5c2a8a2c57257d53bbdee7ed Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28build system: when cleaning the tree, remove ..config.tmp*Patrick Georgi
kconfig uses mktemp so ..config.tmp isn't enough. Change-Id: If910a40269783bbf7392b44cda7e9750bc33f14d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19459 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-27amdfwtool: Move normal firmware 2 after fanless firmware2sMarc Jones
Move the images around in the image stitching. This addresses an issue found with PSP firmware loading on the Google Kahlee mainboard. Note firmware1 must come before firmware2 in the image or the PSP will not allow APU to execute. Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27mb/google/eve: switch touchpad devicetree to i2c-hid and cros_ec i2c deviceWei-Ning Huang
The new touchpad firmware uses i2c-hid instead of custom reporting protocol. The touchpad also exposed another slave address (0x1e) for kernel to communicate with the touchpad EC. Change-Id: Iecaf14f7b8aed836120569e9ade9c3115bc00264 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://review.coreboot.org/19461 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-27cpu/amd/pi: Change wrapper to use config optionMarshall Dawson
Add a check for vboot when locating the binaryPI image. There is currently an ordering problem using cbmem to locate the image when vboot is present. Vboot inserts its locator into the search process so that memory can be checked before flash is queried. For the earliest calls using the wrapper, DRAM has not been set up and cbmem not initialized in romstage. This change prevents an endless loop when vboot searches cbmem. This change has another side effect. When vboot is in effect, the change forces the RO binaryPI to be used even when on either of the RW paths. There is currently no ability to relocate the XIP image for use in a RW region. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474) Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27x86/acpi: Use initialized VBIOS in VFCT tableMarshall Dawson
AMD VBIOS option ROMs often modify themselves during initialization. Check for the presence of a VBIOS at 0xc0000 before populating the VFCT table. If a matching ROM is found, use it for the source of the copy. Tested on Gardenia (Stoney) variant by observing amdgpu driver's dmesg output. Change-Id: I5be7e1562bde51800c5b0e704c79812d85bcf362 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19383 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27crossgcc: fix DESTDIR buildsPatrick Georgi
We need to rewrite libtool's files (foo.la) a couple of times so it knows where to look (while still whining that $DESTDIR$TARGET != $TARGET. well, duh.) Change-Id: I54cafd47c76d855222ba905b5eb4533a23bdfd34 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19463 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-27google/poppy: Enable PD MCU deviceShamile Khan
In order for PD charge events to properly notify the OS when a charger is attached we need to enable the PD MCU device and event source from the EC. Without this change the charging still happens, but the OS does not notice and update the charge state icon in the Chrome OS UI. BUG=b:35586577 BRANCH=none TEST=On a poppy board that has the VBUS rework applied, plug in a charger to either port and see charge status updated to indicate charging in the power_supply_info tool and the Chrome OS UI. Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/19441 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-04-27amd/pi/hudson: Add VBNV cmos reset optionMarc Jones
If the mainboard supports VBNV, call init_vbnv_cmos() instead of the normal init_cmos(). The VBNV version does some VBNV pre and post setup around the normal init_cmos(). Change-Id: I34b02409019b945cd68c830e006e99338643f29c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19399 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27i82801gx: Enable PCI-to-PCI bridgeKyösti Mälkki
Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. Since the LPC function claims the resources for IOAPIC, ROM and low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI configuration will not overlap those regions and does not hide the resources mentioned in the original comment. The bridge was disable in the following commit [1] commit a8e1168064b34b46494b58480411a11bc98340f6 Author: Stefan Reinauer <stepan@coresystems.de> Date: Wed Mar 11 14:54:18 2009 +0000 This patch contains some significant updates to the i82801gx component and will be required for a series of later patches. Roughly it contains: but unfortunately it was not noted which system this caused problems with. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6 Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/2706 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-27nb/amd/amdk8: Link raminit_f.cArthur Heymans
For this debug.c needs to be linked too. Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-27google/fizz: Configure HDMI HPD to use native functionShelley Chen
BUG=b:37684299, b:35775024 BRANCH=None TEST=reboot and ensure graphics are displayed through HDMI port. Change-Id: I74a664b2d42f55adfa64f292f6ede4c956e16fbf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19451 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-27google/fizz: Enable SATA on port 1Shelley Chen
BUG=b:37486021 BRANCH=None TEST=compile coreboot and make sure sda and sdb show up in /sys/class/block. Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-27Revert "amd/pi/hudson: Move ACPI IO registers"Kyösti Mälkki
This reverts commit e7394ca90366d35ac52416c21052a3ceb459dc81. Configuration register for ACPI PM base address is initially configured inside the PI blob. Therefore, the value of HUDSON_ACPI_IO_BASE needs to be the same as DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS used in the build of binaryPI blob. Change-Id: I36700e49e21cc675e8e22b06efffb40e9c1e4236 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19454 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2017-04-26mb/intel/d510mo: Add romstage timestampsArthur Heymans
Change-Id: I324edce44ad82217ac1fba177f4a0bb3c799308c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19426 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-26mb/intel/d510mo: enable ACPI resume from S3Arthur Heymans
Replace ram_check with quick_ram_check, because ram_check is slow and is destructive for dram content. Change-Id: I5fb1bfe711549aabb6e597bda22848988a7e9cbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19416 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-26nb/pineview/raminit: Don't do Jedec init on resume from S3Arthur Heymans
This is not needed. Change-Id: Id19a00c1546b7a71d90aa8c7e43e6efde1e9fbbc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19425 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-26mma: Make MMA blobs path SOC specificPratik Prajapati
MMA blobs are SOC specific (not board). So far MMA is supported by big cores (SKL and KBL). Change-Id: I922789a2a12d55360624dd6de15ab9f0bb5f0acf Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/19260 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-26amd/pi/hudson: Add TPM decode to SPI functionMarc Jones
Add a function to send the TPM decode to the SPI interface. Enables use of SPI TPMs on Hudson mainboards. Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19402 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26amd/pi/hudson: Clean up whitespace in header filesMarshall Dawson
Change spaces to tabs and do general whitespace cleanup. Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19401 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26amd/pi/hudson: Move ACPI IO registersMarc Jones
Move the ACPI IO registers from 0x800 to 0x600 to avoid the IO space required by the Google EC, also at 0x800. This shouldn't have any conflicts on other AMD systems. Change-Id: Iac7388c15e899277fd506fb37965164488358335 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19171 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-26amd/pi/hudson: Add LPC IO decode enable functionMarc Jones
Add a function to enable LPC IO decode AKA WideIO. This can enable up to 3 regions, which may be 512 or 16 bytes wide. Change-Id: I2bed3a99180188101e00b4431d634227e488cbda Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-26cbmem_console: Document known reimpementations of console structure/APIJulius Werner
It turns out that there are quite a few other projects that can access the CBMEM console by now. If we ever want to make another structural or behavioral change to it, we need to know where these implementations are so we can make sure they're all getting updated. Let's try to build a comprehensive list in the file that should be the source of truth for all (coreboot's own implementation). Change-Id: Ia3d6a87230f5bfdde9d812bc7154e22880c1377a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19439 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25amd/pi/hudson: Add GPIO get functionMarc Jones
Add a basic GPIO get function. Note that GPIO set, ACPI/GPE, and other features should come in future commits. Future changes to be modeled on the other soc/ gpio functions. Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19159 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25AMD Geode: Move conflicting mainboard_romstage_entry()Marc Jones
The silicon specific mainboard_romstage_entry() in amd/cpu/car.h, which is used by all AMD silicon car code, caused a conflict. Move the silicon specific defines to silicon header files. Also, no longer include car.h in the romstage file. Change-Id: Icfc759c4c93c8dfff76f5ef9a1a985dd704cfe94 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18769 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25soc/intel: Unify `timestamp.inc`Paul Menzel
These files are actually indentical, but unfortunately, the formatting was changed without caring for the already present files. Fix that. Use the license formatting where less lines are used. The next step is to put that in a common location. Change-Id: Iecb263b9d321a33e64988b315220893df2e0045c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19423 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-25util/ectool: Dump ram by defaultArthur Heymans
According to the comment above the default should dump the EC ram, though is never reached since the variable 'write_addr' is not 0, but initialized at -1. Also removes brackets around one line statement below if to make checkpatch.pl happy. Change-Id: I390996b253f2f20682cd9ab2d4f560de6eccfc57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19152 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-04-25util/ectool: Fix timeout on sending EC commandArthur Heymans
When setting output to verbose, it incorrectly reports that it times out on every command. TESTED on Thinkpad X60. Change-Id: I24f05f0c165462d5ba2604c7e2fe139400683275 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-04-25soc/intel/skylake: Fix the PCI ID for SATA controllerFurquan Shaikh
Update the PCI ID for SATA controller on Kaby Lake. Change-Id: Id0b5e0366e04fbac6a57a15407f33f390a2a1856 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19395 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25soc/intel/skylake: use postcar stage for fsp 2.0Aaron Durbin
Utilize the postcar stage for tearing down CAR and initializing the MTRRs once ram is up. This flow is consistent with apollolake and allows CAR_GLOBAL variables to be directly accessed and no need for migrating CAR_GLOBAL variables as romstage doesn't run with and without CAR being available. Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19335 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25device: allow devicetree accesses in postcar stageAaron Durbin
Change-Id: Ib6f8ee937c4f3d8e2c0ff3851a819077fa499ccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19334 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25console: rework log level to not be reliant on ROMSTAGE_CONSTAaron Durbin
The console log level variable doesn't really rely on ROMSTAGE_CONST proper. Instead, the mutability of the variable is based on the current implementation of ROMSTAGE_CONST (__PRE_RAM__). As such directly use that logic for the code. In addition, refactor the code to let the compiler and linker optimize out accesses instead of using the pre-processor. Change-Id: I44bcc409266ef52b9be29f75efde73a6707a53f4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19438 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-25Makefile.inc: ensure cbfs-files-processor-struct has correct ccoptsAaron Durbin
The ramstage-c-ccopts variable needs to be double dereferenced for the cbfs-files-processor-struct handler so all the ccopts are included since the ramstage-c-ccopts is fully constructed later by another function. Without this not all the flags are present on the command line. Change-Id: I5425b3c1f23d767c61f654dd287584403f85d719 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19380 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-25google/gru: change the sd power sequenceCaesar Wang
In the safety considerations, we should make sure the slot of SD is enabled first, since we want to the power switch of corresponding is powered up. The different boards have the different power switch for sdmmc. Some power switch IC need turn on delay for long time. let's move the slot power of SD to romstage and avoid explicit delays or per-board. BRANCH=none BUG=b:35813418, b:35573103 TEST=check the signal for children of gru, and boot up from sd card. Change-Id: Id164e4c4c900c6b1ca0251fc27db4cd36c56f6ff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ea1b01cc13628033b85251dbb44407f075efdc85 Original-Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79 Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/447076 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19430 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25mainboard/amd/gardenia: Remove PMxEE write on S4 resumeMarc Jones
Delete the write to PM register 0xee. This register is not listed in the current BKDG and S4 is not currently supported on this APU. NDA document #47517 "A55/.../A85X fusion Controller Hub Register Reference Guide" provides some clues on the intent of this write. This register has always been observed to power on with a value of 0x08 so the write has no effect. This should be revisited again when SMI and PSP fully implement the support required for S3. Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18494 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25arch/x86: Add read64 and write64 functionsMarshall Dawson
Create new functions similar to read and write of other sizes. Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19394 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25google/oak: Enable dual DSI for rowan and the BOE 8-lane MIPI/DSI panelDaniel Kurtz
Unlike other oak derivatives, Rowan uses an 8-lane BOE tv097qxm-nu0 MIPI/DSI panel that requires dual DSI support. Rework oak display initialization to special case Rowan, which uses a provided edid struct for its panel, special panel backlight sequencing and needs to configure mtk_ddp and mtk_dsi to use dual dsi mode. BRANCH=none BUG=b:35774871 TEST=Boot Rowan in developer mode and see output on the panel Change-Id: I136ba5bd1ab12c4ad92995e066fc6d6cf54d0898 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19389 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
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