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2017-04-24util/blobtool: clean up blobtool.l a bitMartin Roth
- Rewrite STRING and COMMENT expressions to remove need for CHARS. - Clean up regular expressions - get rid of unnecessary expressions. - Remove extra newline from the end of the file. - Clean up stripquotes() function -- Remove unnecessary backslashes in '\"' -- Check malloc for failure -- Remove unnecessary assignment of 0 to the end of the new string, snprintf will take care of it. - Update blobtool.lex.c_shipped to the new version. Change-Id: I002962cfae0816ed3c7a5811dfb1b8b48fdc5729 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19230 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-22nb/intel/pineview/raminit: Fix CONFIG_DEBUG_RAM_SETUP=y not compilingArthur Heymans
The function decode_spd uses undeclared variables and an incorrectly initialized array. Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19336 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-21mb/lenovo/t420: Enable libgfxinitNico Huber
In the single GPU configuration, the T420 has an LVDS port, one DP++ and one VGA port connected to the IGD. Docking solutions feature up to two additional DP/DVI-D ports, also directly connected to the IGD. This makes the list of ports to probe pretty long (takes about 70ms if nothing but LVDS is connected). We could save about 20~30ms if we'd limit the ports in case we are not docked or have a discrete GPU. Change-Id: I8e02c8003ff745d05ee272c59377174847f5219c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19378 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-20mainboard/google/eve: Set touchpad IRQ to level triggeredDuncan Laurie
This commit changes the interrupt configuration for the touchpad to be level triggered so it matches what the device is actually using. When the system wakes from suspend by way of touchpad interrupt, or there is touchpad input while in suspend that does not wake the device (when the device is in tablet mode) the interrupt edge is not seen by the AP so the driver does not handle the event and the touchpad keeps the interrupt asserted and does not send further interrupts. The end result is a non-functional touchpad after resume until it is reset or the driver is reloaded. This happens because the touchpad is actually treating the interrupt as level triggered and expects the kernel driver to read a data packet over I2C before it will de-assert the pending interrupt. BUG=b:35774857 BRANCH=none TEST=Test that the system can reliably wake from suspend by touchpad event via the EC and continue to have a functional touchpad after resume. Change-Id: Iaf7c04d9bc9d945bdcc196dff54c92a2a68368f3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19382 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-20Turn CBMEM console into a ring buffer that can persist across rebootsJulius Werner
This patch allows the CBMEM console to persist across reboots, which should greatly help post factum debugging of issues involving multiple reboots. In order to prevent the console from filling up, it will instead operate as a ring buffer that continues to evict the oldest lines once full. (This means that if even a single boot doesn't fit into the buffer, we will now drop the oldest lines whereas previous code would've dropped the newest lines instead.) The console control structure is modified in a sorta backwards-compatible way, so that new readers can continue to work with old console buffers and vice versa. When an old reader reads a new buffer that has already once overflowed (i.e. is operating in true ring buffer mode) it will print lines out of order, but it will at least still print out the whole console content and not do any illegal memory accesses (assuming it correctly implemented cursor overflow as it was already possible before this patch). BUG=chromium:651966 TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco. Also confirmed correct behavior across suspend/resume for the latter. Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mb/asus/kgpe-d16: Enable TPM when selected in KconfigTimothy Pearson
Issue TPM startup on romstage completion via common LPC TPM code if the TPM was enabled in Kconfig. Change-Id: Id886d6aeefa045fb979f128b1cf4c10fff243b24 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19338 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19google/gru: change kevin boot-time center logic voltage to 925mVDouglas Anderson
Kevin's center logic isn't super clean so it needs 925 mV for center logic. All newer gru variants only need 900 mV. BRANCH=gru BUG=b:37429075 TEST=Reboot tests Change-Id: I8c3bd6c245700b23c27cd5758c35c9993f801cb4 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/479463 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19357 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19google/gru: change center logic voltage to 900mVDerek Basehore
It seems that we should only ever run at 900mV on center logic. Changing it to 950mV before might have just masked over problems that are now fixed. BRANCH=none BUG=chrome-os-partner:56940 TEST=on kevin, run stressapptest -M 1536 -s 1000 Change-Id: I5a09b1b403df800396bb2f2e8c76d14a4519d44a Signed-off-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/391032 Reviewed-by: Douglas Anderson <dianders@chromium.org> Commit-Queue: Lin Huang <hl@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/19356 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-19soc/intel/quark: Move include of reg_access.hLee Leahy
Move include of reg_access.h from pci_devs.h to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: I0d2de96f51c56001cdd06c7974cbc649fde1e89c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19355 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19libpayload/libc/console: Flush input driver buffer on initFurquan Shaikh
When console input driver registers itself, perform flush of input buffer to avoid interpreting any stale key presses before libpayload is run. keyboard.c: Remove the redundant buffer flush. 8250.c: Ensure that serial_hardware_is_present is set before call to add input driver. BUG=b:37273808 TEST=Verified that any key presses in serial console before payload is up do not have any effect after the payload starts running. Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy/variants/soraka: add soraka boardYH Lin
Create Soraka board which derives from Poppy, a KBL reference board. More Soraka specific changes need to be done later on. BRANCH=master BUG=b:36995255 TEST=Build (as initial setup) Change-Id: I8af68d2cf475df56336aa0e3bebe86a54ece1999 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://review.coreboot.org/19343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-19mainboard/google/poppy: Provide nhlt variant APIFurquan Shaikh
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:37375693 Change-Id: I2a4317c112f9e3614bd01eb6809727b73328d29d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide memory configuration variant APIFurquan Shaikh
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:37375693 Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide cros_gpio variant APIFurquan Shaikh
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:37375693 Change-Id: I641afe6bb45f106ddebde081a8ac2c64278ebeb9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Add variant API for board_id and gpioFurquan Shaikh
Provide APIs for board_id() and gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:37375693 Change-Id: Ic3c946e6cb12b3c8ef3e83a1037ed0fc8cffbded Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Prepare sharing directory for variantsFurquan Shaikh
Clean up Kconfig file in order to support variants for poppy. Add BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants to use the common baseboard configs. BUG=b:37375693 Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19console: Add convenient debug level macros for raminitNico Huber
Change-Id: Ib92550fe755293ce8c65edf59242a2b04327128e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19332 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-19nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUPNico Huber
Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten some messages. This saves some KiB to make CBMEM console more usable in romstage. Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-19mb/google/poppy: Add camera supportV Sowmya
Add camera related support * Enable the SA Imaging Unit and CIO2 devices. * Enable TPS68470 PMIC and populate related ACPI objects. * Enable OV cameras and populate related ACPI objects. * Enable Dongwoon AF DAC and populate related ACPI objects. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that ACPI tables have the required entries for all the camera devices. Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18969 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19drivers/intel/mipi_camera: Add MIPI CSI camera SSDT generatorV Sowmya
Add SSDT generator for MIPI CSI camera to create ACPI objects used by the Intel kernel drivers. * SSDB: Sensor specific database for camera sensor. * PWDB: Power database for all the camera devices. * CAMD: ACPI object to specify the camera device type. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated SSDT table has the required entries. Change-Id: Ief9e56d12b64081897613bf1c7abcdf915470b99 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18967 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-04-19mb/google/poppy: Add Image Processing Unit ASLSowmya
This patch includes ipu.asl file in the main DSDT definition to add ACPI entries for IMGU and CIO2 devices. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: Ib7485315cb9468da7c6aa090862657a265121493 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19110 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-19soc/intel/skylake: Add ASL entries for IMGU and CIO2 devicesSowmya
Add ASL entries for IMGU and CIO2 devices * _CCA ACPI object to report that there is no Cache Coherent DMA support. * CAMD ACPI object to specify the device type. These ACPI objects are used by Intel kernel drivers. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: I13050253e18408cdb1e196f8003b3f43299aa5a5 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18968 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19elog: Print timestamp when logging eventJulius Werner
We're already reading the RTC whenever we file an event, we might as well print out the value at that time. Having a few RTC timestamps in the firmware log makes it easier to correlate that part of the log to a particular boot once we start having multiple boots in the log. Change-Id: I750dd18aa2c43c95b8c1fbb8f404c1e3a77bec73 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18mainboard/google/poppy: Clean up gpio.h fileFurquan Shaikh
1. Update formatting of gpio table to fit everything within 80 column limit. 2. PEN_RESET gpio is non-existent. Get rid of it. BUG=b:37375693 Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18mainboard/google/poppy: Enable deep S3 in DC modeFurquan Shaikh
Enable lower power state when running on battery. Deep S3 is not enabled when in AC mode to support standard "docked" config. BUG=b:36087058,b:36723679 TEST=Verified following behavior with USB mouse: 1. If AC is connected when entering S3, USB mouse is able to wake up. 2. If AC is not connected when entering S3, USB mouse does not wake up. 3. If AC is connected when entering S3 and removed after entering S3, USB mouse does not wake up. 4. If AC is not connected when entering S3 and attached after entering S3, USB mouse does not wake up. Change-Id: I141a8d4779de004e27fcd9357cef787a38a27b24 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19276 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18x86/acpigen: Fix BufferSize of ResourceTemplateNico Huber
Don't start counting the buffer size amidst the BufferSize field itself. This should help with a regression introduced in Linux with [1] which checks the BufferSize field. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=57707a9a778 Change-Id: I7349c8e281c41384491d730dfeac3336f29992f7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19284 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17mainboard/asus/kgpe-d16: Remove obsolete reference to TPM ASL fileTimothy Pearson
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static ASL file. Change-Id: I3cb2a8a3ac337d1de8a3c394d7a28155597239d0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-04-17[nb|sb]/amd/[amdfam10|sb700]: Add LPC bridge ACPI names for NB/SBTimothy Pearson
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family10h/15h northbridges and SB700 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge doesn't match the built-in default in tpm.c This is a port of GIT hash d8a2c1fb by Tobias Diedrich. BUG=https://ticket.coreboot.org/issues/102 Change-Id: I1c514e335e194b2864599e5419cfaee830b94e38 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19282 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17mb/lenovo/t60: Remove PCI reset code from romstagePaul Menzel
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit bc8613ec (Fix i945 based boards) fixes that to use the correct delay of 200 ms. This code was then copied over, when adding support for the Lenovo T60. The reset was related to the shipped crypto card on the Roda RK886EX and Kontron 986LCD-M, so is not needed on the Lenovo T60. So remove it, to reduce the boot time by 200 ms. The same change is done for the Lenovo X60 in commit 7676730b (mb/lenovo/x60: Remove PCI reset code from romstage). Change-Id: Ifff43f095a1236c9e9a9ef0687e8efe42e72c971 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19298 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-17arch/x86/acpi: Allow "transparent" ACPI device namesTimothy Pearson
Certain devices, such as the northbridge on AMD Opteron systems, do not require a node in the ACPI device path. Allow such devices to be passed over by the ACPI path generator if the device-specific ACPI name function returns a zero-length (non-NULL) string. Change-Id: Iffffc9a30b395b0bd6d60e411439a437e89f554e Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19281 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17libpayload: cbgfx: Show square images on portrait displaysJulius Werner
CBGFX currently doesn't support portrait screens at all. This will have to be fixed eventually but might take a bit of effort. As a first step to make devices with a portrait panel somewhat usable, this patch will just force a square canvas on these panels and keep the bottom part of the screen black. Also switch set_pixel to calculate framebuffer position via bytes_per_line instead of x_resolution. This is supposed to be the canonical way to do that and may differ in cases where the display controller requires a certain alignment from framebuffer lines. Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19279 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2017-04-17nb/amd/amdk8/exit_from_self.c: Use linker instead of includeArthur Heymans
Don't #include *. but use linker. Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-17sb/amd/pi/hudson: Spell verb in comment with a spacePaul Menzel
Change-Id: I7d0d8e2a20d15cbed30e98cf4468e9fb5dd0f1ad Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19292 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-17payloads/seabios: Update stable from 1.10.1 to 1.10.2Paul Menzel
SeaBIOS 1.10.2 was released on February 28th, 2017 [1][2] with the changes below. ``` $ git log --oneline rel-1.10.1..rel-1.10.2 5f4c7b1 QEMU fw_cfg: Write fw_cfg back on S3 resume c45ca70 QEMU fw_cfg: Add functions for accessing files by key 31b6229 QEMU fw_cfg: Add command to write back address of file aa7219d romfile-loader: Switch to using named structs 2a1d88c QEMU DMA: Add DMA write capability d2ac564 ps2port: Disable keyboard/mouse prior to resetting ps2 controller b0e3c67 vgasrc: Increase debug level ca3ab93 ahci: Set upper 32-bit registers to zero ``` This fixes the problem on a Lenovo X60, that the keyboard is not initialized by SeaBIOS when for example loaded from GRUB. [1] https://www.seabios.org/Releases#SeaBIOS_1.10.2 Change-Id: Idc078ffa896b2e105faabd2d8befeaf9a2a0b6ac Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19290 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-15google/slippy: fix internal mic for falco/wolf variantsMatt DeVillier
The HDA verb for falco/wolf's internal mic was wrong, preventing the mic from working properly in Windows and macOS (the Linux driver overrides the verb table, so wasn't affected). Set the verb connector/jack bits properly, to no connector / no jack detect, in order to fix. Also, make (2) small non-functional fixes: On falco, NID 0x1A was being disabled twice (instead of 0x1A and 0x1B both being disabled - copy/paste error). On wolf, NID 0x19 was set to an internal analog mic, where it should have been disabled (again, copy/paste error). Both these errors were introduced when consolidating/upstreaming and were not present in the original Chromium sources. Test: boot Windows [8/8.1/10] and verify mic functional with Realtek drivers on both falco and wolf. Change-Id: I9c343dda4762f0b1f814318c155e22c59d2da8db Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19262 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-15sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is usedTimothy Pearson
Do not map LPC ROM into the system memory space when SPI Flash is configured instead of an LPC ROM. This resolves a long-standing hard boot hang issue on the ASUS KGPE-D16 and related systems; in a nutshell, the incorrectly mapped LPC ROM overrode low memory required by ramstage, causing decompressed ramstage layout-dependent vectoring to romstage code and subsequent execution of random sections of romstage. Sometimes these random sections of romstage reconfigured the hardware in such a way that it could not access SPI Flash on the next boot attempt. Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19280 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kulesz <daniel.ina1@googlemail.com>
2017-04-15nb/intel/x4x/Kconfig: Don't fix CBFS_SIZE on i82801gx southbridgeArthur Heymans
The x4x northbridge can be paired with either an ICH7 (in the case of g41) or an ICH10 (all other cases: g45, q45, p45, ...). Only ICH10 sometimes occurs with a descriptor, gbe and an ME region. ICH7 is always descriptorless so it makes no sense to fix CBFS to accommodate for those other objects. Change-Id: I4a01dfdbce1807e44932a3ac812110382332abd8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19181 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-15util/inteltool: Add ICH10 (Consumer Base) supportArthur Heymans
Reuses ICH10R functions. TESTED on Intel DG43GT (Not supported by coreboot) Change-Id: If9ae8ba8b95e3a7bf6596ae639eb8cafab583298 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19232 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-15mainboard/google/eve: Remove 'probed' setting from rt5663 codecDuncan Laurie
Remove the 'probed' setting from the Realtek 5663 headset codec I2C device. This was added when we had a hardware issue that was preventing I2C operation because the clock/data lines were swapped. With new and/or reworked hardware this is no longer a problem and we do not want the I2C layer in the kernel to talk to the device before the rt5663 driver. BUG=b:35585307 BRANCH=none TEST=Boot on Eve and verify rt5663 driver still loads properly. Change-Id: Ice38889e8f5d3fd1307056cab10fbe3f4e197749 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-15AGESA: Change guard for VBIOS calloutKyösti Mälkki
Change-Id: Ie046fd3c413585131669193a6669358adf709028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-15AGESA: Unify heap locationKyösti Mälkki
HEAP management is identical enough to move heap away from first 1MiB for all platforms. Change-Id: I4128fc084fe072fef6194d260c05592582b7b0d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19267 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-14google/slippy: clean up NGI and move to libgfxinitMatt DeVillier
- remove old, buggy NGI code from falco/peppy variants - remove superfluous INTEL_DP/INTEL_DDI configs, since already selected by northbridge/haswell - always use libgfxinit when use native init config selected - enable NGI/libgfxinit for all slippy variants The reset of the old Haswell NGI code will be cleaned up in a subsequent patchset. Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init using SeaBIOS and Tianocore payloads on peppy, wolf variants Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18824 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-14util/blobtool & sconfig: Update GENPARSER Kconfig questionMartin Roth
blobtool uses the same sort of update mechanism for the .l & .y files, so update the SCONFIG_GENPARSER Kconfig question to encompass both utilities. - Change the name to UTIL_GENPARSER, and update the help text. - Update sconfig's makefile. - Add the check to blobtool's makefile. - Update the makefiles to check for y, not defined. Change-Id: I6215791c9a019bce37d4a150b65d1fdbb9073156 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-14util/blobtool: Hook into coreboot buildMartin Roth
Add a Makefile.inc, based on sconfig's, to use the _shipped variants so that the build doesn't have to generate them with flex & bison. The GENPARSER check is inactive, and will be updated in the next commit. Add the c_shipped & h_shipped files for the current .l & .y files. Change-Id: Ia6c68bfb6e0611ceb6bc76cc66e43266bafc98ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19228 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-14southbridge/via/vt8237r: Get rid of #include early_smbus.cLubomir Rintel
Use linker instead of '#include *.c'. The smbus_fixup() was changed not to use a structure that's defined by a northbridge since multiple different northbridges can be used. Instead the caller now directly passed the memory slot details. Change-Id: Ia369ece6365accbc531736fc463c713bbc134807 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/19082 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14northbridge/via/cn700/acpi: Add the host bridgeLubomir Rintel
Includes the DRAM controller device that knows which where the division between addresses routed to the main memory and to the PCI bus is. Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14northbridge/via/cn700: Add a default VGA BIOS idLubomir Rintel
This is the actual PCI Id of the internal graphics. Change-Id: I2a25ed35a5b01de6da905619fa9fce96738d1c0e Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18895 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-14northbridge/via/cn700: Add IORESOURCE_BRIDGE resources to AGP bridgeLubomir Rintel
Without them the BS_DEV_RESOURCES stage won't traverse the bridge and the graphics controller would be left without resources assigned. Even worse, the resources would stay based in offset 0 which confuses the MTRR setting code and causes a good chunk of the DRAM to be set to type write combining. With the patch applied, the resources are set: Show resources in subtree (Root Device)...After assigning values. ... PCI: 00:01.0 child on link 0 PCI: 01:00.0 + PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0 + PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1 + PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2 PCI: 01:00.0 - PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 - PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 - PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 + PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14 + PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30 And the caching mode is set properly: MTRR: Physical address space: -0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1 -0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6 -0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0 +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6 +0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 The problem was also spot and discussed here: http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14northbridge/via/cn700: Add some delays during raminitLubomir Rintel
Otherwise, it locks up quickly. Not sure which ones are actually needed and why, couldn't bisect it into removing even a single one. The factory BIOS on a Neoware G170 does 200 0xed reads between setting the registers too. Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18893 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14amd/pi/hudson: Add SERIRQ setupMarc Jones
Enable SERIRQ in quiet or continuous mode based on Kconfig. Defaults to quite mode. Change-Id: Ib40a84719fcc3a5d6b3000c3c0412f1bcf629609 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19234 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14amd/pi/hudson: Add hudson PM register definesMarc Jones
Clean up hudson PM register accesses with some register defines. Change-Id: I5ccf27a2463350baec53b7c79fe0fd4ec6c31306 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19233 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14cbmem: Add custom aligned memcpy() implementationJulius Werner
On some architectures (like AArch64), /dev/mem mappings outside of the area marked as normal RAM use a memory type that does not support unaligned accesses. The libc memcpy() implementation on these architectures may not know or expect that and make an unaligned access for certain source/dest/length alignments. Add a custom memcpy() implementation that takes these restrictions into account and use it anywhere we copy straight out of /dev/mem memory. Change-Id: I03eece380a14a69d4be3805ed72fba640f6f7d9c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18300 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-14payloads/external/depthcharge: Update stable commit idMartin Roth
Update from commit 124af94f - Fri Feb 26, 2016 (skylake boards: unconditionally re-enable 8254 PIT for legacy) To commit eb583fa8 - Wed Mar 29, 2017 (rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz) This brings the stable version of depthcharge forward by 325 commits. Change-Id: I31b3235df6d36409ff1b365e6adb6852281df097 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19220 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-14payloads/external/iPXE: Update stable versionMartin Roth
Update from commit 2afd66eb - Fri Jul 29, 2016 ([pixbuf] Enable PNG format by default) To commit fd6d1f46 - Fri Mar 31, 2017 ([thunderx] Use ThunderxConfigProtocol to obtain board configuration) This moves the stable iPXE commit forward 144 commits. Change-Id: Ia0c97f863be39632c9206ca95b3857047fc37e26 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19221 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-14nb/intel/i945: Fix PEG port on 945gcArthur Heymans
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203). Not running PCIEx16 init which is valid for 945gm seems to fix all issues and instabilities related to the PEG port. According to lspci the link width is at the desired x16. It is unknown if devices requesting a lower width work automatically or need more configuration. What happens is that IGD gets disabled by the disable function in gma.c when an external GPU is found unless CONFIG_ONBOARD_VGA_IS_PRIMARY is set. Setting IGD as secondary makes Linux (4.10) hang, so this behavior is a requirement for now. TESTED on P5GC-MX with a discrete GPU and both CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset. Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18549 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-14mainboard/google/eve: Remove ACPI ALS deviceDuncan Laurie
Remove the ACPI ALS device from the EC configuration because this system has an ALS that is presented through the new EC sensor interface rather than the legacy ACPI interface. BUG=b:37179776 BRANCH=none TEST=Boot an Eve device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19265 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14mainboard/google/eve: Set UART0 to skip initialization in FSPDuncan Laurie
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not set back to native mode by FSP when configured as GPIO input by coreboot. Now that FSP is not touching the pins I also removed the workaround to reconfigure the pins after FSP. BUG=b:35647877 BRANCH=none TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS is booted and they are not set back to native function by FSP. Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19264 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-14mainboard/google/eve: Enable internal pull-down on USB_C{0,1}_DP_HPDDuncan Laurie
These lines act as inputs to both EC and AP and when the corresponding TCPC mux is in low power mode the line is floating. Add an internal pull-down to each GPIO to prevent it from floating in this state. BUG=b:35775012 BRANCH=none TEST=Verify that the kernel does not see a device present on DP when the TCPC mux is in low power mode. Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19263 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-13soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESSFurquan Shaikh
With recent change to use common block PCR (ccd8700c), IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS slipped into the tree. Fix this by replacing all occurrences of IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS. Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19277 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-13mainboard/sapphire/pureplatinumh61: Enable EuP and PMENicola Corna
With EuP and PME enabled the USB power turns off during S5. Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/19073 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-04-13mainboard/google/reef: Configure sdcard card detect (CD) pin GPIO_177Venkateswarlu Vinjamuri
This configures GPIO_177 as native function. This enables OS to boot from sdcard. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13soc/intel/apollolake: Set sdcard card detect (CD) host ownershipVenkateswarlu Vinjamuri
Currently sdcard CD host ownership is always owned by the GPIO driver. Due to this sdcard detection fails during initial boot process and OS fails to boot from sdcard. This implements change in host ownership from acpi to GPIO driver when kernel starts booting. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13mainboard/google/snappy: Increase weida touchscreen reset delayWisley Chen
Weida touchscreen controller needs 130 ms delay after reset BUG=b:35586513 BRANCH=reef TEST=Verified that touchscreen works on power-on and suspend/resume on snappy. Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/19245 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13google/eve: Disable Deep S3 in AC modeDuncan Laurie
In order to support a standard "docked" config disable Deep S3 when connected to AC power. This allows USB devices to wake the device from suspend if it is externally powered, but still retains the lower power state when running on battery. BUG=b:36723679 BRANCH=none TEST=manual testing on Eve for USB wake behavior: 1) when suspended on battery USB keyboard does not wake 2) when suspended while connected to AC a USB keyboard does wake 3) if suspended with AC, and then AC is removed, system does not wake with USB keyboard 4) if suspended without AC, and then AC is added, system does not wake with USB keyboard (it cannot get enabled without waking and re-suspending) Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19240 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13google/eve: Enable WiFi SAR featureDuncan Laurie
Enable the Intel WiFi SAR feature for Eve, which will be used to provide wifi power tables based on values read from VPD. This is enabled based on CONFIG_CHROMEOS because it relies on the presence of VPD code from vendorcode/google/chromeos. BUG=b:36727652 BRANCH=none TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables with the values that were set in VPD. Change-Id: I11c129baca891221177575108ac09ba1707b516e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19241 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13mainboard/google/poppy: Enable internal pull-down on USB_C{0,1}_DP_HPDFurquan Shaikh
These lines act as inputs to both EC and AP. Thus, add internal pull-downs to prevent them from floating. BUG=b:35648530 Change-Id: I42326c810775d5449e99e52e81870970247ce335 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19243 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13mainboard/google/poppy: Add support for cr50 SPI TPMFurquan Shaikh
Put all configs required for enabling cr50 SPI TPM on poppy under POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI TPM on this board. Also, add required callback for irq status and devicetree config for GSPI0. BUG=b:36873582 Change-Id: I67793093c006c1325fc16f669a96126525f83243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13drivers/spi/tpm: Clean up SPI TPM driverFurquan Shaikh
1. Move common TIS macros to include/tpm.h. 2. Use common TIS macros while referring to status and access registers. 3. Add a new function claim_locality to properly check for required access bits and claim locality 0. BUG=b:36873582 Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19213 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-11intel/soc/apollolake: Use intel/common/uart driverAamir Bohra
Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19204 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/skylake: Use intel/common/uart driverAamir Bohra
Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/common/block: Add Intel common UART codeAamir Bohra
Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/18952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/apollolake: Use LPSS common libraryAamir Bohra
Use lpss common library to program reset and clock register for lpss modules Change-Id: I75f9aebd60290fbf22684f8cc2ce8e8a4a4304b0 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19154 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/skylake: Use LPSS common libraryAamir Bohra
Use lpss common library to program reset and clock register for lpss modules. Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19153 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11Documentation: Reflow Kconfig.mdMartin Roth
The original document was written and committed with no regard to line lengths. This makes it easier to write. Now it needs to be easier to read, so wrap the lines at 80 characters where possible. - A couple of headings had to be rewritten to keep them under 80 characters. This required the addition of a new paragraph that had the old header. - Remove URL text that was just duplicating the URL. - All other text is the same, just wrapped. Change-Id: I44833c28750714fccb87296868c1ff78ab7f1d07 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19076 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-11sb/intel/i82801gx: Add i2c_block_read to smbus.hArthur Heymans
Using i2c_block_read speeds up reading SPD four to fivefold compared to sequential byte read. TESTED on Intel D945GCLF. Change-Id: I6d768a2ba128329168f26445a4fca6921c0c8642 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18927 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-11scarlet/gru: skip display because mipi driver not readyShunqian Zheng
Scarlet don't have eDP and MIPI driver is not ready, skipping display for now or else Scarlet would be stuck in reading eDP HPD because there even not power for it. TEST=boot to kernel on Scarlet Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348 Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/19237 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-11google/eve: Limit memory SKU 5 to 1600MHzDuncan Laurie
Due to issues with stability limit the SKU with K4EBE304EB-EGCF memory to 1600MHz instead of 1866MHz. BUG=b:37172778 BRANCH=none TEST=pass stress testing on devices with this memory Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19227 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10nb/amdk8/(pre_)f.h: Don't declare global variable in headerArthur Heymans
This is needed if one wants to use the header more than once. Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-10soc/intel/common/block: Add LPSS function libraryAamir Bohra
LPSS function library implements common register programming under lpss. Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/apollolake: Use RTC common codeSubrata Banik
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: I55e196f6c5282d7c0a31b3980da8ae71764df611 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18700 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/skylake: Use RTC common codeSubrata Banik
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/common/block: Add Intel common RTC code supportBarnali Sarkar
Create Intel Common RTC code. This code currently only contains the code for configuring RTC required in Bootblock phase which has the following programming - * Enable upper 128 bytes of CMOS. Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/apollolake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/common/block: Add Intel common PCR supportSubrata Banik
IOSF_SB message space is used to access registers mapped on IOSF-SB. These registers include uncore CRs (configuration registers) and chipset specific registers. The Private Configuration Register (PCR) space is accessed on IOSF-SB using destination ID also known as Port ID. Access to IOSF-SB by the Host or System Agent is possible over PSF via the Primary to Sideband Bridge (P2SB). P2SB will forward properly formatted register access requests as CRRd and CRWr request via IOSF-SB. Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18669 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10google/eve: Update I2C bus timingDuncan Laurie
Update the I2C rise/fall timings based on newly measured values on a new board with updated pull-up resistor values. Touchscreen: rise time 98ns, fall time 38ms Touchpad: rise time 111ns, fall time 41ns TPM: rise time 112ns, fall time 34ns BUG=b:35583133 BRANCH=none TEST=Each I2C bus frequency was verified on a scope to be ~400MHz Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-09drivers/spi: Get rid of spi_get_configFurquan Shaikh
There is only one user for spi_get_config i.e. SPI ACPI. Also, the values provided by spi_get_config are constant for now. Thus, get rid of the spi_get_config call and fill in these constant values in SPI ACPI code itself. If there is a need in the future to change these, appropriate device-tree configs can be added. BUG=b:36873582 Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-08arch/x86: remove CAR global migration when postcar stage is usedAaron Durbin
When a platform is using postcar stage it's by definition not tearing down cache-as-ram from within romstage prior to loading ramstage. Because of this property there's no need to migrate CAR_GLOBAL variables to cbmem. Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-08AGESA: Add helpers to track heap relocationKyösti Mälkki
Change-Id: Ib43e59e4d4ee5e48abf7177b36cb06fdae40bde9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08AGESA f14: Fix memory clock register decodingKyösti Mälkki
Bottom five LSBs are used to store the running frequency of memory clock. Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08ec/roda/it8518: Do EC write manually with long timeoutNico Huber
The EC may take very long for the first command on a cold boot (~180ms witnessed). Since this needs an incredibly long timeout, we do this single command manually. Change-Id: I3302622a845ac6651bc7f563370d8f0511836f94 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18707 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08ec/acpi: Add function to read EC status registerNico Huber
Change-Id: I7b690d1f23ecf4083952c173be1d3a1246bc1593 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18706 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08libgfxinit: Select CONFIG_VGA when neededNico Huber
This wasn't caught earlier because many boards select it manually. Change-Id: I245ef8f44923b5384123bd549570db7c348e03b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18771 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-083rdparty/libgfxinit: Update submodule pointerNico Huber
Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-07KBL: Update FSP headers - upgrade to FSP 2.0.0Balaji Manigandan B
Updating headers corresponding to FSP 2.0.0 Below UPDs are added to FspmUpd.h * PeciC10Reset * PeciSxReset rest of the changes are update to comments CQ-DEPEND=CL:*340004,CL:*340005,CL:*340006 BUG=None BRANCH=None TEST=Build and test on Poppy Change-Id: Id8ecea6fa5f4e7a72410f8da535ab9c4808b3482 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/19109 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07soc/intel/skylake: Enable XHCI clock gate control in ACPINaresh G Solanki
Enable SS link trunk clock gating & D3hot when device enters D3 state. Similarly disable SS link trunk clock gating & D3hot when device enters D0 state TEST=Build & boot Poppy board. Check working for XHCI wake when DUT is in S3. Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18879 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07intel/minnow3: Clean up Kconfig, devicetree and FMAPBrenton Dong
This patch cleans up the code by: o adding necessary default definitions to Kconfig o removing incorrect definitions from devicetree o removing irrelevant entries from FMD file devicetree.cb and minnow3.fmd carried over a lot of code from google/reef which is not correct for Minnow3 hardware. Minnow3 is not intended to boot Chrome OS and does not need Chrome related flash regions. The erroneous code is removed. These changes are the same as those done for leafhill in commit: 6a48923 mainboard/intel/leafhill: Clean up This was tested by building with the new configuration and booting to UEFI Payload Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07mainboard/intel: Fix checkpatch errors in minnowmaxMartin Roth
This fixes the following issues, with no functional changes: ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar" ERROR:SPACING: space required after that ',' (ctx:VxV) WARNING:LONG_LINE_COMMENT: line over 80 characters WARNING:SPACE_BEFORE_TAB: please, no space before tabs ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition ERROR:SPACING: space prohibited before that close parenthesis ')' WARNING:RETURN_VOID: void function return statements are not generally useful 2 unfixed issues: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses Verified that the binary was the same before and after the changes. Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19078 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>