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2016-02-01southbridge/amd/sb700: Enable extended APIC ID when Kconfig option setTimothy Pearson
Change-Id: I52fc2c2294edead3b5dacf397c0a1ab2e08b1e3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13160 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01southbridge/amd/sb700: Set HPET min tick value to RPR recommendationTimothy Pearson
Change-Id: I766eca6369b60a79a6823bc744934e3f1fbc17b2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13159 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabledTimothy Pearson
The existing code did not allow for the second core of the BSP to reside on an APIC ID other than 1, leading to a boot hang on Family 15h processors when APIC_ID_OFFSET was set to anything other than 0. Furthermore, insufficient AP stack space was allocated for AP start. Change-Id: I4ded3cfb3736149e2265848014352d7622d5042a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13158 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-01mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572DTimothy Pearson
Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13157 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-01util/release: extend release scriptPatrick Georgi
Add the ability to release a given commit id, and normalize the tarballs to use coreboot/1000 for owner and group, and the last commit date as mtime for all files. Change-Id: Ia349f429090fe9804f7f14c226812646e2f712be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13514 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-31buildgcc: Add GNU make to reference toolchainStefan Reinauer
Change-Id: I8a41065880c3fd1f95ee8877031bf1738aaae859 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13519 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-31buildgcc: Update LLVM to 3.7.1Stefan Reinauer
Not much testing, update mostly so we can test with the latest scan-build. Change-Id: I50d28b7e0dfd31f9ae565c8515d5ab1760ca4c62 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-31buildgcc: Rename armv7-a-eabi compiler to arm-eabiStefan Reinauer
The compiler really supports a whole line of ARM CPUs, not just ARMv7a: arm-eabi-gcc: note: valid arguments to '-march=' are: armv2 armv2a armv3 armv3m armv4 armv4t armv5 armv5e armv5t armv5te armv6 armv6-m armv6j armv6k armv6s-m armv6t2 armv6z armv6zk armv7 armv7-a armv7-m armv7-r armv7e-m armv7ve armv8-a armv8-a+crc iwmmxt iwmmxt2 native So let's reflect this in the cross compiler name. Change-Id: I717760d80954655b2de9ae019b813d81e9a75762 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13515 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-31vendorcode/intel: remove unused apple specific assembler macrosStefan Reinauer
Since this code is pulled in through commonlib, it will break compilation of cbfstool on OSX. Change-Id: I342bfa7e755aa540c4563bb5cd8cccacee39d188 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13525 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31drivers/intel/fsp1_1: Fix spelling error in API and copyrightLee Leahy
Change granluarity to granularity. Change wacbmem_entryanty to warranty. Update copyright dates. TEST=None Change-Id: Ib7775cb33616751760919a5850777dc6f77a6be9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13528 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31h8/battery: Fix ASL warning.Vladimir Serbinenko
Change-Id: Idf74e400efa3fea8eb74f372e4f261ab6567db8a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13513 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-31stout: Fix VGA PCIIDs.Vladimir Serbinenko
Change-Id: I7dcde170d0f59ea9886342c0d2c09b70b9d0d84d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13537 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-30kconfig_lint: Add readme documentMartin Roth
The readme describes the operation and usage of kconfig_lint. It also lists all the notes, warnings, and errors that kconfig_lint looks for. Change-Id: I873f394ff93fce42cd9638cbbad6134f1aef3a6a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13464 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: add comments and whitespace fixes.Martin Roth
No functional changes. Change-Id: I40284b68ddda7e19741c5306a8c74761c00e4b35 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13463 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: Skip temp files when looking for unused Kconfig files.Martin Roth
Don't warn on Kconfig.orig and Kconfig~ files when trying to verify that all the Kconfig files in the coreboot source tree are being loaded. Change-Id: Ie7babe60b29735e5ccc5f93f4e42ad82dfb47044 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: Update prompt structureMartin Roth
- The prompts were not getting incremented, so each prompt for a symbol would overwrite the previous. - Record the menu each prompt is in. Change-Id: Ia282a30344d5e135f4f2027be9aff0e49a4e5edb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13461 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: Add warning if tristate type is used in corebootMartin Roth
Although there's no reason we COULDN'T use tristate types, we haven't up to this point. If there's a good reason to use them in the future, this check can be removed. Change-Id: I5f1903341f522bc957e394bc0fd288ba1adab431 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13460 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: merge 'git grep' and 'grep' exclude dir and filesMartin Roth
The code had originally been using standard grep to look through the coreboot tree for Kconfig symbols. When this was switched to git grep, the --exclude-dir options didn't work, and nothing was added to exclude the directories that shouldn't be searched for symbols. This resulted in invalid warnings as it searched directories that had Kconfig symbols for other projects. This merges the exclusion list for both the regular and git versions of grep for consistent behavior. Change-Id: I7fed8b9fa827cb14f7373e7b774acc56e43cb6ff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13459 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: Don't look at IS_ENABLED() text in comments.Martin Roth
This fixes at least one kconfig_lint warning. Change-Id: I35edf57e90315a8372aaf3b41e923cd8dad7386a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13458 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: Exclude some Kconfig symbols from unused symbol checksMartin Roth
The configuration that coreboot uses for setting selected symbols typically involves a structure like this: config BLEH_SPECIFIC_OPTIONS def_bool y select SYMBOL This leads to an an extra kconfig symbol BLEH_SPECIFIC_OPTIONS that is never referenced by anything else, generating a warning. Since this is currently the construct that coreboot uses, filter it out of the warnings for now. Change-Id: I85a95e4c4e8469870c7f219f2a92955819845573 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13457 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30kconfig_lint: merge 'git grep' and 'grep' exclude dir and filesMartin Roth
The code had originally been using standard grep to look through the coreboot tree for Kconfig symbols. When this was switched to git grep, the --exclude-dir options didn't work, and nothing was added to exclude the directories that shouldn't be searched for symbols. This resulted in invalid warnings as it searched directories that had Kconfig symbols for other projects. This merges the exclusion list for both the regular and git versions of grep for consistent behavior. Change-Id: I69a1e0b30fecca152e02a511c82248b6091b3d8b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13456 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-30lint: Add a check for the executable bit being set on source codeMartin Roth
Change-Id: Ia51bd0fa742b2cb17f638c15d669ad1a7f65fefd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13433 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-01-30soc/intel: Add skeleton infrastructure for Apollolake SOCAlexandru Gagniuc
This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-30arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCKAlexandru Gagniuc
Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/13485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-30arch/x86: Rename bootblock.S to bootblock_romcc.SAlexandru Gagniuc
bootblock.S was used strictly for setting up the system so that the assembly generated by ROMCC could be executed. Since the infrastructure now exists to run a bootblock wihtout ROMCC, rename this file accordingly. this is done to prevent any future confusion. Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/11784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-29Revert "northbridge/intel/sandybridge: Fix random raminit failures"Vladimir Serbinenko
It break x230 access to channel 1. This reverts commit 9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238. Change-Id: I8a3b13d17729f25cea3460ac2f87bca3c193d388 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-01-29build system: allow modifying cbfstool options for files-in-regionsPatrick Georgi
By implementing a more complex options-for-region function, special needs for certain files in certain regions can be dealt with. Change-Id: I2e1e08d5357b717011c41675f76908bf2319f91d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13505 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29build system: Unwind multi-region cbfstool add commandsPatrick Georgi
Add files to fmap regions one-by-one, so we can modify options per-file-per-region. Change-Id: Ic3ff5a4e563796c9fdd5705236aef37c883abf5e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13504 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29build system: deduplicate users of cbfs-add-cmdPatrick Georgi
When adding the cbfstool remove requirement of the UPDATE_IMAGE path to cbfs-add-cmd, prebuil[dt]-files become identical in both cases. Change-Id: I80faaf1c83368b9dd00a9f247bf89e6d596be996 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13503 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29build system: deduplicate use of cbfs-autogen-attributesPatrick Georgi
Also drop the second argument to cbfs-add-cmd because it's not needed anymore. Change-Id: Ie01d73f6b2aff09caccc397f72d6d8065624aebe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13502 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29build system: deduplicate the addition of alignment/base argumentsPatrick Georgi
Change-Id: I951606333d19cd6bf655294b8b3097884b6ac9e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13501 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29build system: pass $(file) explicitlyPatrick Georgi
And not in the global context. Change-Id: Ife7394b1343663456c24316df6a07d883adb9ee9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13500 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29build system: separate cbfstool add invocations into separate commandsPatrick Georgi
They used to be chained into a single make shell invocation but now they're individual commands, which makes them easier to manage. Change-Id: I22394fd31989d5180790818153f466c0e7ebbedd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13499 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29build system: reformat cbfs-add-cmdPatrick Georgi
Change-Id: Iccf2c0ac62d410fd541d7aa244b9989b92584c13 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29southbridge/amd/sb700: Add CMOS option to disable legacy USB supportTimothy Pearson
Change-Id: I136c259136ce66a0c319a965ae0ee27f66dce1b3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13155 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29mainboard/cubieboard: use bootblock_mainboard_early_initIru Cai
since commit f1e321001d5954096f06f9a43138219a9a46536e, the UART init should be in bootblock_mainboard_early_init() which runs before console init. (see src/lib/bootblock.c) Change-Id: Ib00afdd6e81e7689fbd743c8a5f547d424896d71 Reviewed-on: https://review.coreboot.org/13448 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INITJean Lucas
Move the default select of "Use native graphics initialization" for Peppy to the ChromeOS section as SeaBIOS (default payload) requires a vBIOS and takes twice as long to load with this option enabled. For the same reasons, this option shouldn't be enabled by default (def_bool y). Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/13493 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29soc/braswell: Fix Global NVS base addressHannah Williams
TEST=Boot to OS Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e Reviewed-on: https://review.coreboot.org/13506 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-29board_status/getrevision.sh: get rid of colons in dir namesMartin Roth
Gnu make won't build in directories that have a colon in their name. When the makefile expands a variable containing a dirctory name that has colons in it, it seems to interpret that as a makefile target, and fails the build. Many other characters also confuse the makefiles, including spaces, ampersand symbols, dollar signs, etc. I've started including scripts into the board-status directories to do the build of the rom that was tested, and this is preventing them from working without renaming the directory before doing the build. Change-Id: I9dd8e4027be21363015cd8df9918610e206afce2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13490 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: pchandri <preetham.chandrian@intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13138 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29arch/arm64: Override bl31 timestamp with coreboot build timestampPatrick Georgi
If coreboot's build process is reproducible (eg. using the latest git timestamp as source), bl31 is, too. This requires an arm-trusted-firmware side merge first (in progress) and an update of our reference commit for the submodule, but it also doesn't hurt anything because it merely sets a variable that currently goes unused. Change-Id: If139538a2fab5b3a70c67f4625aa2596532308f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13497 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-29superio/winbond/w83667hg-a: Add support for W83667HG-ATimothy Pearson
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While the Nuvoton NCT5572D is effectively the same core, and a close enough match to get things working initially, the W83667HG-A has a different LDN mapping and several extra features that require a separate support driver. Clone the Nuvoton NCT5572D and modify according to the W83667HG-A datasheet, version 1.4. Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13156 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-29southbridge/amd/sb700: Add missing DMA setup step from AMD RRGTimothy Pearson
Change-Id: I412a0e5f2e0686b10a295dd7c0e9b537dc1a0940 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13154 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL fileTimothy Pearson
Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13153 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Enable ASUS MIO audio optionTimothy Pearson
The KGPE-D16 supports an optional MIO audio card, which connects to the on-board HDA interface of the SP5100. Enable the HDA interface for use with the MIO card. Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13152 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Move memory test before IMD setupTimothy Pearson
Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13151 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29nb/amdmct/mct_ddr3: Enable mainboard voltage setTimothy Pearson
The existing code used an incorrect macro name to check for mainboard DRAM voltage set support, and as a result no voltages were actually set. Furthermore, the existing code did not contain a centralized voltage assumption for boards that did not have a DIMM voltage set implementation. Use the correct macro name to test for boards with voltage set implementation, and provide a basic fallback to 1.5V operation for boards without a voltage set implementation. Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13150 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson
The existing code generated an incorrect boot APIC ID from node and core number for single node packages, leading to a boot failure when the second node was installed. Properly generate the boot APIC ID from node and core number. Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13149 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.Damien Zammit
Fixed incorrect comment regarding port 80 LPC route. Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstatesDamien Zammit
Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13465 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000Damien Zammit
Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13129 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-01-29nb/intel/x4x: Move to early cbmemDamien Zammit
Previously with errors in the ram init, early cbmem was disabled. Now that the ram is working correctly, set as early cbmem platform and update all (1) boards to use it. Tested on GA-G41M-ES2L Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13131 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29nb/intel/x4x: Cleanup gma.cDamien Zammit
Tidy up the code and move vga_textmode_init() later Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13128 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29nb/intel/x4x: Tidy up raminit and fix msbpos() functionDamien Zammit
- Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13127 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29nb/intel/x4x: Tidy up northbridgeDamien Zammit
- Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29nb/intel/x4x: Fix memory hole with both channels populatedDamien Zammit
Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13125 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-28src/: give scripts a .sh extension for easy identificationMartin Roth
Just rename the two scripts that are in the src/ tree to give them a .sh extension. Since we generally expect files in the src directory to be source files, this allows to identify these as scripts easily. Change-Id: I0ab20a083880370164488d37a752ba2d5a192fdc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28via/cx700: Use zeroptr over 0Patrick Georgi
This eliminates all "ud2" instances from romstage disassembly. Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/13488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Provide a gcc-safe zero pointerPatrick Georgi
zeroptr is a linker object pointing at 0 that can be used to thwart GCC's (and other compilers') "dereferencing NULL is undefined" optimization strategy when it gets in the way. Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12294 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Add interface to program USB2_COMPBG registershkim
Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Tested-by: shkim <sh_.kim@samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen@intel.com> Signed-off-by: shkim <sh_.kim@samsung.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.Freddy Paul
TEST=Plug/Unplug AC Adapter multiple times and make sure device is charging properly. Original-Reviewed-on: https://chromium-review.googlesource.com/303990 Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Original-Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Freddy Paul <freddy.paul@intel.com> Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12748 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi/DPTF: Write TCHG state on AC connect.Jenny TC
DPTF should update the charger cooling device state during boot time and every 3 seconds after boot. But 3 seconds polling doesn't seems to be working with current version of DPTF. This impacts charging since DPTF writes states 4 when charger is not connected at boot time. On connecting the charger, DPTF doesn't write 0 to enable charging. This issue is addressed by calling the PPPC function to read cooling device state and passing the value to SPPC to set cooling device state. This doesn't compromise safety since DPTF can override this value later based on the platform thermal condition. Also this provides additional safety measure in the unlikely event that DPTF crashes and is not re-spawned by OS. With this patch even after DPTF crashes, if the power adapter is plugged it would still allow the system to charge correctly. Original-Reviewed-on: https://chromium-review.googlesource.com/288460 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Jenny Tc <jenny.tc@intel.com> Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12729 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Update DPTF parameters to higher temperature.Divagar Mohandass
Fish bowl HTML5 graphics benchmark with 250 fish is not reaching 60 FPS. This change will update the DPTF parameters to accommodate this test. TEST=Run fish bowl benchmark with 250 fish and check for 60 FPS. Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302208 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi: Fix CID1 offset in commentHannah Williams
Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 Reviewed-on: https://review.coreboot.org/13483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix for auto wake from S5Hannah Williams
Disabling S5 wake from touch panel and trackpad TEST=Build and boot the platform. TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid Plug AC in -> EC boots up and AP will shutdown the platform and open Lid -> platform boots to OS. Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://review.coreboot.org/13425 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Fix for Crossystem "wpsw_cur" statusKumar, Gomathi
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-on: https://review.coreboot.org/13424 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix issues found during static code analysisRavi Sarawadi
TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Get Boot Flash Write Protect statusHannah Williams
Read GPIO to get the status Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13186 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Enable CA MirrorShobhit Srivastava
Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12749 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/cyan: Disable SD Card Detect Simulation in FSPHannah Williams
CQ-DEPEND=CL:12742 Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Disable SD Card Detect Simulation in FSPHannah Williams
CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 Reviewed-on: https://review.coreboot.org/13035 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Disable SD card detect simulation in FSPDivya Sasidharan
CQ-DEPEND=CL:13038 Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Original-Reviewed-on: https://chromium-review.googlesource.com/311850 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Set max frequency to be turbo frequencyHannah Williams
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12736 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Remove support for older rev boardsHannah Williams
Cleaning up code to remove support for early revs of Strago board Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13434 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Configure Boot Flash Write Protect status GPIOHannah Williams
Set up the GPIO(MF_ISH_GPIO_4) to read WP status. TEST=Use crossystem to read the WP status Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff Original-Reviewed-on: https://chromium-review.googlesource.com/302424 Original-Tested-by: John Zhao <john.zhao@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13185 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Enable native mode on sd card cd lineJagadish Krishnamoorthy
Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12741 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Disable unused lines on Gpio North BankJagadish Krishnamoorthy
The unused lines leads to spurious interrupts on few of the systems. TEST=run suspend_stress test and make sure that kbd is working. Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313417 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13176 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix DSP clockfdurairx
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28util/cbfstool: add 'compact' commandAaron Durbin
While assembling CBFS images within the RW slots on Chrome OS machines the current approach is to 'cbfstool copy' from the RO CBFS to each RW CBFS. Additional fixups are required such as removing unneeded files from the RW CBFS (e.g. verstage) as well as removing and adding back files with the proper arguments (FSP relocation as well as romstage XIP relocation). This ends up leaving holes in the RW CBFS. To speed up RW CBFS slot hashing it's beneficial to pack all non-empty files together at the beginning of the CBFS. Therefore, provide the 'compact' command which bubbles all the empty entries to the end of the CBFS. Change-Id: I8311172d71a2ccfccab384f8286cf9f21a17dec9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13479 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28util/cbfstool: add machine parseable printAaron Durbin
In order to more easily process the output of 'cbfstool print' with other tools provide a -k option which spits out the tab-separated header and fields: Name Offset Type Metadata Size Data Size Total Size ALIGN_UP(Offset + Total Size, 64) would be the start of the next entry. Also, one can analzye the overhead and offsets of each file more easily. Example output (note: tabs aren't in here): $ ./coreboot-builds/sharedutils/cbfstool/cbfstool test.serial.bin print -r FW_MAIN_A -k Performing operation on 'FW_MAIN_A' region... Name Offset Type Metadata Size Data Size Total Size cmos_layout.bin 0x0 cmos_layout 0x38 0x48c 0x4c4 dmic-2ch-48khz-16b.bin 0x500 raw 0x48 0xb68 0xbb0 dmic-2ch-48khz-32b.bin 0x10c0 raw 0x48 0xb68 0xbb0 nau88l25-2ch-48khz-24b.bin 0x1c80 raw 0x48 0x54 0x9c ssm4567-render-2ch-48khz-24b.bin 0x1d40 raw 0x58 0x54 0xac ssm4567-capture-4ch-48khz-32b.bin 0x1e00 raw 0x58 0x54 0xac vbt.bin 0x1ec0 optionrom 0x38 0x1000 0x1038 spd.bin 0x2f00 spd 0x38 0x600 0x638 config 0x3540 raw 0x38 0x1ab7 0x1aef revision 0x5040 raw 0x38 0x25e 0x296 font.bin 0x5300 raw 0x38 0x77f 0x7b7 vbgfx.bin 0x5ac0 raw 0x38 0x32f8 0x3330 locales 0x8e00 raw 0x28 0x2 0x2a locale_en.bin 0x8e40 raw 0x38 0x29f6 0x2a2e u-boot.dtb 0xb880 mrc_cache 0x38 0xff1 0x1029 (empty) 0xc8c0 null 0x64 0xadf4 0xae58 fallback/ramstage 0x17740 stage 0x38 0x15238 0x15270 (empty) 0x2c9c0 null 0x64 0xd2c4 0xd328 fallback/payload 0x39d00 payload 0x38 0x12245 0x1227d cpu_microcode_blob.bin 0x4bf80 microcode 0x60 0x17000 0x17060 (empty) 0x63000 null 0x28 0x37cf98 0x37cfc0 Change-Id: I1c5f8c1b5f2f980033d6c954c9840299c6268431 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28mb/intel/d510mo: Use SATA AHCI by defaultDamien Zammit
Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-28mb/intel/d510mo: Use native gfx initializationDamien Zammit
Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13034 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDTDamien Zammit
Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13453 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-28mb/intel/d510mo: Add missing GPIO and GPENDamien Zammit
Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13452 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28nb/intel/pineview: Native VGA init (CRT)Damien Zammit
VGA grub console works but display wobbles left/right drm/i915 driver reports one error: - [drm:i915_irq_handler] *ERROR* pipe A underrun - Monitor does not display 1920x1080 after modeset - Other resolutions look out of sync Cause: suspect single bug in raminit (chipset init) Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12921 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28drivers/intel/fsp1_1: Remove extra include referencesLee Leahy
Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-28Move object files to $(obj)/<class>/Nico Huber
Instead of tagging object files with .<class>, move them to a <class> directory below $(obj)/. This way we can keep a 1:1 mapping between source- and object-file names. The 1:1 mapping is a prerequisite for Ada, where the compiler refuses any other object-file name. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13181 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-28Makefile: Make full use of src-to-obj macroNico Huber
There were several spots in the tree where the path to a per class object file was hardcoded. To make use of the src-to-obj macro for this, it had to be moved before the inclusion of subdirs. Which is fine, as it doesn't have dependencies beside $(obj). Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.Kane Chen
LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage TEST=Test on Strago and make sure the leakage is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352 Original-Reviewed-on: https://chromium-review.googlesource.com/317020 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13175 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: EC_IN_RW gpio input configuration.Divagar Mohandass
Configure EC_IN_RW signal as gpio input. TEST=Boot to Chrome OS in normal mode and enter recovery mode use ctrl-d to switch to Dev mode. Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304040 Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/13124 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Clean up DDR configuration.Divagar Mohandass
This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13122 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Disable unused devices.Divagar Mohandass
This change will disable unused devices in device tree to improve boot performance. TEST=Build/Flash CB and boot to OS. verify Touch screen, Audio, WIFI and Track pad functionality. Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/300943 Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Gomathi Kumar <gomathi.kumar@intel.com> Reviewed-on: https://review.coreboot.org/13423 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27soc/braswell: Fix leakage on V1P8S railShobhit Srivastava
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27soc/braswell: Add macro NATIVE_INT_PU20KHannah Williams
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13054 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27intel/strago: Fix GPIO configHannah Williams
Fix GPIO config for this board: - SD card detect to GPI - SATA GPI to not used - GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination - I2C4 SDA and SCL from not used to Native Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13431 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEnHannah Williams
Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27drivers/intel/fsp1_1: Enable builds without MRC cacheLee Leahy
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27intel/sklrvp: Remove mainboardMartin Roth
The Intel Skylake RVP3 mainboard is not building, and according to Intel, there is no plan to continue working on it for coreboot. The intel/kunimitsu board is the Skylake reference design for coreboot.org. Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13469 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 13:46:21 +0000