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2015-04-22intel/broadwell: guard CHROMEOS support betterPatrick Georgi
Since CHROMEOS_VBNV_* are selected by mainboards, they may be active without CHROMEOS being selected. In this case, they should be a no-op. Change-Id: I3b84e2a919ffaa809d713e72e5e4df7a7575e6b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22coreboot: common stage cacheAaron Durbin
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22coreboot: tiered imdAaron Durbin
A tiered imd allows for both small and large allocations. The small allocations are packed into a large region. Utilizing a tiered imd reduces internal fragmentation within the imd. Change-Id: I0bcd6473aacbc714844815b24d77cb5c542abdd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8623 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22coreboot: add imd libraryAaron Durbin
The imd (internal memory database) library provides a way to track memory regions by assigning ids to each region. The implementation is a direct descendant of dynamic cbmem. The intent is to replace the existing mechanisms which do similar things: dynamic cbmem, stage cache, etc. Differences between dynamic cbmem and imd: - All structures/objects are relative to one another. There are no absolute pointers serialized to memory. - Allow limiting the size of the idm. i.e. provide a maximum memory usage. - Allow setting the size of the root structure which allows control of the number of allocations to track. Change-Id: Id7438cff80d396a594d6a7330d09b45bb4fedf2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8621 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22chromeos: fix some compilation issuesAaron Durbin
This fixes some compilation issues observed with CONFIG_CHROMEOS. Nothing within the vbootX subdirectories is functional yet, but a partial compilation within the chromeos direction works now. Notable fixes: duplicate definitions and missing prototypes. Change-Id: I53c7b6dcf06b8bcf41a8555094b48968c0740026 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9936 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22chromeos: make functions visible with CONFIG_CHROMEOSPatrick Georgi
They were keyed to VBOOT_VERIFY_FIRMWARE which made them invisible under some circumstances. Change-Id: I61c56b4d245351fae0ec14f80bcd17ba93184651 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9956 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22elog: use CONFIG_RTCPatrick Georgi
When RTC is not selected, return all 0. Change-Id: I892a9489fc1d82fb8e61cf02666f797dc6412e05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22rtc: add config flag to denote rtc API availabilityPatrick Georgi
RTC drivers now select RTC, so that code which depends on them can implement fallback behavior for systems that lack the hardware or driver. Change-Id: I0f5a15d643b0c45c511f1151a98e071b4155fb5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22chromeos: Drop {developer,recovery}_mode_enabledPatrick Georgi
They were already moved to src/lib/bootmode.c in commit 5687fc9 Declare recovery and developer modes outside ChromeOS Change-Id: Ia27a0c79baa364ce3779a8a699e9246d26d02ecb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22nvidia/tegra132: Add spi_crop_chunk()Patrick Georgi
Missed during upstreaming Change-Id: Ifef4bb8a097a71244bdb648840cd64a812673107 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9950 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22google/*: Add MAINBOARD_HAS_CHROMEOS where appropriatePatrick Georgi
Some recently upstreamed boards are missing this flag Change-Id: I89d73970f23eed6ea127e620c38f9687b2f5b048 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9949 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22vboot2: CFLAGS_* doesn't contain preprocessor flags anymorePatrick Georgi
The preprocessor flags that are manipulated in that line are managed exclusively in CPPFLAGS since commit 58f73a69. Change-Id: I2263401a292b4f7435659b24cf4f695a927015ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9948 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22qemu-armv7: fix cbfs media implementationAaron Durbin
When using qemu-armv7 to load coreboot.rom with the -kernel flag the rom is offset by 0x10000. Therefore only allow mappings within 0x10000 and 0x10000 + CONFIG_ROM_SIZE. TEST= QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 \ -m 1024M -nographic \ -kernel coreboot-builds/emulation_qemu-armv7/coreboot.rom Change-Id: Ifec5761a7d54685f664c54efaa31949b8cc94bad Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9935 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22coreboot: add a place to choose romstage loaderAaron Durbin
Instead of always loading romstage from cbfs provide a way, similar to ramstage and payload, for other program loaders to intervene. For now, only the cbfs loader is consulted. TEST=Booted to end of ramstage on qemu-armv7 Change-Id: I87c3e2e566d7a0723e775aa427de58af745ecdd5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9934 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22kontron/986lcd-m: update vendor URLPatrick Georgi
Change-Id: Ia43291d0d41e565f2442b625387f3ffde9a98d32 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9947 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22kontron/986lcd-m: Add release yearPatrick Georgi
Change-Id: Ie49e235b81ca0cd7aff05ceed522d9df1d5403b0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9946 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22vboot: route all resets through a single functionVadim Bendebury
It is necessary to trigger console buffer contents dump on reset. Let's make sure all vboot resets are routed through the same function. BRANCH=none BUG=chromium:475347 TEST=built and booted storm Change-Id: I0d8580fb65417ba4b06dfae763dd6455afc8fc26 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9788e2043cb1bd5df7e30574f7df4de4f25caa0d Original-Change-Id: Iafca416700c51a0546249438ca583a415a1ca944 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265292 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9931 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Enable DDR auto self-refreshIcarus Chau
Enable auto entry and auto exit self-refresh. Configure entry idle time to 16x long count sequences. Where a long count sequence is 1024 cycles. The idle entry configuration is based on 32x of the DLL lock time (512 cycles). A conservative setting to help minimize self-refresh enter/exit thrashing. BUG=chrome-os-partner:36456 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR, print on console: sdram initialization is completed. test ddr start from 0x60000000 to 0x80000000 ... test ddr end: fail=0 Translation table is @ 02004000 Mapping address range [0x00000000:0x00000000) as uncached Change-Id: Ibad220429fd52ead2933db03bec1a555f9385e53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3768f82ca268fb854f8c4753916518a1efdf887d Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212125 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Change-Id: Icac1e12745d048b32e1804a546f6b49c8b5953c0 Original-Reviewed-on: https://chromium-review.googlesource.com/265862 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add specific controller initialization to corebootCorneliu Doban
BUG=chrome-os-partner:37533,chrome-os-partner:35814 BRANCH=broadcom-firmware TEST=bootblock initialize Cygnus HW successfully Change-Id: I93b97d7b26f6bacd8fab3d6bc52ec52e92e91a43 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8679570c6607ed6964f46df618fe8d0d22fcb2c0 Original-Reviewed-on: https://chrome-internal-review.googlesource.com/211695 Original-Tested-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Corneliu Doban <cdoban@broadcom.com> Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Change-Id: I62d354bce71aba8d5074f5385616a1265bd604df Original-Reviewed-on: https://chromium-review.googlesource.com/265861 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9929 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_rialto: support the developer key GPIOJonathan Dixon
Currently (EVT) this is a pullup resistor on the board (i.e. always in dev mode). Future builds it will be pull down and require servo or HW modification to control. Either way, this change means the FW should acknowledge it. BUG=chrome-os-partner:38663 TEST=Manually verified that servo devmode switch toggles this GPIO. requires FW signing to verify GPIO is observed and dev mode active. BRANCH=none Change-Id: Ib05216992abc5f6175fe7395471bd379f185b61f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 702c8d222a3d19d6b8db89d122dcdf594c85da99 Original-Change-Id: I1d0f31819b9f7a1ab63deac52bcaf0b996499b0c Original-Reviewed-on: https://chromium-review.googlesource.com/263529 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Jonathan Dixon <joth@chromium.org> Original-Commit-Queue: Jonathan Dixon <joth@chromium.org> Reviewed-on: http://review.coreboot.org/9928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22armv8/secmon: Disable and Enable GIC in PSCI pathFurquan Shaikh
Disable and enable GIC before switching off a CPU and after bringing it up back respectively. BUG=None BRANCH=None TEST=Compiles successfully and psci commands work for ryu. Change-Id: Ib43af60e994e3d072e897a59595775d0b2dcef83 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5271d731f0a569583c2b32ef6726dadbfa846d3 Original-Change-Id: I672945fcb0ff416008a1aad5ed625cfa91bb9cbd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265623 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9926 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-22t132: Add gic.c to secmonFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for ryu. Change-Id: Iaff771cdd1c8b6a7447e1e86aa35ea3ed40b17ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2856d3d4f4ab4e56259d36769d9cbb0ec9642951 Original-Change-Id: I702d7c6fa70b1af02c16b874f9de22c6b04a9100 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265624 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9927 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22armv8/secmon: Correct PSCI function idsFurquan Shaikh
PSCI_CPU_OFF is SMC32 call, there is not SMC64 version. Register SMC32 and SMC64 types of PSCI calls. BUG=None BRANCH=None TEST=Compiles successfully and CPU off works fine with PSCI command. Change-Id: I8df2eabfff52924625426b3607720c5219d38b58 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9228c07f9d9a4dd6325afb1f64b41b9b8711b146 Original-Change-Id: I2f387291893c1acf40bb6aa26f3d2ee8d5d843ea Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265622 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9925 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22armv8/secmon: Correct names for SMC macrosFurquan Shaikh
We support SMC32 calls from AARCH64, however we do not support SMC32 calls from AARCH32. Reflect this policy in the code by using appropriate names for exception type check in SMC handler. BUG=None BRANCH=None TEST=Compiles successfully and able to turn CPU1 on and off using psci commands. Change-Id: Ifc3c9e2fe0c4e6e395f2647769a2d07f5f41f57f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbaf712c2c45273a9eb0b0808a0d4d0630023fdd Original-Change-Id: I133b2c0bbc4968401a028382532bd051d6298802 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265621 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: save and restore cntfrq for secondary cpusJimmy Huang
CNTFRQ_EL0 can only be set in highest implemented exception level. Save and restore CNTFRQ_EL0 for secondary cpus in coreboot. This patch fix the error below: SANITY CHECK: Unexpected variation in cntfrq. Boot CPU: 0x00000000c65d40, CPU1: 0x00000000000000 BRANCH=none BUG=none TEST=boot to kernel on oak board and check secondary cpu's cntfrq. confirmed cpu1's cntfrq is same as boot cpu's. Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c Original-Reviewed-on: https://chromium-review.googlesource.com/264914 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot: add mocked secdataDaisuke Nojiri
This patch allows a board without a secdata storage (typically TPM) to pass the verification stage if recovery path is taken. It's useful for bringup when the actual board is not ready. BUG=none BRANCH=none TEST=booted the kernel from a usb stick on a cygnus reference board Change-Id: I5ab97d1198057d102a1708338d71c606fe106c75 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5d45acee31fd5b7bfe7444f12e3622bae49fc329 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212418 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Iddd9af19a2b6428704254af0c17b642e7a976fb8 Original-Reviewed-on: https://chromium-review.googlesource.com/265046 Reviewed-on: http://review.coreboot.org/9919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add usb phy driverDaisuke Nojiri
The code originates from https://github.com/Broadcom/cygnus-linux/commit/d0752a61273decb16db0fe8d09291f9cc326ed24. BUG=chrome-os-partner:37439 BRANCH=purin TEST=booted kernel from a usb stick on the ref board Change-Id: I51ecf4e1d6890e4286402c26721f4d063ab04711 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fac506e758cb63a947bbdcfbddf9b8edecf7cd2f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/202386 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I027affea293af8744c997a2ed3dec741977bd328 Original-Reviewed-on: https://chromium-review.googlesource.com/264560 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: DDR reads return to controller with no bubblesIonela Voinescu
When the PHY is compiled to run in HDR(half data rate), then either NOBUB or FXDAT must be set to 1 in the DDR system general configuration register. NOBUB specifies that reads should be returned to the controller with no bubbles and this is felt preferable to the fixed latency option (FXDAT). Both of them inrease read latency. BRANCH=none BUG=chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly Change-Id: Iee530ba5bb0acc889fba447dc2ee5cb965ba6926 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7944b4af45d9504098f8b4af44d0f5abafea42c Original-Change-Id: I9ced76bd670fc4efa7441d57e15f97871b046ae9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264341 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9917 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: DDR row/bank/column mappingIonela Voinescu
The DRAM configuration register, apart from holding the device density and width also has a rudimentary address mapping scheme. Currently this is set to the default Bank/Row/Column. This means that the memory is segmented into 8 chunks, each with a page detector. If all the activity is in one section of memory then the other 7 page detectors could be idle. Changing this to Row/Bank/Column would concatenate the page detectors meaning that all 8 could be used by a single initiator. This may not gain anything in a synthetic bandwidth test but could yield extra performance in a real world application or benchmark. BRANCH=none BUG=chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly; all access to DDR works properly in Coreboot ramstage, Depthcharge and Linux; no performance tests were ran so far. Change-Id: I22d86bf3b679ed63884d7436d9d7bbaf1726f640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e852ed42afcdc2062a0037144bab723227cb1f1f Original-Change-Id: If90b0cf5ce86db5e3d6d362873d22d4269e3a49f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264340 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9916 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: add arm64_arch_timer_init functionJoseph Lo
Add arm64_arch_timer_init function which should be called per CPU for setting up the cntfrq register of arch timer. During the Linux kernel bring up time, it will check the cntfrq register per CPU and should be the same with the boot CPU. BRANCH=none BUG=none TEST=bring up 4 cores in Linux kernel without warning message of cntfrq register value Change-Id: I9cb33a54c2c8f9115bbe545a2338ca8e249b8db6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 253cd3c68bb4513ae2033c12c2f070ee391e5a13 Original-Change-Id: I71068dbdd00a719145410ef6ec466f001ae837ad Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264244 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9915 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add secimage and sign bootblockDaisuke Nojiri
secimage is a tool which adds a header and signature to the binary first loaded by the soc. ARM core frequency is set to 1 Ghz. BUG=chrome-os-partner:36421 BRANCH=broadcom-firmware TEST=booted b0 board Change-Id: Ia08600d45c47ee4f08d253980036916e44b0044a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36284d1b242c26b0b5aac2894f7ed1790da1ef15 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/197155 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Iaddd24006b368c8f37e075cb51e151e985029f3b Original-Reviewed-on: https://chromium-review.googlesource.com/264417 Reviewed-on: http://review.coreboot.org/9914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22nvidia/tegra*: check bus number for i2c driver APIsYen Lin
BRANCH=None BUG=None TEST=emerge-foster coreboot Change-Id: I383d2b5f269ed348065a9f270f80514a2ff45742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fba6973c304e1612a9869c2e78a08650b6e5fe66 Original-Change-Id: I6d5d0098db8dbfb21529bf112a04b97779a0f381 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264027 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arch/armv7: Add API to disable MMU pages.Deepa Dinamani
Disables 4K regions in the MMU table. Assumes that the region is already accounted for by the first level page table entry. BRANCH=storm BUG=chrome-os-partner:24786 TEST=verified mmu.pagetable.list output for Storm: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--00000FFF| | | | | | | | | C:00001000--000FFFFF| A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:00100000--29FFFFFF| A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A000000--2A05FFFF| A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:2A060000--2A0FFFFF| A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A100000--3FFFFFFF| A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--59FFFFFF| A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:5A000000--5A1FFFFF| A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:5A200000--7FFFFFFF| A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:80000000--FFFFFFFF| | | | | | | | | Change-Id: Ib603da91966cc4c70ea9d5fee04f1e9890d0bb93 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67db80e6476d8ed35f0a9d1e0d3ca03612b9d9be Original-Change-Id: I6b149c7edbd975231b783cc53ddb63cf2e94052c Original-Signed-off-by: Vikas Das <vdas@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/253800 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org> Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org> Reviewed-on: http://review.coreboot.org/9912 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: Fix operator precedence error in LPDDR initJulius Werner
Upstream coreboot regularly runs Coverity over the code base. Turns out that's a good idea since it's really easy to screw yourself over with a missing parenthesis and some unfortunately deceptive line breaking. This patch fixes a bug in LPDDR3 initialization due to an incorrect operator precedence assumption ( ?: does not bind stronger than | ). In effect, instead of setting MR11[1:0] to 0b11 or 0b00 based on ODT, we're unconditionally setting MR0[1:0] to 0b11. Thankfully, MR0[1:0] seems to contain read-only bits so this might have not been a problem when ODT is off (which is currently true for all LPDDR boards). Also adding a redundant LPDDR_OP() around the 0 to make the intent clearer and changing 3 and 0 to 0x3 and 0x0 to make it more obvious that these are bit masks (right?). BRANCH=veyron BUG=None TEST=Running reboot loop on a Minnie, looks good so far... Change-Id: I06464aaa57e693b1973846a5771162244f7a1c57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan Original-Commit-Id: 5bd9eba39fb7b0f940fead963bbc1878b031b2cb Original-Change-Id: I701ce059472078b5de09a45dd31f54b65a51e641 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/264135 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jinkun Hong <jinkun.hong@rock-chips.com> Original-Tested-by: Jinkun Hong <jinkun.hong@rock-chips.com> Reviewed-on: http://review.coreboot.org/9911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Add variant MEC IOShawn Nematbakhsh
MEC cannot access memmap-range data directly though LPC and instead must access through its EMI unit. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on glower. BRANCH=None Change-Id: If98d425014a894ddeafad4268f92af5860878522 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263611 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Read / write IO ports through common functionsShawn Nematbakhsh
Rather than calling inb + outb directly, access the ports through common functions. This is in preparation for alternative access modes required by certain new embedded controllers. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Verify system boots cleanly in normal mode. BRANCH=None Change-Id: I98783ff67a37d970019683bb589825bc5d68c033 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25afa3f95183d8cf2e9a35272c77e92fbc6ee030 Original-Change-Id: Ic9d8f7f5c5d392212e39db28ebceea461d46f796 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263571 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Implement I2C driverAnatol Pomazau
BUG=chrome-os-partner:35810 BRANCH=purin TEST=Enable I2C1, reset devboard codec, read a register. Here is the code that demonstrates how I2C works: i2c_init(1, 100*KHz); mdelay(50); int rc = i2c_writeb(1, 0x18, 1, 0x80); // reset codec printk(BIOS_INFO, "I2C reset rc=%d\n", rc); mdelay(50); uint8_t data = 0; rc = i2c_readb(1, 0x18, 43, &data); printk(BIOS_INFO, "I2C read rc=%d data=%x\n", rc, data); // data == 0x80 Change-Id: I0d202f8b0375b5ccd9f71b23fb0cadd5a70ae779 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bbe9afe3dccd104f39c2c286d3765a28ea20141 Original-Signed-off-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/195706 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Commit-Queue: Anatol Pomazau <anatol@google.com> Original-Tested-by: Anatol Pomazau <anatol@google.com> Original-Change-Id: I178acef9de18fa854983294edcd2c05886795e2a Original-Reviewed-on: https://chromium-review.googlesource.com/263496 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9908 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Enable gpio on romstageIcarus Chau
BUG=chrome-os-partner:35936 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_GPIO_TEST, print on console: Start gpio test... [gpio_crmu] gpio:0 set input [gpio_crmu] gpio:0 set pullup:0 GPIO get 170=0 gpio request enable pin=64 offset=0x1c .... GPIO set 69=1 [gpio_asiu] gpio:45 set, value:0 GPIO set 69=0 Gpio test completed... Additional test: Measure on GPIO 69 to confirm the voltage change. Apply voltage on AON_GPIO0 to check reading. Change-Id: I634cffccc7f0fa198317a92e3f1670ae6828892e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4784e5d88b9f7acb70bd6f6b12b1096f092f34b8 Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/204537 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Ia4f833be80d7844c2d014c9ffcf587d385e7766c Original-Reviewed-on: https://chromium-review.googlesource.com/263495 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22switch mainboards over to use BOARD_ID_AUTOStefan Reinauer
This patch switches the mainboards with board id straps to use BOARD_ID_AUTO instead of BOARD_ID_SUPPORT. On urara, which does not have those straps, the option is removed. (And re-added for urara derivatives through setting the config option BOARD_ID_MANUAL BRANCH=none BUG=chrome-os-partner:37593 TEST=emerg-nyan_big coreboot, emerge-urara coreboot, emerge-buranku coreboot Change-Id: I5ac4024c6f1f9b9d7a5179d88722c69b23b82bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 22a470698f9c9ed275aa8150a5bb8d8cf368b050 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Change-Id: I48c291ad6f255a28c833bebc2638bfafa2782e74 Original-Reviewed-on: https://chromium-review.googlesource.com/262935 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22build system: add manual board id supportStefan Reinauer
This patch adds manual board id support to coreboot and selects manual board ids vs automatic (ie strap based) where appropriate in the mainboards. CQ-DEPEND=CL:262935 BRANCH=none BUG=chrome-os-partner:37593 TEST=emerge-urara coreboot, see no board_id file emerge-buranku coreboot, see board_id file Change-Id: Ia04e5498a01f35c5418698ecaf3197f56415e789 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3bdb1fa092005be24de9fc68998053982648da85 Original-Change-Id: I4f0820233a485bf92598a739b81be2076d4e6ae7 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262745 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: Add arch_program_segment_loaded call to arm64Furquan Shaikh
arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. BUG=chrome-os-partner:38231 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: Ic6fcc7e5e0cccbab317950f8abab0c494041d19a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 284e3784854f764159b64286cea366c66b6bce2c Original-Change-Id: I5c35b9aa2ae9b5c1f2fcdef40ffb1cde7f49cc1a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263327 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22libpayload: provide icache_invalidate_all() on ARM64Furquan Shaikh
In order to not duplicate the instruction cache invalidation sequence provide a common routine to perform the necessary actions. Also, use it in the appropriate places. BUG=chrome-os-partner:38231 BRANCH=None TEST=Compiles successfully for smaug and boots kernel Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529 Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263326 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9903 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22libpayload: Correct shareability mmu configuration on ARM64Furquan Shaikh
BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and boots kernel Change-Id: I6e1e841d84d1a73e5c726143aeba76af933e81a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59861a2700407b9e6a6209fbc45543c127b50b4b Original-Change-Id: I256d07a41bec83037f2b61a9350f903119d8c101 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263325 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22device: Add class and subclass name supportLee Leahy
Add support to display class and subclass names for PCI devices. BRANCH=none BUG=None TEST=Build and run on strago/cyan. Change-Id: I5136fae45b8a1cd02541f233d29a246cdfcd8331 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7c9b0d7201b09a06ea32f0db84187d15f767c80 Original-Change-Id: Ibf2ee89dd84040ca6ab0e52857a69f7ed0c28f37 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9901 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22Kconfig: Don't select GENERIC_GPIO_LIB in BOARD_ID_SUPPORTStefan Reinauer
The code guarded by BOARD_ID_SUPPORT does not use this library. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BRANCH=none BUG=none TEST=emerge-storm coreboot succeeds in building an image. Change-Id: If8c5c326265441f0c10999e3882706432139fd89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f49b89e0b03f482a30dc652e5956494fb994cc70 Original-Change-Id: Ie2cd2cd049fdb20fa5cc368bee08babd3f7a551c Original-Reviewed-on: https://chromium-review.googlesource.com/262744 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer
BOARD_ID functionality is not what requires the GPIO lib, but it is the mainboard specific implementations that do. The option essentially says whether the SoC provides <soc/gpio.h> (with the interface required by the common GPIO code). Right now, x86 and Samsung's Exynos SOCs don't have support for this interface. So this should be selected by the SOC, not by BOARD_ID_SUPPORT. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=emerge-storm coreboot still successfully compiled an image Change-Id: I0ce2bd7ce023f22791d31a6245833b61135504b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0dd4dea521372194eedf11b077d95fd3b15ad9f7 Original-Change-Id: I3dea6c2fb42a23fcb9d384c3bbfa7fc8e217be2d Original-Reviewed-on: https://chromium-review.googlesource.com/262743 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: Correct shareability option for normal memoryFurquan Shaikh
In order to allow proper working of caches, set the correct shareability option for normal memory. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully for foster and SMP works. Change-Id: I5462cb0a2ff94a854f71f58709d7b2e8297ccc44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e092916780716ac80c3608c1bd8ca2901fbb3bd1 Original-Change-Id: Idd3c096a004d76a8fd75df2a884fcb97130d0006 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: retrieve network device information from VPDVadim Bendebury
Invoke the function which copies MAC addresses from VPD into the coreboot table and calibration data into CBMEM. BRANCH=none BUG=chrome-os-partner:36584 TEST=with the rest of the patches applied observed that the MAC addresses from VPD get copied into the appropriate kernel device tree nodes. Change-Id: I68e2b73520853ef2d3249ca12ee87669fd01f442 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f935098c50e2df345748d3b71cee2152acd422 Original-Change-Id: I6e1483d33480d13380ade2dddae6c92fd3f1f881 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262844 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: process WiFi MACs along with ethernet MACsVadim Bendebury
coreboot is expected to read all MAC addresses from the VPD and put them in the coreboot table entry, depthcharge is expected to associate different MAC addresses with different kernel device tree nodes. This patch adds processing of wifi_macX keys. The order of MAC addresses in the coreboot table is such that the wifi_macX entries follow ethrnet_macX entries, ordered by X. BRANCH=none BUG=chrome-os-partner:36584 TEST=with the rest patches applied verified the contents of the kernel device tree on an urara board. Change-Id: I6523e168d2fea201a4956bc2a2d605b07ddac452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36c12ee1d3ce9d2797902f0e098651067c2283ed Original-Change-Id: Ib87e4815243f34ab258325839cbc12d16120bf89 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262843 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: decode calibration data into binaryVadim Bendebury
The preferred way of communicating WiFi calibration data to the kernel is binary blob. But this data is stored in the VPD, and must be in ASCII, so it is encoded using base64. With the recent addition of the bas64 decoder it is possible to convert the VPD representation to the form preferred by the kernel. BRANCH=none BUG=chromium:450169 TEST=with the rest of the patches applied verified that on both storm and urara the device tree contains the required binary data. Change-Id: I89da94bb425767eedc5e2d576e507663afad65ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c2ae38ded24394e0640b5d077e2231cf956397c5 Original-Change-Id: If8a7d0883ea8bb21a13bf203b25ee9f8a08903a9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262842 Reviewed-on: http://review.coreboot.org/9895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: increase RAM CBFS cache sizeVadim Bendebury
CBFS cache use is very close to the limit, does not allow to read much more from CBFS. BRANCH=none BUG=chrome-os-partner:36586 TEST=the upcoming patches do not fail due to the lack of room in CBFS cache any more Change-Id: I8e784891e59ca284b3bd82557c2114a2f450d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c94d55c8042db81c1eb0c10d5f24883e00cdc19a Original-Change-Id: Ic09dbd5b4a0e165ccef396ff8a9e21b12c49b705 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263268 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Access ID + flags through ACPI I/O portsShawn Nematbakhsh
If CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is set, access to memmap data should go through the ACPI CMD / DATA ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly. BRANCH=None Change-Id: I9d19704df259f5a25e04a9b07b23968e93fe6302 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0b59b040a7889d2d1bd6eeaf57dd960bd29927d Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I405e28828457a1fd83a7ece7192a7e7d0a37be95 Original-Reviewed-on: https://chromium-review.googlesource.com/262932 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22lib: add base64 decoderVadim Bendebury
It became necessary to decode base64 data retrieved from VPD and convert it into binary for inclusion in the device tree. The patch introduces the decoder function based on the description found in http://en.wikipedia.org/wiki/Base64. An open source implementation from http://base64.sourceforge.net was considered, in the end the only thing borrowed from it is the table to translate base64 ascii characters into numbers in 0..63 range. BRANCH=none BUG=chromium:450169 TEST=created a test harness generating random contents of random size (in 8 to 32766 bytes range), then converting the contents into base64 using the Linux utility, and then converting it back to binary using this function and comparing the results. It succeeded 1700 iterations before it was stopped. Change-Id: I502f2c9494c99ba95ece37a7220c0c70c4755be2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6609f76e1559d3cdd402276055c99e0de7da27c8 Original-Change-Id: I5ed68af3a4daead50c44ae0f0c63d836f4b66851 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262945 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22libpayload: fix a mips memmove() bugVadim Bendebury
size_t is an unsigned type and as such is a bad choice for a counting down loop counter. BRANCH=all BUG=none TEST=editing cli command line does not cause hangs any more Change-Id: I0502553b5e2143052345edeb205a01558fccd9b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c171f739497fcd26589976676ab94b23cd7ee8b Original-Change-Id: I4aa38379ac356114fc91a32cced2fa45a00a09d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262714 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: Increase SPI flash frequency to 24.75MHzJulius Werner
This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288 (veyron) boards. This increases flash read speeds (and thereby decreases boot time) significantly, but we don't seem to get any more increases by going even higher. We have also seen occasional read failures at higher speeds in certain configurations, so this frequency seems to be the best option. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted on Jerry with Servo attached. Change-Id: I9bdb62eff169fe2be33558caafe9891668589372 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262645 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: use board ID information to set up hardwareIonela Voinescu
The hardware initialization is now split in basic initialization (MIPS and system PLL, system clock, SPIM, UART), and initialization of other hardware blocks (USB, I2C, ETH). The second part uses board ID information to select setup that is board specific (currently only I2C interface is selected through board ID). BRANCH=none BUG=chrome-os-partner:37593 TEST=tested on bring up board for both Urara and Concerto; to simulate the use of Concerto (I2C3) DIP SW17 was set to 0. it works with default settings on Urara Change-Id: Ic5bbf28ab42545a4fb2aa6fd30592a02ecc15cb5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2b3db2e7f9fa898214f974ca34ea427196d2e4e Original-Change-Id: Iac9a082ad84444af1d9d9785a2d0cc3205140d15 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/257401 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: Fix SPI clock divisor calculationJulius Werner
The code to calculate the RK3288 SPI controller's internal clock divisor is wrong: it assumes that the divisor register was an "n-1" divisor when it actually isn't (due to some misleading kernel code that was copied in here). This means that all SPI clocks are currently running lower than expected. This patch fixes the calculation and changes all callers such that the effective speeds stay the same. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted Jerry with and without the patch, dumping the divisor for flash and EC clocks. Made sure it stays the same. Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262269 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Support accessing memmap data over port 62/66Shawn Nematbakhsh
Some platforms cannot access the 900h-9ffh region over the LPC bus, so it's necessary to access memmap data over the ACPI cmd / data ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d Original-Reviewed-on: https://chromium-review.googlesource.com/262314 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Update ec_commands.h from EC repositoryShawn Nematbakhsh
BUG=chrome-os-partner:38224 TEST=Compile for Samus BRANCH=None Change-Id: I9bb7ed100b876cbd50d39f5c5ad599e4bd7be6b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca8fbf8ed91d95486f0c8db680e8ceabca597a3a Original-Change-Id: I250fcce67f6103cf3037b416b8e74dd4a2cea780 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262313 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arch/arm64: allow floating-point registers accessYen Lin
BRANCH=None BUG=None TEST=build coreboot, make sure there are fmov instructions generated by the compiler, and boot to kernel Change-Id: Ia99c710be77d5baec7a743a726257ef3ec782635 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f770a436a0692c8e57a8c80860a180330b71e82c Original-Change-Id: Iab4ba979b483d19fe92b8a75d9b881a57985eed7 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262242 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/rush_ryu: add serialno from vpdStephen Barber
Add the serial number from VPD on ryu. BRANCH=none BUG=chrome-os-partner:37813 TEST=devicetree is populated with "compatible", "hardware", and "serialno" properties Change-Id: I1e84933a01a34028a062d31aad026f91c3bd29e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18cefb655651c9097ff7f2ef3cb735efbbe32370 Original-Change-Id: I14439c37df0fde7f2328c7caae1adf6a122e8f5f Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260646 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: populate coreboot table with serialnoStephen Barber
BRANCH=none BUG=chrome-os-partner:37813 TEST=devicetree is populated with with "compatible", "hardware", and "serialno" properties Change-Id: Ibe84aa05702d2a33456c6c33d15a4c7d4a6d45d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 61408d969f5d6e1e40f919b3defd5f1622391c9e Original-Change-Id: I02f360f4e5385042f56eb2b2f29072e393a24fc9 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259141 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9882 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22libpayload: cros: add serial number from coreboot tableStephen Barber
Add serial number to lib_sysinfo from coreboot table. BRANCH=none BUG=chrome-os-partner:37813 TEST=ryu boots and /proc/device-tree/firmware/android is populated with "compatible", "hardware", and "serialno" properties Change-Id: I565b332a16b177c51907ffab7976ebd7a665aaaf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5535119f5d499b04bdc178c3040241d2872c4e13 Original-Change-Id: Ie2e222780d1577689a1cbf76ae8514c74fc469f4 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259140 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot2: provide config option to clear dev mode state on recoveryVadim Bendebury
On embedded devices with limited input capabilities it is necessary to clear the developer mode condition when entering recovery. The new configuration option will enable such behavior using the new vboot2 flag. CQ-DEPEND=CL:261630 BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applies observed desired behavior on SP5 Change-Id: I99c3d1330bea9980a2af3b9fd99e29ab96f2cf07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c0a6315d6b4ede8d43e736ee6c82f1023f4716d Original-Change-Id: I8e4a521e574b53a670daf692f7b45dc21635f272 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261620 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22libpayload: usb: fix compilation error in debug fuctionHarry Pan
Since CL:170664, all SC_SPEED_XXX renamed to SC_SPEED1_XXX. There is one missing in xhci_dump_slotctx() function which makes compilation error. BUG=none TEST=enable USB_DEBUG and XHCI_DUMPS macros in xhci_private.h; then emerge-auron libpayload Change-Id: Ib96805cb7fc1cad17b205277539fb2120632f6f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ca0174e93ad131309ad07187c95c1e84c7d4fc5 Original-Change-Id: Id056b4684831a5717e87969e95ab17f11db29696 Original-Reviewed-on: https://chromium-review.googlesource.com/261414 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Harry Pan <harry.pan@intel.com> Original-Tested-by: Harry Pan <harry.pan@intel.com> Reviewed-on: http://review.coreboot.org/9877 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot2: ignore physical dev switch in case virtual mode is configuredVadim Bendebury
It is better to explicitly disable the call to read the physical switch setting than to leave it up to implementation. In fact no implementation would be even required. BRANCH=none BUG=none TEST=verified that storm works as expected Change-Id: I4b39827dba34ec0124960d0634e45d4554252d9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c9fd014f1bfec6570b20ed8fed16d14d7e4e11b9 Original-Change-Id: I5d6d223f0c684e105a5e3d0b407e0fb181c7a7df Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261588 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: add ELPIDA F8132A3MA and FA232A2MA sdramjinkun.hong
BRANCH=None TEST=Boot from veyron BUG=None Change-Id: Ie154d233f144bde2625cf069b9b754e9518a1768 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ddd03f8757b5122f6ca87baffdf95c46e356e53 Original-Change-Id: I725cfb04ff46f7e6493e0e12a464c45b1362bc1a Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/261083 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9874 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: provide icache_invalidate_all()Aaron Durbin
In order to not duplicate the instruction cache invalidation sequence provide a common routine to perform the necessary actions. Also, use it in the appropriate places. BUG=None BRANCH=None TEST=Built on ryu. Change-Id: I29ea2371d034c0193949ebb10beb840e7215281a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5ab28b5d73c03adcdc0fd4e530b39a7a8989dae Original-Change-Id: I8d5f648c995534294e3222e2dc2091a075dd6beb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260949 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9871 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22elog: Eliminate CONFIG_ELOG_FULL_THRESHOLD and CONFIG_ELOG_SHRINK_SIZESol Boucher
These Kconfig options provided a level of configurability that is almost never necessary, so they are being moved into ordinary preprocessor defines in elog_internal.h. The new threshold to trigger shrinking is relative to the number of additional (maximum-size) events that can fit, and the new target post-shrink size is a percentage of the total ELOG area size. BUG=chromium:467820 TEST=Add loop at the end of elog_init() that fills the ELOG area to just below full_threshold with dummy events. Observe successful shrinkage when the next event is logged. BRANCH=None Change-Id: I414c4955a2d819d112ae4f0c7d3571576f732336 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce439361e3954a2bf5186292f96936329171cf56 Original-Change-Id: I926097f86262888dcdd47d73fba474bb2e19856a Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260501 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9869 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: update sdram-ddr3-samsung-4GB.incjinkun.hong
The old parameters are wrong. K4B8G1646Q: rank = 2, row = 15 is right. BUG=None TEST=Boot from veyron BRANCH=None Change-Id: I41848c158f3ea028035cc8c0d969a4a449390a54 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 601ba06c636ff0f0779e6ef9357b53060a1ec19b Original-Change-Id: I5bc6798890b3ba0f5134d048ae6bbf2bfd696676 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260483 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Paul Ma <magf@bitland.com.cn> Reviewed-on: http://review.coreboot.org/9866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22Makefile: Disable implicit rulesJulius Werner
This patch disables implicit make rules (like %.o: %.c) from our build system, since we don't use them and they can cause unexpected results when there's a mistake in the Makefiles. BRANCH=None BUG=chromium:466469 TEST=emerge-falco coreboot fails with only this patch and succeeds with this and the $(src-to-obj) fix. Change-Id: I7478adaddbbeaa2226fd941ffacfce2577ba59ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c2543f25f7db61f93be96784eca3f4f65e3ffaa0 Original-Change-Id: Ia6a91f040ad4ef556cf7912cd82a73173dfec8cb Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259947 Original-Reviewed-by: Mike Frysinger <vapier@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: use bl_en instead lcd_bl to fill_lb_gpiohuang lin
in depthcharge we will use "backlight" gpio which in lb_gpio table to control backlight, we use lcd_bl before, but it will not meet the backlight power sequence, so we change it to bl_en. BUG=chrome-os-partner:37348 TEST=Boot from speedy, and backlight work well BRANCH=None Change-Id: I19e488c7d3f1fe5cb91f8a93fae6b848f58b36b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb594ce612e1cedeabced4531fbd954f3698da98 Original-Change-Id: Ib0dac7c48bce7d0b28ec287b32d8c5bad575893f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/259900 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot: when configured, pass the wipeout request to vbootVadim Bendebury
It has become necessary to be able to "factory reset" certain devices on firmware request. The vboot package has been modified to provide the necessary API, this patch introduces a configuration option and uses the API when enabled. CQ-DEPEND=CL:259857 BRANCH=storm BUG=chrome-os-partner:37219 TEST=with all the patches applied, on storm, holding the recovery button at startup for 10 seconds, causes 'crossystem wipeout_request' to report '1'. Change-Id: I5e57bc05af3753f451626021ba30c7726badb7b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f70e03e9a8c55bf3c45b075ae4fecfd25da4f446 Original-Change-Id: I4c2192da4fabfdef34d527e5b80d137634eb6987 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259843 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9862 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22Makefile: Avoid duplicate class suffixes in $(call src-to-obj)Julius Werner
The build system uses the $(src-to-obj) function in multiple places to figure out the corresponding output object file for a certan source file, most importantly when generating the rule to build it. Usually this is pretty simple, but some odd cases are a little tricky... such as the auto-generated intermediary C files containing an array definition generated from an ASL file. These files have already been compiled per stage, so they contain the stage as a suffix and reside in the build directory (e.g. build/.../dsdt.ramstage.c). The previous $(src-to-obj) implementation just blindly appends the stage again and turns this into build/.../dsdt.ramstage.ramstage.o. This isn't very useful, so to avoid confusion this patch makes it strip additional stage suffixes for those intermediary files. This also fixes a bug with the ASL postprocessor, which didn't take this double suffix into account: it added build/.../dsdt.ramstage.o to ramstage-objs which should've been build/.../dsdt.ramstage.ramstage.o. This only worked by accident because make compiled the file with its implicit %.o: %.c rule instead. BRANCH=none BUG=chromium:466469 TEST=emerge-falco coreboot with the new make 4.1. Also build Falco and Veyron_Jerry with make -r -R to make sure there are no other accidental uses of implicit rules in our build system. Change-Id: I4aeaa60add1ef4215cb6c0b222c3886395c7a045 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d9ea2e082eca1045409ea1f403082c97dedc70d8 Original-Change-Id: I951edbc9f653321a9084543a65009c6e9154d819 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259950 Original-Reviewed-by: Mike Frysinger <vapier@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9861 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22qualcomm/ipq806x: report versions of RPM and DDR init componentsVadim Bendebury
DDR init blob version string can be found at a fixed location in memory once the blob is loaded. Maximum size of the string is 48 bytes. The RPM RW version is defined in a 32 bit version stored at yet another fixed address once RPM RW has started. BRANCH=storm BUG=chrome-os-partner:30623 TEST=ran this command on the booted system: localhost ~ # egrep '(DDR|RPM)' /sys/firmware/log Loaded DDR init blob version 99ce41d@-AAABANAZA DDR initialized Starting RPM Started RPM version 1.0.128 localhost ~ # Change-Id: If3c3c8368845b978605ccfda7e09c21ae2e5ab9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 328c9c57cf93110bc0fdd267134d72e386d70834 Original-Change-Id: If411f6f7bca53ea20390b7e851cb3d120681eade Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/256738 Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com> Reviewed-on: http://review.coreboot.org/9860 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22qualcomm/ipq806x: add board id value for SP5Vadim Bendebury
SP5 whirlwind is the earliest hardware version equipped with the LED ring. BRANCH=storm BUG=chrome-os-partner:36059 TEST=none Change-Id: I4c90a75911350bafd8ccb8755b2491e9447f285b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3dfee90457295668a2b60d5a1e913caf52557877 Original-Change-Id: I6bffdcc47fe9c72796e3bac44d211f907538ef0b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258270 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9857 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: retrieve board ID from a CBFS fileVadim Bendebury
Concerto board does not have the means of detecting the identity of the device it is controlling. But it is very beneficial to be able to use the same firmware image on Concerto boards running different devices. The suggested solution is to keep the device identity as a string in a raw CBFS file called 'board_id'. With this patch coreboot maintains a table of possible board name strings and their matching board IDs. BRANCH=none BUG=chrome-os-partner:37593 TEST=verified that without the board id file addition the default Board ID of zero is used. Adding the file as follows: echo -n 'concerto' > /tmp/bid cbfstool /build/urara/firmware/image.serial.bin add -f /tmp/bid \ -t raw -n 'board_id' results in firmware reporting board ID setting of 1. board_id: failed to locate CBFS file board_id board_id: name urara, ID 0 Change-Id: I5a02192740dc94b1ea8090092cc325fe0ac42aa6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f41f9b07f155f0c719c36e0cd93081205624557e Original-Change-Id: I8341782005b101be78f5c9a6b375c8f73179c1ad Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/257170 Reviewed-on: http://review.coreboot.org/9856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add timestamps in pre-ram stagesDaisuke Nojiri
BUG=none BRANCH=broadcom-firmware TEST=timestamp table: 0501: 31858 0005: 106680 0503: 132098 0504: 135573 0006: 168656 0013: 168660 0014: 240487 0502: 240491 0001: 240515 0002: 247544 0003: 537158 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chrome-internal-review.googlesource.com/204758 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Tested-by: Daisuke Nojiri <dnojiri@google.com> Change-Id: I5b4608152e97d53e35d28aa7bed2bfd158409df9 Reviewed-on: https://chromium-review.googlesource.com/256418 Reviewed-on: http://review.coreboot.org/9855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/purin: add DMA coherent regionDaisuke Nojiri
BUG=none BRANCH=broadcom-firmware TEST=boot to depthcharge Change-Id: Id10437c12e219e07121395abd442d53b3b56c7be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f33e9218ca8df1d149761c09253c30837b607433 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/204757 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I93def9c326cc8b4fea69078987bddf09d9f2a797 Original-Reviewed-on: https://chromium-review.googlesource.com/256417 Reviewed-on: http://review.coreboot.org/9854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Initialize dram in romstage.Icarus Chau
BUG=chrome-os-partner:36456 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR, print on console: sdram initialization is completed. test ddr start from 0x60000000 to 0x80000000 ... test ddr end: fail=0 Translation table is @ 02004000 Mapping address range [0x00000000:0x00000000) as uncached Change-Id: I88dc2f0c504e2a152133edd442c3d776dd73d37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 376471751d6980f99bbe47faad193c79a05fa69f Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199775 Original-Commit-Queue: <ichau@broadcom.com> Original-Tested-by: <ichau@broadcom.com> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Change-Id: I47bc5d9ec147cc8bfbd893e8c0d7e5fc5e401771 Original-Reviewed-on: https://chromium-review.googlesource.com/256416 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadcom/cygnus: Fix missing writel->write32 transformationPatrick Georgi
cygnus' serial driver wasn't part of the tree when the big transformation was done, so follow up. Change-Id: Ic1a53bea9bcaf1e568b50b9c2ad7782e65e36328 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9852 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21libpayload: add timer driver for cygnusDaisuke Nojiri
BUG=chrome-os-partner:36011 BRANCH=broadcom-firmware TEST=measured 10 seconds in depthcharge: Starting depthcharge on purin... dpch: time 10 9 8 7 6 5 4 3 2 1 0 Change-Id: I0bcb01c255b19518bb8440111ac81f056c07ed69 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f5993bd400dd5d38e62d07bc8ce3513175e0d518 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200569 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Id83aae29cec6320d897e0b231d023a9ee885903e Original-Reviewed-on: https://chromium-review.googlesource.com/256415 Reviewed-on: http://review.coreboot.org/9850 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21cygnus: add QSPI driverCorneliu Doban
The driver uses the MSPI controller to read/write to/from SPI flash BUG=chrome-os-partner:35811 BRANCH=boradcom-firmware TEST=bootblock loads and executes verstage Change-Id: I34c7882170e4f89bee1b6001563c09b16dfea8ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8c3b156019df429e9d12728224ed4eec8436f415 Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199776 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Tested-by: Corneliu Doban <cdoban@broadcom.com> Original-Commit-Queue: Corneliu Doban <cdoban@broadcom.com> Original-Change-Id: Ice798ec76011ee47e13174b4c5534b0d0bc8b4ad Original-Reviewed-on: https://chromium-review.googlesource.com/256414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: add new SDRAM configuration with ram-code 1101bZhengShunQian
This add hynix-2GB SDRAM(H5TC4G63AFR-PBA), whose timing is the same as H5TC4G63CFR-PBA, to veyron boards. BUG=None BRANCH=veyron TEST=build on mighty and boot on mighty board with ram-id reworked Change-Id: I3ae5e65e60e18414cf4de6fbcc5bed736b1492de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b22029f9b05ebb9a775266a7e3aae38b50c1883a Original-Change-Id: If17fb002f2816990e1706833b37ac6be345e540b Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256307 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/9848 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu
The existing DDR setup configures the burst length to be 8. However the DDR controller can only be given sufficient data per clock to satisfy a burst length of 4, hence the bursts are only half populated. This results in a 50% drop of efficiency. Fix this by configuring the burst size to 4. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly BRANCH=none Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256305 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu
The DDR On Die Termination was incorrectly configured at 75R, where as the data sheet suggests for DDR2-800 it should be set to 50R. Correct this by adjusting the ODT setting in the EMR register. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly BRANCH=none Change-Id: I2f0242c422b1cb3d1f64ce3dd17b62fef5e7e155 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac081ac59c0dc3d16a7b540cd379fb870b6cfe40 Original-Change-Id: If7951812033c4e88f4be3c143fb49526eddba142 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9846 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: clean DDR2 initialization codeIonela Voinescu
The proper way to initialize DDR2 is for the PHY to automatically establish precise timing configuration through the training process. The alternative (used initially for testing) is no longer needed. This change determined the removal of some local variables as they ended up being used in one location only. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly. BRANCH=none Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e28f3ef9a22436bb0fa949df6f5a5c6a67002dfd Original-Change-Id: Ifb9c1bb6e0b71af72340381bd2349850d1b4af2d Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256303 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21cygnus: enable serial driver for depthchargeDaisuke Nojiri
BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=tested input and output by the cli in depthcharge Change-Id: Icd517a366a3fe5bdcf9e9aeb4284d7e4378ee3f2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 02c3b6c82d9d71beb19a0879591c754fa7685362 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200568 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I97144fc6f19969b8cf3872939c9c74efaef3604b Original-Reviewed-on: https://chromium-review.googlesource.com/256413 Reviewed-on: http://review.coreboot.org/9844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21storm: print uber-sbl informationVadim Bendebury
Process information reported by uber-sbl: print out its version and RPM and KRAIT log contents. BRANCH=storm BUG=chrome-os-partner:30623 TEST=rebooted a storm device, checked out /sys/firmware/log after booting up Chrome OS: localhost ~ # head -29 /sys/firmware/log | tail -15 Uber-sbl version: @vbendeb-AAABANAZA Section 0 log: 0 :00:SBL1, Start 0 :00:SBL-RO Krait 2623 :00:SBL-RO Krait 0 :00:BB 4666 :00:BB 0 :00:sbl1_hw_init, Start 6130 :00:sbl1_hw_init, Delta 0 :00:SBL1, End 15372:00:SBL1, Delta Section 1 log: 0 :00:SBL-RO Krait, Start 0 :00:SBL-RO Krait, End 336 :00:SBL-RO Krait, Delta localhost ~ # Change-Id: I524dbb49f676046a43bfba26b31b2834c8d2769c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dcabca6eb87dcead0c9c33749ed76ac939d843c1 Original-Change-Id: Ic037f936ff2d09b0346fb5239094e7928dfd7620 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/252830 Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9843 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21armv7: preserve bootblock invocation parameterVadim Bendebury
Some platforms may pass as a parameter the maskrom or vendor startup code information when calling the bootblock. Make sure the bootblock startup code saves this parameter for use by coreboot. As we don't want to touch memory before caches are initialized, save the passed in parameter in r10 for the duration of cache initialization. Added warning comments to help enforcing that cache initialization code does not touch r10. BRANCH=storm BUG=chrome-os-partner:30623 TEST=with the rest of the patches applied see the QCA uber-sbl report in the coreboot console output. Change-Id: Ic6a09e8c3cf13ac4f2d12ee91c7ab41bc9aa95da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e41584f769eb042604883275b0d0bdfbf5b0d358 Original-Change-Id: I517a79dc95040326f46f0b80ee4e74bdddde8bf4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255144 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9842 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21ipq808x: add uber sbl parameter definitionsVadim Bendebury
This describes the structure of the information passed through a pointer by uber-sbl to be processed by the coreboot bootblock. BRANCH=storm BUG=chrome-os-partner:30623 TEST=with the rest of the patches applied observed uber-sbl information added to the coreboot console log. Change-Id: If04c4ee0ccfda3df45bd22eb576aaa5b51f1c4b5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed39e2bcd793fd490416b407f627b5a9a86b8f78 Original-Change-Id: I1dffbf4559853a818e81ca5fdeff013cf008dd6a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21urara: I2C clock and MFIO setup function for all interfacesIonela Voinescu
The I2C MFIO setup function now supports all interfaces. Also, the API for the clock setup function changed to support all interfaces. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I6dfd1c4647335878402cabb2ae512d6e3737a433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8a7ffb54e3f5092c9844b9b502949d3cfc053d1 Original-Change-Id: Ibd67c07acf3d1d9c594faa8ced5ab56d9abb2e40 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256362 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: add clock setup for all I2C interfacesIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I02202585140beb818212c02800f6b7e4966a922a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256361 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
This patch removes quite a bit of code duplication between cpu_to_le32() and clrsetbits_le32() style macros on the different architectures. This also syncs those macros back up to the new write32(a, v) style IO accessor macros that are now used on ARM and ARM64. CQ-DEPEND=CL:254862 BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu, Storm and Urara. Booted on Jerry. Tried to compare binary images... unfortunately something about the new macro notation makes the compiler evaluate it more efficiently (not recalculating the address between the read and the write), so this was of limited value. Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254866 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Manually clean up the mess left by write32() transitionJulius Werner
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Change write32() argument order to match x86Julius Werner
This patch changes the argument order for the (now temporarily unused) write32() accessor macro (and equivalents for other lengths) from (value, address) to (address, value) in order to conform with the equivalent on x86. Also removes one remaining use of write32() on ARM that slipped through since coccinelle doesn't inspect header files. BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: Id5739b144f6a5cfd40958ea68510dcf0b89fbfa9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f02cae8b04f2042530bafc91346d11bb666aa42d Original-Change-Id: Ia91c2c19d8444e853a2fc12590a52c2b6447a1b9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Replace write32() and friends with writel()Julius Werner
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21romstage_handoff: Fix for changing CBMEM structureDuncan Laurie
Adding a new field to a CBMEM structure does not work if there are systems with older RO that do not have this new field as it means romstage did not prepare the field and ramstage is using it uninitialized. To deal with this instead of adding a new field split the existing s3_resume variable into bytes, using the first byte for the existing s3_resume variable (which is always just 0 or 1) and the second byte for the new varible, which will always be 0 for the old RO and can be set by new RO. BUG=chrome-os-partner:37108 BRANCH=samus TEST=manual testing on samus: 1) ensure that if vboot requests reboot after TPM setup that it still works and the reboot happens after reference code execution. 2) ensure that if RO is older without this change that it does not cause a continuous reboot if newer ramstage is added 3) test that suspend resume still works as expected Reviewed-on: https://chromium-review.googlesource.com/253550 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 1ccb7ee5fc6980ca0f26fa52b385d2cc52f396c9) Change-Id: I6e206b4a3b33b8a31d102d64bd37d34657cf49ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe85678ee788ff939bc8c084829a1b04232c4c6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: If69d0ff9cc3bf596eee8c3a8d6e04951820a26fe Original-Reviewed-on: https://chromium-review.googlesource.com/256114 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron_{brain,danger}: Specify vboot romstage and ramstage indicesDavid Hendricks
This applies the same hack to Danger and Brain as on Rialto which allows us to remove the EC-related sections from their respective flashmaps. BUG=none BRANCH=veyron CQ-DEPEND=CL:255669 TEST=built and booted on Brain w/ depthcharge and mosys changes, was able to read vbnv data from userspace Change-Id: I95715d59a21cd081ac4a3a2216576ede5620f1a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4de4273be9ac80ca77a34bc076d1f265fbb94e9f Original-Change-Id: I6c2041e8c17ab157599255a505aaef5e2447a241 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255780 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>