summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-11-05ARM: Use local versions of libgcc functions instead of linking against libgcc.Gabe Black
The flags used to compile libgcc may make it incompatible with the code it's linked against, and/or the hardware it's going to run on. Rather than try to tease the right libgcc from the compiler, lets just leave it out and use our own implementations of the necessary functions. Most of these implementations were taken from the Linux kernel, except for uldivmod.S which was taken from a CL originally written for U-Boot by Che-Liang Chiou in December of 2010. It was modified to not use the CLZ instruction on machines that don't have it, anything earlier than ARMv5. The top block was taken from an earlier version of the same CL which didn't use CLZ in that spot. The later block was written from scratch. BUG=None TEST=Built and booted into the bootblock on nyan. Ran a series of tests which divided and modded a 64 bit value by various 32 bit values which were powers of 2. Confirmed that this function was used and that the returned value was correct. Printed decimal and hex versions of some values and verified that they equaled each other. Built and booted on pit with serial enabled. BRANCH=None Original-Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/172401 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402) *** This second patch is cherry-picked and squashed again to *** pick up the libgcc changes that were skipped previously. arm: Move libgcc assembly macros to arch/asm.h libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. BUG=None TEST=Snow still boots. Original-Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182178 Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) *** Additional changes for stage specific builds Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3e48f34ebf6fbe20c3dd76ecbcbea7844e9466e Reviewed-on: http://review.coreboot.org/7322 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-05inteltool: Show more info on sandy/ivy.Vladimir Serbinenko
Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6692 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04i82801gx: Handle whole FADT in southbridge.Vladimir Serbinenko
Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7199 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04inteltool/sandybridge: Kill mch_registers codepath.Vladimir Serbinenko
It never worked. Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7324 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04abuild: fix cross compiler testPatrick Georgi
Actually abort if a cross compiler is missing, but also handle subarchitectures (currently: armv4 and armv7 for arm) properly. Change-Id: Idf37fb029178df6f2ac029466c66aaa2010bdbd2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7297 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04inteltool: Add support for Haswell ULT and Lynx Point LPDennis Wassenberg
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5 Reviewed-on: http://review.coreboot.org/7275 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-04amd/agesa/f16kb: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7302 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
Bring code inline to be consistent with the rest of coreboot. See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase, 'expressions that refer to functions get converted to pointers to those functions' Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7290 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04mainboard/dmp/vortex86ec: Unused variable in romstage.cEdward O'Callaghan
Change-Id: I9cc549b7862ee535928bd06b5fb4bd38bb67a992 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04superio/ite: Use common dispatch for pnp entry/exit functionsEdward O'Callaghan
We already have these implemented under superio/common, use those instead of this copy-paste syndrom. Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7310 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04build: fetch submodules as requiredPatrick Georgi
Also document the unusual git feature we employ for 3rdparty Change-Id: I1d1c986f9d1c4dd8db687d746dbdeb510679141a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7243 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04romstage: Pass .car.data as ignored section while adding romstageFurquan Shaikh
We don't want segment for .car.data section to be considered while elf_to_stage transformation is being done. Thus, use -S option for add-stage. Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/7305 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-04cbfstool: Add option to ignore section in add-stageFurquan Shaikh
Allow add-stage to have an optional parameter for ignoring any section. This is required to ensure proper operation of elf_to_stage in case of loadable segments with zero filesize. Change-Id: I49ad62c2a4260ab9cec173c80c0f16923fc66c79 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/7304 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04cbfstool: Convert cbfs-mkstage.c into pelfFurquan Shaikh
Change cbfs-mkstage to use parsed elf instead of calling elf_headers. That allows us to have access to the complete elf including the string table. Change-Id: Ie767d28bdf41af38d1df0bce54bc0ada45123136 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/7303 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-03AMD boards: constify romstage variablesPatrick Georgi
That takes them out of .data Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7313 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-03AGESA f12: Add "const" modifiersPatrick Georgi
Apply commit 283ba78415 to f12 (literally, plus one adaptation). Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7312 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-03Revert "gigabyte/ga-b75m-d3h: Add new Intel mainboard"Vladimir Serbinenko
Breaks abuild and is dependent on WIP, is WIP itself. This reverts commit d7d0c8134854cba72f0c3fe25946b27ce0364b43. Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7319 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-02intel_wifi: Export the SMBIOS structure required by intel driver.Vladimir Serbinenko
Change-Id: I22984a1bc7ca3be6593143af4fce8d5bfe469837 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7295 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-02inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 SeriesStefan Tauner
Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3 settings were missing. This led to some investigation and this patch, thanks! Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/7239 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-02SeaBIOS Makefile.inc: Remove build dir for uppermem optionMartin Roth
The build directory got removed while my patch was in flight and I didn't notice when I submitted it. The uppermemory change was added in commit 4d7d25f38a - http://review.coreboot.org/#/c/6364 The output directory was changed for everything else in commit ab11a6a94c - http://review.coreboot.org/#/c/6460 Change-Id: Ib8311f694280d305e826adbb76e3e7b722b30e0f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7298 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-02gigabyte/ga-b75m-d3h: Add new Intel mainboardDamien Zammit
This is based on LENOVO X230 port. Board boots to linux via SATA. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS 3. USB does not work. SeaBIOS/GRUB2 do not detect devices connected to USB ports 4. Sound needs corrected codec verb settings Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7020 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-02intel/bd82x6x: Add new current for native USB portsDamien Zammit
Change-Id: I88ef36b94b961a318d280d8de1b8721fcbeb93b0 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-02amd/agesa/f15: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I52da16b39293c8aeff150db83b8b1aeaa232c205 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7299 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f12: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ife26fb5eca5164e72b5e55eba90757253765b633 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7300 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f10: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ic1bd19087a4500ba0ca9e312ea351e301ab42518 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7301 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01superio/fintek/f81216h: Implement device supportEdward O'Callaghan
Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7309 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO'sEdward O'Callaghan
Super I/O manufactures have found new and innovative ways to enter and exit out of LDN config in PNP config space. Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01northbridge/via: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: Ib9d0fae363c5c1fbed3a63cb8aa86716cf1f9ee1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7289 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01northbridge/amd: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: I3fdd2a9f981592112998d74ce4cfe4850d8fab31 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7288 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01northbridge/intel: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: I9aeed70f72d4df260312df6e53379f1741415b65 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7287 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01mainboard: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: I37c302c7a17645f55d568c1a5f7bb791319ddbb4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7286 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7285 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01drivers: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: I931bd9c89bce6ac8f8e9e482a7876e2004abfb38 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7284 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01include/device/device.h: Provide DEVICE_NOOP macro shimEdward O'Callaghan
Rather than everyone writing their own adhoc device operation NOP shim, we provide some formalism. We later make use of this to reduce the loc count down trivially. Change-Id: I2d04bfb50e76f367a0ee258dab97d7caa12ec99e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7283 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-30lenovo/x2x0,t530 hda_verb.c: codestyle - remove some spacesNicolas Reinecke
Change-Id: Ieee54e28641f88497503d6d91ddeb52ad091d78d Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7274 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-30mainboards/asrock/e350m1: Use driver for Nuvoton NCT5572D superio chipFelix Held
On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot port to this board however used the driver of the Winbond W83627HF SuperIO, which is compatible enough to get most stuff working, but which clears bit 6 in register 0x2B. This switches the function of pin 38 of the NCT5572D from RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the unpopulated miniPCIe slot are connected to this pin, so they didn't get reset during a reboot. Using the newly added driver for the Nuvoton NCT5572D fixes this problem. There is also a trace from the pin 37 of the SuperIO, which can be configured as RSTOUT2#, to pin 82 of the USB3-chip with unknown function. As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB but not in Linux. Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6266 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-30Makefile: Fix HOSTCC for clangEdward O'Callaghan
Change-Id: I0470cf2c1e5266ceb33d55c9d616bfff37e97ed6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-30superio/nuvoton: Add support for Nuvoton NCT6776Felix Held
Add support for both NCT6776D and NCT6776F devices. Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/5450 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-30superio/nuvoton: Add support for Nuvoton NCT5572DFelix Held
Change-Id: I3b720cf879bf5326be885d2d3a3f9cfba0a27c7e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6229 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2014-10-29cpu/intel: Add configuration for socket LGA1155Damien Zammit
This allows mainboards to explicitly select LGA1155. Change-Id: Id33679b27c89038588347cb4f1a6a0e66aae3e6e Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7197 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-29libpayload: usb: ehci: Honor 10ms reset recovery periodJulius Werner
This patch adds the 10ms TRSTRCY delay between a reset and the following Set Address command that is required by the USB 2.0 specification to the EHCI root hub driver. The generic_hub driver that's used for XHCI and external hubs already included this delay. This is such a glaring violation of the spec that I'm really amazed how many USB 2.0 devices we tested before seemed perfectly fine with responding to a Set Address within 2 microframes of the reset... It also increases the port reset hold delay by one millisecond to avoid an ugly race condition on Tegra SoCs: they decided to time the 50ms themselves instead of relying on the CPU to do it (fair enough), and to automatically transition Port Reset to 0 and Port Enable to 1 after that (bad idea). If the CPU's read-modify-write to clear Port Reset races exactly with the host controller setting Port Enable, we may end up clearing the bit again and going into the companion controller handoff path later on. The added millisecond shouldn't cause any problems for other host controllers and is not a big deal compared to other delays in this code path. BUG=chrome-os-partner:26749 TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always gets detected correctly. Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/189872 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 4deca38e9d79f6373f4418fcaf51a6945232c8b8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68a29bfd2e0f30409fbfc330b2575f0f9f61a79d Reviewed-on: http://review.coreboot.org/7221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-29intel/sandybridge: Add PCI ID for northbridge 0x150Damien Zammit
Change-Id: I335244b7c39d6ddff6ecb06cb823fee09e35ee26 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7233 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-29Pipe stderr to /dev/null when getting LIBCLANG_RT_FILE_NAMEMartin Roth
Fix a warning when using gcc: i386-elf-gcc: error: unrecognized command line option '-print-librt-file-name' Change-Id: I421933ede9ddbddad37544a62e428c79e9ee2c8d Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7249 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-29minnowmax: Tell the FSP to set TSEG to 8MBMartin Roth
Minnowboard Max was broken by commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI because TSEG wasn't set to 8MB by the FSP. The default in the FSP is 1MB. Change-Id: I2e671a6ca0240e931399920c62439c36133789aa Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7240 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-29southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loopEdward O'Callaghan
Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/6147 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-10-28mainboard/google/butterfly: Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I167d2c9ad3f690de41fee51dd7800ce76b328e41 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7231 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-28src/Kconfig: Don't treat warns as errors on Clang builds yetEdward O'Callaghan
Currently clang/llvm builds are not fully supported. As such, let us tone down treating errors as warnings until we actually build the entire tree. Change-Id: If7f90f9887e27250f5e6d73d1692505676be9d47 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7230 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-28mainboard/google/stout: Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Id5c5d68048169b0cd400926cead2d1835194d1a5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28mainboard/samsung/lumpy: Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Ibbcdbb44c7586ac8d445870789647f8ff9585452 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7232 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-28A tool for IPQ8064 encapsulationVadim Bendebury
This is a copy of the tool provided by the vendor. It adds a header which tells the early stage loader where to load the next phase blob for execution. It is going to be used to encapsulate the bootblock. Usage of this tool is as follows: ipqheader.py <base-addr> <input-file> <output-file> Old-Change-Id: I448c006719f4f3dd5a6716ff2e47f7fc275c805e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193494 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 201630f8637eb627f0894ecd7bceb31017244ad4) Make ipqheader.py executable Modify the utility to become a Linux executable. While at it, fix the program name reported by error messages. Old-Change-Id: I25061d43fdea72655a696deb9e494e9c7382f670 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193495 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit bbbf69c754aa3b6a1bf17ab3ced1c739c3ee0688) ipq8064: SBL headers must have 4 byte aligned blob sizes It turns out that for SBL3 to load the next phase, the sizes in the MBN header must be 4 byres aligned. This change makes sure that this requirement is enforced. Old-Change-Id: Ia64f04bb281ae772b060d2f7713c98dd348972ba Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196167 (cherry picked from commit fa6a52a07cb87ecf2538a6b0d47605d79104e4cc) Add proper license to the ipqheader tool This patch adds a vanilla BSD 3-Clause license. Original-Change-Id: I9da7176e670b598808ef5be2461b6105a4c5f6c5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225783 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a0c47a8d74f1ac131c91e978b6d68bbcfaa52c37) Squashed 4 commits for the ipqheader util. Change-Id: I144c01947a89e1348a06aa82590e972e2ec31247 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6976 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-28rmodtool: add support for ARMAaron Durbin
Add support for creating ARM rmodules. There are 3 expected relocations for an ARM rmodule: - R_ARM_ABS32 - R_ARM_THM_PC22 - R_ARM_THM_JUMP24 R_ARM_ABS32 is the only type that needs to emitted for relocation as the other 2 are relative relocations. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built vbootstub for ARM device. Original-Change-Id: I0c22d4abca970e82ccd60b33fed700b96e3e52fb Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190922 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a642102ba7ace5c1829abe7732199eda6646950a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib3b3c90ebb672d8d6a537df896b97dc82c6186cc Reviewed-on: http://review.coreboot.org/7204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-28rambi: switch MCLK from 19.2Mhz to 25MhzKein Yuan
With following settings 1.Coreboot 25Mhz 2.Maxim codec configured with MCLK=25Mhz 2.I2C 400Khz fixed 4.Including Enable/Disable SHDN bit when LRCLK starts/Stops 5.Removed PLL toggle workaround routine. audio playing is smooth before/after S3, no noise when recording so change MCLK from 19.2 back to 25Mhz. BUG=chrome-os-partner:26948 BRANCH=firmware-rambi-5216 TEST=test audio play and record on Rambi, works fine. Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6 Signed-off-by: Kein Yuan <kein.yuan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/193881 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7219 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
We're no longer configuring hotplug + backlight settings from devicetree, so remove these entries + fields. BUG=chrome-os-partner:27304 TEST=Compile only. BRANCH=rambi+squawks Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193831 (cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7218 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
- The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28rambi: always show dev/rec screens on eDP connected panelKein Yuan
bit: 7 6 5 4 3 2 1 0 LFP2 EFP2 EFP3 CRT2 LFP EFP TV CRT so int 15 0x5f35 need to return 0x8(LFP/eDP) instead of 0x2(TV). BUG=chrome-os-partner:26365 BUG=chrome-os-partner:27505 BRANCH=rambi TEST=Booted with and without HDMI connected monitor. DEV screen always showed on eDP panel on Rambi. Change-Id: I8f876e78383424f517689eb25e9229a27739957b Original-Change-Id: I77edbeb3c86549f90302b4296b5a2f50313ca675 Signed-off-by: Kein Yuan <kein.yuan@intle.com> Reviewed-on: https://chromium-review.googlesource.com/193303 Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit dd375462147f182331f336ba826108e58b4e0a47) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
According to DPTF team _PPC in TCPU must return 0 always. BUG=chromium:355964 TEST=Pass build. BRANCH=rambi Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73 Signed-off-by: Kein Yuan <kein.yuan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/193069 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 6dbcc677ceebbaf832e41e6db1e6cf171e2e231f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
Provide the option to embed MRC as an ELF file and not just binary blob. This allows for MRC to be relocated. BUG=chrome-os-partner:27654 BRANCH=rambi TEST=Built and booted rambi. Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192893 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7214 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
Suggested settings to try for performace regression: 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26211 BRANCH=baytrail TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192573 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP status. BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` + reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86 Reviewed-on: http://review.coreboot.org/7211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28cbmem: Fix 64-bit pointer related casts in dynamic_cbmem.cMarcelo Povoa
Change-Id: I7a382d42e1552d13b1feffc37848674f304adee2 Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187726 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 57bbca93f12e0ddbde3e673070483e13521dfbdd) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6973 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-28cbfstool: If compression fails, warn and use the uncompressed data.Gabe Black
The LZMA compression algorithm, currently the only one available, will fail if you ask it to write more data to the output than you've given it space for. The code that calls into LZMA allocates an output buffer the same size as the input, so if compression increases the size of the output the call will fail. The caller(s) were written to assume that the call succeeded and check the returned length to see if the size would have increased, but that will never happen with LZMA. Rather than try to rework the LZMA library to dynamically resize the output buffer or try to guess what the maximal size the data could expand to is, this change makes the caller simply print a warning and disable compression if the call failed for some reason. This may lead to images that are larger than necessary if compression fails for some other reason and the user doesn't notice, but since compression errors were ignored entirely until very recently that will hopefully not be a problem in practice, and we should be guaranteed to at least produce a correct image. Original-Change-Id: I5f59529c2d48e9c4c2e011018b40ec336c4fcca8 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187365 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit b9f622a554d5fb9a9aff839c64e11acb27785f13) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Change-Id: I5f59529c2d48e9c4c2e011018b40ec336c4fcca8 Reviewed-on: http://review.coreboot.org/6958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28cpu/x86/smm/Makefile.inc: Correct SMM linkage under clang buildsEdward O'Callaghan
Ensure that the SMM build stage links properly using the compiler-rt runtime under a Clang build. Change-Id: Iead28c46d63f5bbb27757b7dc66fe06b4813d03c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-28build: Allow clang build linkage to use libcompiler-rtEdward O'Callaghan
Make use of '-print-librt-file-name' over '-print-libgcc-file-name' to use Compiler-RT runtime glue over libgcc glue. NOTE: *** Requires at least clang 3.6.x Change-Id: I7f63284473d6067bf775409970c8dd98f5d5a8d5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6144 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7146 Tested-by: build bot (Jenkins)
2014-10-27drivers/spi: add Macronix MX25U6435F and MX25L6495F supportIdwer Vollering
Contributed by MXIC: http://www.coreboot.org/pipermail/coreboot/2014-October/078835.html Change-Id: I07f872a5cbb2b0ea63794edb8fbca40d7856ce10 Author: Alex Lu <alexlu6@mxic.com.tw> Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/7194 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-27superio/*/superio.c: Don't hide pointer types behind typedefsEdward O'Callaghan
Hiding pointer types behind 'typedef's is usually not a great idea at the best of times. Worse the typedef becomes an integer at different stages in Coreboot. Let us refrain from doing this at all. Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7136 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-27superio: Use 'pnp_devfn_t' over 'device_t' in romstage componentEdward O'Callaghan
The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6231 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-27superio/common/conf_mode.c: Don't hide pointers with typedefsEdward O'Callaghan
Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7137 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-27lenovo/x2[23]0: Handle Ricoh SD cardreaderVladimir Serbinenko
Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7203 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-26include/device/device.h: Deduplicate '*_pnp_devfn_t' typedefsEdward O'Callaghan
'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6230 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-25Use spelling LENOVO troughout instead of using Lenovo sometimesVladimir Serbinenko
Change-Id: Ia4060831236d72f880eeff6263ada40cf195fb12 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7180 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-25lenovo/{x60,t60}: Change PARTNUMBER for consistencyVladimir Serbinenko
Change-Id: I0ace5f49b84170ab4701ad1b70d3c50c99066e53 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7178 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-25lenovo: Use readable name as part number.Vladimir Serbinenko
Part number is used only for coreboot ROM identification and in coreboot tables. Rather than guessing the P/N, just use readable name. SMBIOS uses information from EEPROM and so isn't affected. Change-Id: I33534c3acb83f20d5b493c82bfc98896bf64ff1a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7177 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-24lenovo/*: Remove unused MAINBOARD_VERSIONVladimir Serbinenko
Change-Id: I88e889efe43b32e7efc59ea40d13e79209a27264 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7179 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-24siemens/sitemp_g1p1: Fix serial output for simo boardDennis Wassenberg
The simo board with console output at UART port 1 (COM2) will not produce any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly. Commit f29200240e428761827ab8d179fa23068bfa9d59 (superio/ite/*: Factor out generic romstage component) will only and always activate UART port 0 unregarded to CONFIG_UART_FOR_CONSOLE value. Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE will be enabled and used for console output Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78 Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: http://review.coreboot.org/7060 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-24sandybridge: Kill CONFIG_HAVE_MRC_CACHEVladimir Serbinenko
Change-Id: I54955fa44d126b7a3d382f57b4aa0dac01688104 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7129 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-24sandy/ivy native: dedup romstage.c main()Vladimir Serbinenko
Change-Id: I9909a5b2bdb4b59219db6304fa4332802fe0301c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7127 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-23AMD Hudson: enable IMC fan control using ACPI codeWANG Siyuan
IMC fan control should be enabled after OS launched. I have tested on OliveHill and Parmer with Windows 7 and Ubuntu 13.10. Change-Id: I16d6ff6b1272d16b840e803e0a95f6e363c79704 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/7165 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-10-23AMD Trinity and Kabini: fix fan controlKyösti Mälkki
The fan can stop but can't run again. "AGESA: Call get_bus_conf() just once" (commit ef40ca57) results to this problem. This patch can resolve this problem. Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6981 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-23intel/sandybridge: Add VGA pci device ID 0x0162Damien Zammit
for Ivy Bridge. Tested on Gigabyte ga-b75m-d3h. Change-Id: I7a1b1e8bac38789321960ebbe8c97d68a5aebfe2 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7173 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-23t530: Move to common gpio.h inrastructureVladimir Serbinenko
Change-Id: I5cf6dbab64f3eda02e6418be65f21e28ddf0d9ff Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7125 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-22libpayload: usb: Make OHCI work with ARM systemsJulius Werner
This patch enables the OHCI driver to use DMA memory, which is necessary for ARM systems where DMA devices are not cache coherent. I really only need this to test some later OHCI changes, but it was easy enough... copied almost verbatim from ehci.c. Change-Id: Ia717eef28340bd6182a6782e83bfdd0693cf0db1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193730 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit e46b6ebc439e86a00e13bf656d60cf6c186a3777) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7010 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22amd/torpedo amd/dinar: Sanitize agesawrapper headerKyösti Mälkki
Change-Id: I3badb18839773e38834de967a51c29a306975d20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7152 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-22AGESA fam15tn fam16kb: Fix missing FCH function prototypesKyösti Mälkki
Change-Id: I242664032d368794d828fce73a20f75ded45051d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7151 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-22amd/olivehillplus: No global variables for romstageKyösti Mälkki
These functions are only used for ramstage. Change-Id: I089230ca625037637c7af061b0939fd981dbdfd2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7148 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-22AGESA boards: Fix early agesawrapper_amdinitmmio()Kyösti Mälkki
Regression introduced with commit 7b23ae0 AGESA: Trace execution with AGESAWRAPPER() As the call is made before console_init() is called it must not call any printk(). Debugging Olivehill and Parmer platforms using a custom FPGA (as these boards have no Super-IO UART) have been observed to halt and/or delay at early boot. Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7059 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
2014-10-22macbook11: Fix typoVladimir Serbinenko
Change-Id: Iddd4d99af7e1c70384f13f18d785f491c47c7617 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6712 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-22libpayload: usb: xhci: Fix STALL endpoint handlingShawn Nematbakhsh
- Remove the call to clear_stall in xhci_reset_endpoint because we will call clear_stall from the mass-storage driver. - Remove the xhci_reset_endpoint call from xhci_bulk on STALL since we will reset on the next transfer anyway. - Remove the clear_halt parameter from xhci_bulk since it's now unused. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I852b87621861109e596ec24b78a8f036d796ff14 Reviewed-on: https://chromium-review.googlesource.com/192866 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit e67e4f0545cbdc074328c83c7edccf9e712cd7be) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7011 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22reg_script: include in romstageIsaac Christensen
The new broadwell support uses the reg_script functions in romstage. Change-Id: Ic040bf947d35854711f4c1547858b0e4378ef759 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7003 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
The reg_script functionality is only used by specific chipsets so have it selected instead of defaulting to y for ARCH_X86. Change-Id: I8fb9466e148eed7896ca8ed80755c77ba1190583 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-22tegra/nyan*: sdram updatesTom Warren
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
Most of the code related to the mc146818 is not related to the RTC and is really for managing the CMOS storage. Since we intend to add a generic API for RTC drivers it's inconvenient for those functions to have an rtc_ prefix. This CL renames those functions so they start with cmos_ instead. There are some places where rtc_init was called with a comment that says something about starting the RTC. That wasn't correct before (the RTC is always running), but it looks a little odd now that the function is called cmos_init. This CL also opportunistically cleans up some style problems in this file. Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/197794 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788) Removed the addition of stdint.h to mc146818rtc.h since types.h is now included. Changed rtc_init to cmos_init for fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex. Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22spi: Remove unused constants from spi-generic.h.Gabe Black
These constants aren't used anywhere. Change-Id: Ifdad9b088a281909892edb34dcb58419e0e123ba Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192047 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3cdaf9dd7de6ae71efc9e74335d876ec55f9ca0a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22tpm: i2c: When probing the TPM, write a 0 into the TPM access register.Gabe Black
Not doing so makes it fail when run at high frequency. Change-Id: I1cfb69c55f03cb90f66f437289803d897a1aad5c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/191812 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 04452441d2bfe2cacd3e0b6990c0e9261b5350d1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7007 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
Broadwell D0 updated to 0x10 (debug) Broadwell E0 updated to 0xD Haswell updated to 0x1C Change-Id: Ib3e27b3467fec1106c69d82c0b1522d58025d67e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/208212 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 048a8b68dbc79dd27dc3188dde407a95c4d729fc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6984 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-22broadwell: Update microcodeDuncan Laurie
40651: rev 00000018 306D3: rev FFFF000F 306D4: rev 00000009 Change-Id: I47a6caadc83f0ed96b0a4b0c624ad105d9dee3b6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f8f0703c7042a14c6807cbea74eae6e85ba6854e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
broadwell: Add romstage usbdebug support Reviewed-on: https://chromium-review.googlesource.com/199412 (cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5) broadwell: Add romstage code to configure PCH UART for console Reviewed-on: https://chromium-review.googlesource.com/199807 (cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a) broadwell: Expand the PCI device convenience macros Reviewed-on: https://chromium-review.googlesource.com/199891 (cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad) broadwell: Add ramstage driver for ADSP Reviewed-on: https://chromium-review.googlesource.com/199892 (cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f) broadwell: Update ACPI devices Reviewed-on: https://chromium-review.googlesource.com/201080 (cherry picked from commit 2446b35578eb36e0009415bec340059135751549) broadwell: Reserve DPR region Reviewed-on: https://chromium-review.googlesource.com/201081 (cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6) broadwell: Remove old pei_data and add cpu function for romstage Reviewed-on: https://chromium-review.googlesource.com/201690 (cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274) broadwell: Fixes for graphics without executing VBIOS Reviewed-on: https://chromium-review.googlesource.com/202356 (cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa) broadwell: Fix compilation failure when loglevel is lowered Reviewed-on: https://chromium-review.googlesource.com/202357 (cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc) broadwell: Disable GPIO controller interrupt Reviewed-on: https://chromium-review.googlesource.com/203645 (cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9) broadwell: Add support for E0 stepping Reviewed-on: https://chromium-review.googlesource.com/205160 (cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273) broadwell: misc updates for CPU driver Reviewed-on: https://chromium-review.googlesource.com/205161 (cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97) broadwell: Read power state earlier and store in romstage params Reviewed-on: https://chromium-review.googlesource.com/208151 (cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e) broadwell: Add parameters to pei_data structure Reviewed-on: https://chromium-review.googlesource.com/208153 (cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af) broadwell: Move platform report output after power state is read Reviewed-on: https://chromium-review.googlesource.com/208213 (cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78) Squashed 15 commits for broadwell support. Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6982 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
New microcode released this week. Change-Id: I426d0e00d1c03650049cbe033b53a909a7d944c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 63ec6438b566d14a2b878474ca068cf70d9aa9d6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6966 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
This broadwell implementation will support Haswell ULT in addition to broadwell CPUs. Add the latest available microcode for the broadwell C0 and D0 parts as well as Haswell ULT. Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198742 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 69d5b7c834a4f52656ab14562ea913477418e588) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6965 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 12:58:02 +0000