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2016-01-07viatool: add NetBSD supportAndrey Korolyov
Change-Id: I033044e4b781475d6d60a49a61313a720103ce38 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12836 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07Revert "util/crossgcc: Regenerate MPFR autotools files before build"Timothy Pearson
This reverts commit 68d0e4a5a1e7028227f6fbe086c891955cb7854e. Special handling of MPFR is no longer needed with the latest MPFR release. Change-Id: I96d9ea92cfb74eed6af2ba62254f0678081e2b4f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12833 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07util/crossgcc: Bump MPFR version to 3.1.3Timothy Pearson
The current MPFR version contains a stale config.guess file that requires special handling on ppc64el systems. Bump the MPFR version to the latest release. Change-Id: I5e86c732c09f8a6a43f9812452124d64d337ea3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12832 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06viatool: Add VIA C3 MSRsAndrey Korolyov
Tested on C3/EPIA board and Linux x86 Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06cpu/amd/fam10h-15h: Add tsc_freq_mhz() functionTimothy Pearson
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-06cbfstool: correct add-master-header logic to match runtime expectationsAaron Durbin
The cbfs master header's offset and romsize fields are absolute values within the boot media proper. Therefore, when adding a master header provide the offset of the CBFS region one is operating on as well as the absolute end offset (romsize) to match expectations. Built with and without CBFS_SIZE != ROM_SIZE on x86 and ARM device. Manually inspected the master headers within the images to confirm proper caclulations. Change-Id: Id0623fd713ee7a481ce3326f4770c81beda20f64 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12825 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-06Revert "x86: Align CBFS on top of ROM"Aaron Durbin
This reverts commit 65e33c08a9a88c52baaadaf515b9591856115a77. This was the wrong logic to fix the master header. Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12824 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06Documentation: Add information about patches from other git reposMartin Roth
This is more tribal knowledge that I don't think I've seen written down anywhere else. It's not a huge issue, but when looking through the git log, it helps to be able to differentiate the information from the old gerrit with the information from the new one. Change-Id: I7993bda1e9aab79dc26940aaba9ddc52382ed0df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12804 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06cbfstool: Add 'hashcbfs' command to compute hash of CBFS region.Aaron Durbin
For the purposes of maintaining integrity of a CBFS allow one to hash a CBFS over a given region. The hash consists of all file metadata and non-empty file data. The resulting digest is saved to the requested destination region. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Integrated with glados chrome os build. vboot verification works using the same code to generate the hash in the tooling as well as at runtime on the board in question. Change-Id: Ib0d6bf668ffd6618f5f73e1217bdef404074dbfc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12790 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06cbfstool: keep cbfs master header pointerPatrick Georgi
Adding new files overwrote the header with the empty file (ie 0xff), so carve out some space. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I91c292df381c2bac41c6cb9dda74dae99defd81d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12789 Tested-by: build bot (Jenkins)
2016-01-06cbfstool: Adapt "cbfstool copy" to only use fmap regions.Patrick Georgi
These need to go together, so the commit became a bit larger than typial. - Add an option -R for the copy source fmap region. Use: cbfstool copy -r target-region -R source-region. - Don't generate a CBFS master header because for fmap regions, we assume that the region starts with a file header. Use cbfstool add-master-header to add it afterwards, if necessary. - Don't copy files of type "cbfs master header" (which are what cbfstool add-master-header creates) - Leave room for the master header pointer - Remove -D command line option as it's no longer used. BUG=chromium:445938 BRANCH=none TEST=Manual test on image and integration test w/ bundle_firmware changes. CQ-DEPEND=CL:313770,CL:313771 Change-Id: I2a11cda42caee96aa763f162b5f3bc11bb7992f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12788 Tested-by: build bot (Jenkins)
2016-01-06cbfstool: Use buffer over offset/size pair for cbfs_copy_instancePatrick Georgi
This allows adding support for FMAP based cbfstool copy more easily. BUG=chromium:445938 Change-Id: I72e7bc4da7d27853e324400f76f86136e3d8726e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12787 Tested-by: build bot (Jenkins)
2016-01-06commonlib: Add function to hash contents of a CBFS region.Aaron Durbin
Provide a common routine to hash the contents of a cbfs region. The cbfs region is hashed in the following order: 1. potential cbfs header at offset 0 2. potential cbfs header retlative offset at cbfs size - 4 3. For each file the metadata of the file. 4. For each non-empty file the data of the file. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized in chromeos cros_bundle_firmware as well as at runtime during vboot verification on glados. Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12786 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-01-06commonlib/cbfs: Add type ids for empty filesPatrick Georgi
We will soon need to handle empty files. Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12785 Tested-by: build bot (Jenkins)
2016-01-06commonlib: Prepare code to be included in cbfstool builds.Aaron Durbin
Some of the files need to be adjusted so that they can be used both in cbfstool as well as coreboot proper. For coreboot, add a <sys/types.h> file such that proper types can be included from both the tools and coreboot. The other chanes are to accomodate stricter checking in cbfstool. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Built on glados including tools. Booted. Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add common cbfs parsing logic to coreboot and cbfstool.Aaron Durbin
To continue sharing more code between the tools and coreboot proper provide cbfs parsing logic in commonlib. A cbfs_for_each_file() function was added to allow one to act on each file found within a cbfs. cbfs_locate() was updated to use that logic. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add function to compute relative offsets from two region_devices.Aaron Durbin
Provide a helper function which returns the relative offset between 2 region_devices that have a parent-child child relationship. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06toolchain.inc: Test for valid toolchain when ANY_TOOLCHAIN is usedMartin Roth
Even when ANY_TOOLCHAIN is selected, a valid compiler for the requested architecture is needed. Change-Id: If1a0a1ca6b726e8e58d29c69de93546510582548 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-05xcompile: Remove warnings about missing tools & architecturesMartin Roth
Let toolchain.inc error out when the architecture or tool is missing. Change-Id: I39a51e5a2c778d6bbc50354807e5e2b717fa9e52 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12682 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-04util/crossgcc: Add ppc64el supportTimothy Pearson
Change-Id: I619f7c3cef7f0aaa6fccb3d52f2ac1f6ace6d0d6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12818 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04util/crossgcc: Regenerate MPFR autotools files before buildTimothy Pearson
The config.guess file included with MPFR is completely obsolete, leading to build failures on ppc64el due to the system architecture not being detected. Regenerate the files from the host system via automake before attempting to build MPFR. Change-Id: I00fc16003906e373d112c25978197ac907adccfd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04util/crossgcc: Bump GMP version to 6.1.0Timothy Pearson
The previous official GMP release (6.0.0) contains a bug that prevents compilation on ppc64el systems. Increase version to the latest version (6.1.0). Bug details: gcc build on ppc64el fails with: (.text+0x4c): undefined reference to `BMOD_1_TO_MOD_1_THRESHOLD' While I don't have an exact commit hash due to Hg use upstream, a missing BMOD_1_TO_MOD_1_THRESHOLD define on ppc64el was quietly fixed in Hg before the 6.1.0 release. Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12811 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04sb/amd/sr5650: Correctly locate CPU MMCONFIG resourceTimothy Pearson
The code committed in GIT hash * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support did not correctly locate the CPU MMCONFIG resource, leading to failures with operating systems and firmware (e.g. SeaBIOS) when the PCI extended configuration space option was activated. Due to the southbridge routing not being set up, MMCONFIG accesses were targetting DRAM and therefore the PCI devices were not being configured. The failure normally manifests as a system hang immediately after PCI configuration starts. Search for the CPU MMCONFIG resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12821 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04toolchain.inc: Update help text, Add TODO.Martin Roth
- Update the help text to be more informative. - Add todo about IASL - we shouldn't require it if the build doesn't use it. Change-Id: Iffeb94f78c1ae7535a8a7b9b0b9f1728301a42b3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-04toolchain.inc: Skip how to use any toolchain if it's selectedMartin Roth
If ANY_TOOLCHAIN is selected, don't bother telling the user how to do what they've already done. Change-Id: I7182d18a91e832aa56638ec64fe8b3b0c38cff7a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04toolchain.inc: Move nocompile around entire check, Comment endifsMartin Roth
Move the check for NOCOMPILE flag around the whole block. There's no need to test COMPILERFAIL if NOCOMPILE is set. Comment the endif lines to make it easier to understand. Signed-off-by: Martin Roth <martinroth@google.com> Change-Id: Id7bb5ca13e6bf1cabf4b7b2ff3256b47b966bac1 Reviewed-on: https://review.coreboot.org/12678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-04toolchain.inc: Test for toolchain when using llvm/clangMartin Roth
Change-Id: I45ed5e289f9bfae90d71938243f921588b256e39 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04genbuild_h.sh: allow coreboot to be a git submoduleBen Gardner
When coreboot is pulled in as a submodule, the .git "folder" is a file, not a folder. Use the '-e' test instead of '-d' to allow for that. Change-Id: I0dd8866b0016f7ba099cdaf4d7db442ff22612b5 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12819 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04Revert "AMD OemS3Save: refactor for Merlin Falcon"Kyösti Mälkki
This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93. Do not mix open-source AGESA and binary PI trees. Once you have working S3 support for binaryPI platforms, add the adapted oem_s3.c file as northbridge/amd/pi/oem_s3.c instead. Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/12282 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-03sb/intel/bd82x6x: Add missing PCIIDs for variants .Vladimir Serbinenko
Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12820 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-12-31nb/intel/gm45: Export low-power and (SFF) optionsNico Huber
Make the low-power and small form factor (SFF) options overridable from romstage main. Also disable both options by default. That's ok as there aren't yet any in-tree users of the GS45 chipset. As a nice side-effect, this adds X200s support to the lenovo/x200 port. Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12814 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-31lenovo/x200: Revise onboard IRQ routingNico Huber
All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I687262556d918311757fda9afda9ebfdd7edf947 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12813 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-31superio/it8772f: Add register to set the default value of FAN speedTed Kuo
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef Original-Reviewed-on: https://chromium-review.googlesource.com/262832 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12799 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31superio/it8772f: Add switch to enable HWM (Hardware Monitor)Ted Kuo
Set up External Temperature to read via thermal diode/resistor into TMPINx register by setting thermal_mode switch. Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034 Original-Reviewed-on: https://chromium-review.googlesource.com/260545 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a) Original-Reviewed-on: https://chromium-review.googlesource.com/262340 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12798 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: memlayout: update GRAM sizeIonela Voinescu
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: I2C: fix base address for I2C clock setupIonela Voinescu
The base address for the I2C dividers (DIV1 and CLOCKOUT) was erroneously set to the toplevel clock controller base address and not to the correct peripherals clock controller base address. Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: identity map SOC registers regionIonela Voinescu
This region must be mapped uncached. This is necesary for an U-boot payload which will obtain all register base addresses as physical addresses from the device tree and will use them as such. Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: Add SOC_REGISTERS memory regionIonela Voinescu
When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: Use SYS PLL in integer modeIonela Voinescu
Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-30gigabyte/ga-g41m-es2l: Add mainboardDamien Zammit
Board uses x4x native raminit Board boots into Debian 8 with full graphics IRQ9: nobody cared, gets disabled (PIC needs IRQ settings?) VGA: - VGA native init works in grub with analog connector - Fails to boot with both channels of ram populated Change-Id: I7417813456817529b8cbaace45cefe47467d0a82 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/11306 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30northbridge/intel/x4x: Native raminitDamien Zammit
Passes memtest86+ with either one or two sticks of 2GB ram but memory map needs a hole at 0xa0000000 to 0xc0000000 Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/11307 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30superio/it8718f: Add missing PNP infoDamien Zammit
Change-Id: Id6d50d4d6af31e43f851645f09383121755291f6 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12815 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-30drivers/xgi/common: Fix XGI_SetGroup2Stefan Reinauer
This code looks like it was created from a disassembly of some other driver. Attempt to fix it, without hardware or documentation. CID 142909: Operands don't affect result (CONSTANT_EXPRESSION_RESULT) Change-Id: I9b9cadf2acdba73913aad6bbe0d14ad64a652915 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12774 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-30Kconfig: move fmap description file prompt into the mainboard menuMartin Roth
The FMD is board-specific, so it makes sense to have it in the mainboard menu. Change-Id: I52fba5ced869d51d10065f8c9ebd258d3a1d4156 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/12805 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-30MAINTAINERS: Designate Intel maintainers for FSP 1.0 BaytrailAlexandru Gagniuc
After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I62b2eaec8270ac1fce5bfbee3b3da68aba116b0f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/11894 Reviewed-by: York Yang <york.yang@intel.com> Tested-by: build bot (Jenkins)
2015-12-30x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE filesAlexandru Gagniuc
Non-code flow assembly stubs do not have to be included in bootblock.S, now that we have more freedom in bootblock linking. Rather than bringing these stubs to the config system, just link them in the bootblock. Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this point, as some intel SOCs use this stub for code flow. objdump -h build/cbfs/fallback/bootblock.debug on a few random boards confirms that the appropriate sections are still included in the final binary. Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/11856 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30Makefile.inc: Fmaptool build fixesMartin Roth
- make sure CONFIG_CBFS_SIZE is lowercase for fmaptool. - Regenerate the fmap.fmd file when config.h changes. - Print the fmaptool step when doing the build. Change-Id: Ib518ed469d9e39eb41c81f7b19480c7789067d2d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/12806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29x86: Align CBFS on top of ROMNico Huber
Since the introduction of the new (interim?) master header, coreboot searches the whole ROM for CBFS entries. Fix that by aligning it on top of the ROM. Change-Id: I080cd4b746169a36462a49baff5e114b1f6f224a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12810 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-29MAINTAINERS: Designate Intel maintainer for FSP 1.0 Ivy BridgeMartin Roth
After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I33d95db12d9e394360a207c8fbcfbc15723115c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-12-29device/pnp: Ability to set vendor specific logical device configDamien Zammit
According to the PNP ISA v1.0a spec, config registers in the range of 0xf0 up to 0xfe are vendor defined and may be used for any purpose. Config register 0xff is reserved and is defined as such. Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa are able to be set using the PNP_MSCx bit flag masks. This patch adds support for all 15 vendor specific config registers, and updates the existing superio pnp_info to use them where appropriate. Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29northbridge/intel/x4x: Intel 4-series northbridge supportDamien Zammit
Boots to console on Gigabyte GA-G41M-ES2L Ram initialization *not* included in this patch VGA native init works on analog connector Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/11305 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29mips: add coherency argument to identity mappingIonela Voinescu
In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-29cbmem: Makefile: Add install targetDenis 'GNUtoo' Carikli
Change-Id: Ib20481e43e6ca5b56c630cdc0eb7b1b01311cbb6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12404 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-28genbuild_h.sh: Get current rev for git revision, not origin/masterMartin Roth
Using origin/master as the git revision breaks reproducibility, giving different values depending on when the code was pulled from the repo at coreboot.org. By using the current revision instead, we get identical builds. Change-Id: If4be6e048d6c8e417b8c074199745900ccd82b49 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12807 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-27mainboard/google/urara: change SYS PLL to 700MHzIonela Voinescu
This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-27soc/intel/broadwell: Add back support for EHCI debug setupDuncan Laurie
The EHCI debug device setup code was removed from broadwell in commit 49ee5ef: http://review.coreboot.org/11874 However the generic device setup code is in the southbridge/common/intel directory while broadwell is in the soc directory so this is not used. Add it back to the broadwell soc to fix undefined reference compile errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'. This was tested to compile and produce romstage and ramstage output on a google/samus board. Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12794 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27broadwell: Fix SATA Gen3 DTLE configuration registersDuncan Laurie
The port0 and port1 registers were swapped, which meant it did not work to apply the DTLE settings to the correct SATA port. This was tested on an unreleased mainboard but is verified with the documentation to be the correct register addresses now. Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12793 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27broadwell: Fix CONFIG_SPI_CONSOLE usageDuncan Laurie
Locking down the SPI controller with a specific opcode menu kills the SPI console. Skip this when the SPI console config option is enabled. This was tested using an em100 and google/samus board to ensure the console output does not stop at the finalize step. Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12792 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-26ACPI: Add hack to avoid IASL warning when reading back registersMartin Roth
Upcoming versions of IASL give a warning about unused methods. This adds an operation after the read to use the local variable and avoid the warning. The warning can be completely disabled on the command line, but as it can find real issues, my preference is to not do that. Fixes warnings: dsdt.aml 640: Store (CTMP, Local0) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-26IT8772F: Clean up it8772f includes and add a LED APIdavid
- Remove it8772f c includes - Add a new LED API, it8772f_gpio_led - Stumpy: using it8772f_gpio_led BUG=chrome-os-partner:28232 BRANCH=Guado TEST=emerge-guado coreboot chromeos-bootimage Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3 Signed-off-by: David Wu <David_Wu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/241813 Tested-by: David Wu <david_wu@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: David Wu <david_wu@quantatw.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12797 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-25cpu/allwinner/a10: Fix I2c speed calculationMartin Roth
Looking at the A10 datasheet, N should go in bits 2:0, but was being cleared by shifting it left by three bits, then anding it with 7. Fixes coverity warning: CID 1241888 (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT) operator_confusion: (n << 3) & (7U /* 7 << 0 */) is always 0 regardless of the values of its operands. This occurs as the bitwise second operand of '|'. Change-Id: I17e71a73adf37a62607e8e5865b1da749d7278aa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12779 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-22soc/intel/fsp_baytrail: Make sure i2c bus is < 7Martin Roth
Baytrail has I2c Busses 0 to 6, so is supposed to error out if the I2c driver is called with 7 or greater. Due to an off-by-one error it could be called with bus 7. Fixes coverity warning: CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN) 3. overrun-local: Overrunning array base_adr of 7 4-byte elements at element index 7 (byte offset 28) using index bus (which evaluates to 7). Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12781 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-22drivers/intel/fsp1_0/fsp_util.c: Fix indentationMartin Roth
- Also update post code comment to keep under 80 characters. Change-Id: Id0fd0ee5660f2628fe33188855bebb6e3eea8d2e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12780 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-21imgtec/pistachio: DDR2, DDR3: DLL reset setIonela Voinescu
Bit 8 of the MR register is automatically set by the PHY during memory initilization but having it set in the register leads to a more clear understanding. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: DDR2, DDR3: DQS gate earlyIonela Voinescu
Switching on DQS Gate Early and DQS Gate Extension with 500R DQS/DSQN Resistors. This setup was recommended by Synopsys. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: increase CBFS cacheIonela Voinescu
Increase CBFS cache size to allow for a bigger payload. Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20buildgcc: Add coreboot toolchain string to clang versionMartin Roth
clang version now returns: coreboot toolchain v1.33 November 25th, 2015 clang version 3.6.1 (tags/RELEASE_361/final) (based on LLVM 3.6.1) Change-Id: I948d7f4d06c244987342cfc7d5c7e728cbed93bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12777 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20Makefile.inc: Move addition of payload rev & config to payload makefileMartin Roth
These files need to be added to cbfs-files after PAYLOAD_CONFIG and PAYLOAD_VERSION have been defined. Where they were before, they didn't get added to the final build. Change-Id: Ib1b230f9eb72a8c1710ef473a9f24c0fb7ec6e17 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20soc/intel/broadwell: Init var before use, only use when neededMartin Roth
root_port_init_config() pcie.c wasn't initializing a variable before passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the uninitialized value into a register. In theory, the register would only be used if data was being written, and pch_iobp_exec() was being used to read the data, not write it, so this change shouldn't have any practical effect. Fixes coverity error: CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT) Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12778 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-12-20board_status.sh: Double quote variables to prevent globbing and word splitting.Martin Roth
Quoting variables prevents word splitting and glob expansion, and prevents the script from breaking when input contains spaces, line feeds, glob characters and such. See shellcheck warning SC2086. Change-Id: I7256d2fc2a22bce7723950a534fef6d57cbd097f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20board_status.sh: checksum the rom and save it for later verificationMartin Roth
This allows users who build the rom from the board-status repo to verify that their rom matches the original. Change-Id: I4e8564e389495909219f92ccdafb8e9568f8f0d0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20board_status.sh: Clean up output, show what the script is doingMartin Roth
- Print what the script is doing so when it asks for the ssh password several times in a row, it's obvious that it's actually doing different things, not that the password failed. - Don't print the output from cbfstool - it's not useful. Change-Id: I785283475e14f242117682800c26db6b4f9f1e2c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20board_status.sh: Extract payload config & version filesMartin Roth
If the payload_config and payload_version files are in coreboot.rom, extract and save them. Change-Id: I36b17ed189f94e2d4e873b0e219e5a9a2abe77a1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20board_status.sh: Update to fix serial port readsMartin Roth
The old serial port read method lost characters from the boot log. This method works better for me. - Put get_serial_bootlog arguments into variable names for clarity. - Fully configure the serial port with stty: disable parity and flow control. - Change serial port read from reading with 'cat' to reading with 'read'. - Update help to show current default speed from the variable. tested under dash, bash, and zsh on several platfoms. Change-Id: I91ae63a3c226e61019dbdf69c405c3f20ba7db54 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-18southbridge/amd/sr5650: Add MCFG ACPI table supportTimothy Pearson
As the southbridge largely controls the PCI[e] configuration space this patch moves the resource allocation from the northbridge to the southbridge when the extended configuration space region is enabled. Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-18mainboard/asus/kgpe-d16: Enable CBFS spinlocksTimothy Pearson
Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12062 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18drivers/pc80: Add optional spinlock for nvram CBFS accessTimothy Pearson
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18cpu/samsung/exynos5250: Move update-bl1.sh to 3rdparty/blobs/Stefan Reinauer
The binary is taken from blobs, so the script should live over there, too. Change-Id: I3cc0aabc846c352ccf5cb348132b320a37f273a6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12725 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-12-18siemens/mc_tcu3: Set GPIO_S0_SC[75] to outputWerner Zeh
The usage of the pin has changed and therefore this pin needs to be set up as output and drive low initially. Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12754 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-17Enable KCONFIG_STRICT modeStefan Reinauer
Change-Id: I6aa77db1b12a67472302ea39d7433993a6838af6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/10978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-17google/veyron: Add commercial board names in Kconfig.nameDenis 'GNUtoo' Carikli
The correspondence between engineering code names and commercial names can be found on chromium.org website at: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices This it to make the names more relevant: towiki (in util/board_status/to-wiki/towiki.sh) will pick such names, which end up in the supported board list at: http://www.coreboot.org/Supported_Motherboards Change-Id: I2d705672d7202964fea3f62a5bd61a231d3f14c0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12652 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-12-17Kconfig: Fix CONFIG_GDB_STUB dependenciesDenis 'GNUtoo' Carikli
If we select CONFIG_GDB_STUB without CONFIG_SERIAL: build/console/console.romstage.o: In function `__gdb_hw_init': [...]src/include/console/uart.h:74: undefined reference to `uart_init' build/console/console.romstage.o: In function `__gdb_tx_byte': [...]/src/include/console/uart.h:75: undefined reference to `uart_tx_byte' build/console/console.romstage.o: In function `__gdb_tx_flush': [...]/src/include/console/uart.h:76: undefined reference to `uart_tx_flush' build/console/console.romstage.o: In function `__gdb_rx_byte': [...]/src/include/console/uart.h:77: undefined reference to `uart_rx_byte' Note that CONFIG_GDB_STUB should also work trough usbdebug, But due to the lack of testing, it has been disabled when added. This commit gives more information on the issue: f2f7f03 console: Add console for GDB Change-Id: I9accf8189dfd2c4ae379c03649d2e5863183457b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-17google/veyron: Indicate which boards are laptops.Denis 'GNUtoo' Carikli
This is to make towiki pick that information, to make these boards end up in the laptop list at: http://www.coreboot.org/Supported_Motherboards Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12716 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-17Drop src/cpu/ indirection for MIPSStefan Reinauer
Change-Id: I406166e650e07851ab1b293450fa29da8af075d9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12724 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17Makefile.inc: Include build/dsdt.d if it existsMartin Roth
The dsdt dependency file is created, but wasn't being used to determine whether or not to update the dsdt file. If it's present, include it into the makefile so dsdt.aml gets rebuilt if any of the depencencies change. Change-Id: I76bc22541c6b9740841bda891a5b88030cb949cd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-17soc/imgtec/pistachio: add implementation for system resetIonela Voinescu
Implement system reset by calling the watchdog soft reset. Following the soft reset, the SoC will reset to the same logic state and therefore have the same effect as a hard (power-on) reset except for: - watchdog scratch registers will be unaffected (hard reset will clear them) - the real time clock will be unaffected BUG=none TEST=tested on Pistachio bring up board Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12755 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17soc/imgtec/pistachio: Implement hard_reset()Stefan Reinauer
Verified boot needs hard_reset() now, so offer a dummy implementation for the Imagination chip. Sorry, I don't have the specs for this chip anymore to make a real implementation, but I would like to keep this code from bit rotting. Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12723 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17vendorcode: google: chromeos: Remove old fmap.c fileJulius Werner
This file became obsolete when FMAP code moved to src/lib/ and is no longer built by any Makefile. Let's remove it to avoid confusing people. Change-Id: I55639af28f9f3d4c4cb0429b805e3f120ecc374e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12753 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-12-17Makefile.inc: Document extract_nth and the fields it extractsMartin Roth
Change-Id: I0b5cffff95aca0ea0d6302b436797dada1850ba0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-17soc/intel/fsp_baytrail: Adjust root port INT routingMartin Roth
Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12684 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-12-16libpayload: add archive.hDaisuke Nojiri
archive.h is a header file for the programs which need to parse an archive created by 'archive' tool. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311201 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/12734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16intel/fsp_baytrail: change indent to use tabsBen Gardner
Change-Id: If0d0a15442738bab0e34f1b05513e7f8e8fa9afc Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-16northbridge/intel ACPI: Remove unused Local methodMartin Roth
The remainder of the divide operation was being placed into a Local, but was never being used, causing an IASL warning. Since this field is optional, just remove the Local. Fixes IASL warning: dsdt.aml 640:Divide (Multiply (CTDN, 125), 100, Local0, PL2V) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: I0b43ef638b1bc3e1163c45f31f8da57aa0d39e22 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12706 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-12-16toolchain.inc: print XGCCPATH if it's setMartin Roth
To help a user debug issues, print the current XGCCPATH value if it's set. Change-Id: I69afdd1c93cfd4747547ecad0d5e1ab4c87511b7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12677 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16x86/smbios: Return index 0 for empty stringsBen Gardner
Section 6.1.3 (Text Strings) of the SMBIOS specification states: If a string field references no string, a null (0) is placed in that string field. Change smbios_add_string() to do that. Change-Id: I9c28cb89dcfe2c8ef2366c23ee6203e15b7c2513 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16buildgcc: Add coreboot toolchain version to iaslMartin Roth
Add the coreboot toolchain version to iasl's version output. % ./xgcc/bin/iasl -v Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20150619-64 Copyright (c) 2000 - 2015 Intel Corporation coreboot toolchain v1.33 November 25th, 2015 This won't actually be checked until the next version of iasl so that we don't have to rebuild again for no reason. The buildgcc version was intentionally not incremented for this minor change. Change-Id: I03a1a777fdb84e34bfceb7b1eb43fffbc1f3a2fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16lib: Fix strncmpHannah Williams
strncmp continues to compare the characters in the input strings past any null termination it may encounter. Null termination check is added. Reviewed-on: https://chromium-review.googlesource.com/314815 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Hannah Williams <hannah.williams@intel.com> Tested-by: Hannah Williams <hannah.williams@intel.com> (cherry picked from commit ca7022752115eddbcb776f0c0d778249555ddf32) Reviewed-on: https://chromium-review.googlesource.com/315130 Change-Id: Ifc378966dcf6023efe3d32b026cc89d69b0bb990 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12721 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16intel/fsp_baytrail: rename include folder baytrail to include/socBen Gardner
This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:50:57 +0000