summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-09-17ifdtool: Const-correct and redesign some functionsBill XIE
Const-correct some functions which do not write back, and use pointers to access existing region_t variables. The last changeset is dismantled this time. This commit is only focused on const-correctness. Change-Id: I6d05418c8b32fa31dcd038a3e56f9aefe13fa9c4 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21288 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-17board_status: Add option to set cbmem pathDavid Hendricks
This allows the user to specify a custom path for cbmem on the DUT. Change-Id: I2c28737d6efaae238fd6831cd3d00b2142b39a4c Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/21565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-17cpu/x86/sipi_vector.S: Use correct op suffixDamien Zammit
clang wont compile `cmp` asm opcode because it's ambiguous, use the correct op suffix `cmpl` Change-Id: I82da5a9065b382e182dc7d502c7dca2fc717543b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-17via/cn700: Fix clang error with missing mainDamien Zammit
According to clang, main has no prototype for bcom/winnetp680 so add it into corresponding raminit.h Change-Id: I8a55267901986757a4fa88ee13460ffbed3eeadc Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16mb/google/poppy: Add lens_focus property for OV13858 camera moduleV Sowmya
Add lens_focus property with reference to VCM device for OV13858 camera module to register the corresponding v4l2 sub-device asynchronously. BUG=b:64133998 BRANCH=none TEST=Build and boot soraka. Dump DSDT and verified that it has the required entries and verified the camera functionality. Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21512 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-16google/lulu,gandof: set kb backlight on bootMatt DeVillier
Set keyboard backlight to 75% on boot, except when resuming from S3. This enables the backlight at a reasonable level prior to the OS driver taking over, providing early proof-of-life and enhanced usability in grub etc. Uses same method as other google boards with a keyboard backlight (chell, link, samus). 75% value determined based on user feedback. TEST: boot google/lulu,gandof boards, observe keyboard backlight enabled in pre-OS environment. Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16soc/intel/common: smm.h: Fix copyright yearJonathan Neuschäfer
Intel obviously didn't exist in 201 :-) Change-Id: I230d3b92ec6832fcea056fd3d099147002274d73 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16payloads/external: Clone GRUB2 over HTTPSJonathan Neuschäfer
Since the git:// protocol is unencrypted and unauthenticated, there's a security risk associated with using it: A man-in-the-middle attacker could replace e.g. the master branch with malicious code. Mitigate this risk somewhat by cloning GRUB2 via HTTPS. Change-Id: Ice8f8d108e7dfa1a1ecd58d9735944fa9570ace8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-16google/reks: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/reks (Lenovo Chromebook N22/N42) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new reks variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-reks-7287.133.B, commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16google/edgar: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/edgar (Acer Chromebook 14 CB3-431) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new edgar variant - Add common code to the baseboard which will apply to all variants other than cyan Sourced from Chromium branch firmware-edgar-7287.167.B, commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16mainboard/intel/glkrvp: Add support for audioHannah Williams
This patch adds the below: 1) Add correct SSP endpoint config for spk and headset 2) Update GPIO config for jack detection 3) Update GPIO config for I2S pins TEST=sound card binds TEST=cross checked SSDT entries from /sys/firmware/acpi/tables/ TEST=Jack interrupt works Change-Id: I32022ddacd79917730080889c040f842e0c9e6b9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16soc/intel/apollolake: Leave Hda enabled for GLKHannah Williams
Audio was disabled during initial stages, this patch enables back. It was disabled to unblock other validation tests. TEST=lspci lists audio controller Change-Id: I5d3872e86623763e20ee6464897f47792c731642 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/21529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16device/dram/ddr2: Fix decoding tRRArthur Heymans
Bit 7 is set on all options so only the default option in the switch statement is returned. Change-Id: I6a698ec9c15a2611a34c5965edf93638553775f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15mainboard/intel/cannonlake: Add ec entry into flashmapLijian Zhao
Add EC entries into chromeos.fmd file. BRANCH=None BUG=None TEST=Flash image and confirm system can get out of reset successfully. System will not be able to reach reset vector if flash map described in coreboot does not match intel flash map generated from fit. Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15util/scripts/cross-repo-cherrypick: improve cros-side rewritePatrick Georgi
Sometimes the BUG/BRANCH/TEST metadata isn't separated by a newline from the later git/gerrit metadata, which messes up further processing. Add that newline to minimize the amount of human intervention required. Change-Id: I37171bf6764b64e0ab0e81297a03f4d8b7744256 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15soc/amd/stoneyridge: Improve code qualityRichard Spiegel
Remove empty functions. In function pointer structure "device_operations", replace the 0 equality by NULL equality. Files: hda.c, sata.c and usb.c Change-Id: I9f8dc7681ab2e651872e69a8b2e990e59ebe80c9 Signed-off-by: Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21522 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15mb/google/poppy: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-15soc/intel/skylake: Move UNCORE PRMRR base and mask defines.Pratik Prajapati
UNCORE PRMRR BASE and MASK MSRs are not common, so move to SOC specific header file and rename the #define to start with MSR_* Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15soc/intel/common/sgx: use SOC specific API to get PRMRR base and maskPratik Prajapati
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask. Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21246 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15soc/intel/common/sgx: Define and use soc_fill_sgx_param()Pratik Prajapati
To remove chip.h dependency from SGX common code - Create API soc_fill_sgx_param() and use it in sgx.c - Implement same API for skylake/kabylake - define sgx_param structure Also include intelblocks/sgx.h instead of soc/msr.h Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15MAINTAINERS: Remove extra unnecessary spaceSumeet Pawnikar
Remove extra unnecessary space at end of line. Change-Id: I27688c3b8df71b875f1dc1020465d838756362be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/21521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15MAINTAINERS: Add Julius as LZ4 maintainerJulius Werner
I imported the LZ4 compression code and want to keep an eye on it to ensure that our sources stay in sync with upstream. Change-Id: I249ce24f6630d66d451d993198cd267478e5743e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15MAINTAINERS: Add INTEL FSP DENVERTON-NS SOC & HARCUVAR CRBMariusz Szafranski
Add Intel FSP Atom C3000 SoC ("Denverton" and "Denverton-NS") and Harcuvar CRB to the list. Change-Id: I1c4bfd0900e8d425b95b5ef6c541b1e988846667 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/21515 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-15google/cyan: convert to variant configurationMatt DeVillier
Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14mainboard/intel/cannonlake_rvp-u: Configure USB portsPratik Prajapati
Configure USB2, USB3 and Type-C ports for CannonLake-U RVP Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14mainboard/intel/cannonlake_rvp-y: Configure USB portsPratik Prajapati
Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14src/soc/intel/cannonlake: Define USB configuration paramsPratik Prajapati
Define USB2, USB3 and Type-C configuration for CannonLake. Change-Id: I42243950366d672e886158eb1934350f47b4ff1f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14siemens/mc_apl1: Add delay to wait for legacy devicesWerner Zeh
There are old legacy onboard devices which are too slow for a coreboot boot with log level BIOS_ERR. In this case coreboot is so fast that these devices do not have enough time to become visible on the PCI bus and this in turn leads to missing resource allocation for this devices. The most generic way to work around this problem on existing hardware is to introduce a delay right before the PCI enumeration starts. The needed delay time depends on the hardware and will therefore be get from hwinfo. Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-14timestamp: Add function to get time since bootWerner Zeh
Add a function to retrieve the elapsed time since boot. For that purpose use the base time in the timestamp table among with the current timestamp at call time of the function. So more precise the returned time is the elapsed time since the timestamp was initialized scaled in microseconds. This was chosen to get a reliable value even on platforms where the TSC might not be reset on software reset or warm start. Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14soc/intel/skylake: Implement UNCORE PRMRR get base and mask APIPratik Prajapati
Implement soc_get_uncore_prmmr_base_and_mask() API for SKL/KBL Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14soc/intel/apollolake: Implement UNCORE PRMRR get base and mask APIPratik Prajapati
Implement soc_get_uncore_prmmr_base_and_mask() API for APL/GLK Change-Id: I57df1f0e8ff984f32de4efdc6ebd68be501b4799 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14intel/common/systemagent: Add API to get SOC specific PRMRR base and maskPratik Prajapati
Implement weak definition and SOC specific code would implement actual definition. Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-14usbdebug: Fix init and add support for postcarKyösti Mälkki
It was originally designed such that if usbdebug_init() was called before cbmem_initialize(), it would fetch the already-initialized state from CBMEM. This changed when cbmem_find() behaviour changed to require cbmem_initialize() to be called first. As a result, ramstage had to reinitialize all of the EHCI controller and USB endpoints on entry. This was slow, specially with AMD hardware where one can scan USB ports to probe for the debug dongle. For postcar and ramstage, move usbdebug entry such that it is triggered from CBMEM_INIT_HOOK instead of console_init(). Side-effect of this is usbdebug console shows 'coreboot-xxx ... starting...' line only for romstage. Initialisation for usbdebug is never done in postcar. If you have USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on usb either. While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE and alike. Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13soc/intel/cannonlake: Add serialio device configLijian Zhao
Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13AGESA buildsystem: Reduce include path exposureKyösti Mälkki
Remove AGESA_AUTOINCLUDES -list from coreboot proper CPPFLAGS. Couple individual directories are now manually added to complete builds. Change-Id: I2595b87641c70e34e49fedf11b42f4961b0842dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13AGESA vendorcode: Remove AGESA_ENTRY_INIT_RECOVERYKyösti Mälkki
Deprecated and not used in our builds. Change-Id: I01773bb62b1599d18ad51d6f444abec46faec942 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13AGESA vendorcode: Move PlatformInstall.hKyösti Mälkki
All thse Option.*Install.h files are about configuring what eventually is referenced in the final libagesa build. It's self-contained so isolate these together with PlatformInstall.h to hide them from rest of the build. Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mb/google/soraka: Update DPTF parametersWisley Chen
Cloned from baseboard/dptf.asl and update the parameters for soraka. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU: passive point:85, critial point:100 TSR0: passive point:55, critial point:65 TSR1: passive point:58, critial point:70 TSR2: passive point:60, critial point:75 TSR3: passive point:60, critial point:75 2. Set PL1 Max to 7W, and PL1 Min 4.5W 3. Change sampling period of thermal relationship table (TRT) setting CPU: 5 seconds TSR0: 30 seconds TSR1: 30 seconds TSR2: 8 seconds TSR3: 8 Seconds BUG=b:65467566 TEST=build, boot on soraka, and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590 Reviewed-on: https://review.coreboot.org/21453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13agesa/f15tn: Remove unnecessary logic opDamien Zammit
One liner that fixes a warning with clang Change-Id: I4d7dfaa5fcf0e95acd650e4c129e0899b5d68f09 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-13rmodtool: Increase limit on number of symbolsDamien Zammit
An internal index `i` was previously allocated as Elf64_Half which is uint16_t. Bumping to uint64_t increases the number of allowed symbols and prevents a segfault in processing a larger ramstage.debug file. Also introduce a separate counter for the number of sections. Change-Id: I9ad2f64c452cef2e7bf957f766600891cb5ae798 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13amd/stoneyridge: Remove duplicate PCI definitionsMarshall Dawson
There were two copies of the same definitions in the file. Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13fsp1_0/fsp_util: Rename global symbol find_fspDamien Zammit
To avoid error with symbol redefinition (using clang): src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition ".global find_fsp\n\t" Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp. Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mb/google/soraka: Fine-tune USB 2.0 port4Wisley Chen
Fine tune usb 2.0 strength for port 4 to pass eye diagram. BUG=b:65306272 TEST=build on soraka, measure usb2.0 eye diagram, and result is pass. Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13nb/intel/i945/raminit.c: Replace numbers with macrosElyes HAOUAS
Use macro instead of numbers Change-Id: Ife1aff0a5cf311881b3a11533b71a74c518a633f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/21472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-13amd/stoneyridge: Remove multi-node supportMarshall Dawson
The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13amd/stoneyridge: Simplify SB link routingMarshall Dawson
Remove the check for the southbridge link from Stoney Ridge. The APU is an SoC which can never be installed in a multi-node system. It is pointless to detect and remember the sblink value, which is set by hardware and comes up 0. The BKDG marks this as a reserved field vs. documentation for multi-node-capable Family 15h devices. Because there is only one option for SB link now, relocate the register write done by set_vga_enable_reg() and remove the function. Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setupMarshall Dawson
Delete the check for sibling cores and the programming of CPUID HTT and CmpLegacy back-door bits. The code has no effect on modern Family 15h APUs. The bits being modified come up set out of reset. Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Remove PSP BAR init from cpu initMarshall Dawson
Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The BAR is configured in romstage by AmdInitPost(). Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Make cbmem_top SMM awareMarshall Dawson
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to HAVE_SMI_HANDLER. Change the value returned by cbmem_top() to carve out a range to be used by TSEG. The SMM Mask register has a granularity of 128KB but align the value to 16MB to keep down the number of variable MTRRs required. Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13util/lint: Exclude external payloads from coreboot lowercase checkMartin Roth
Change-Id: I70bbf37fad67fd9bda5724811f4bbdcc53779a42 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-13arch/x86: Fix typo with MTRRKyösti Mälkki
Change-Id: I67a470c2c2a659d5355fdd0939d0572c1ff3e291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13soc/intel/cannonlake: Add ramstage uart debug supportLijian Zhao
Use fixed resources for LPSS uart devices for debugging purpose. BUG=NONE BRANCH=NONE TEST=Boot up with coreboot rom, without this changes, serial log will stop print anything during PCI resourcre setup as MMIO address of UART will be re-assigned. Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13asus/p2b-ls,asus/p3b-f: Move to EARLY_CBMEM_INITKeith Hui
These two boards have been boot tested with EARLY_CBMEM_INIT and is good to go. Change-Id: I2e69901ed83502894f6794b3c1d7bab9aab95e51 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21351 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-13intel/i440bx: Implement EARLY_CBMEM_INIT supportKeith Hui
Implement cbmem_top() required for cbmem support in romstage. Boot tested on asus/p2b-ls. Boards to move to this setup in followup patches. Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20977 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-13google/snappy: Update EC keyboard backlight flag by SKU IDKevin Chiu
Set AP SKU ID by ec command EC_CMD_SET_SKU_ID to update EC keyboard backlight flag. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I1153aa0b89250c55f311dd93a01fcef47afd7292 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13ec/google: Add command to set APU SKU ID to ECKevin Chiu
EC needs to have command to set SKU ID from APU to support specific feature (ex: keyboard backlight) for variant board. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I8cd3b8f646d4134d6bfff2869f6df2d9c615c157 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13vendorcode/siemens: Add LegacyDelay to hwilibWerner Zeh
Add a new parameter to hwilib called LegacyDelay. It will be used to define a delay time to wait for legacy devices if coreboot is too fast for old and slow onboard devices. Change-Id: Id0386fdea0ecfb3c1ff6ec1c456071246529950a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13sb/intel/bd82x6x: Add time-stamp around ME DRAM updateNathaniel Roach
Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UARTV Sowmya
This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress for ACPI debug prints. TEST= Build and boot soraka and fetch the ASL debug prints. Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mainboard/intel/cannonlake_rvp: Include ChromeOS supportLijian Zhao
Add ChromeOS support for cannonlake_rvp platform. Change-Id: Ia02407da8ab4aac2c2c33a7796fc71aea12e2925 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mainboard/intel/cannonlake_rvp: Add dummy DSDT tableLijian Zhao
Add dummy ACPI DSDT table for cannonlake rvp platform. Change-Id: If45c2a7da7f5b20ddd3d56bf9d7f68a85d2f791d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao
Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13vboot: Add config to enable EC EFS supportDaisuke Nojiri
This patch makes coreboot set VBSD_EC_EFS flag if CONFIG_VBOOT_EC_EFS is set. Depthcharge/Vboot uses this flag to determine whether it can update EC when it's already running a RW copy. BUG=b:65028930 BRANCH=none TEST=Verify soft sync runs successfully on Fizz. Change-Id: Ic51ddd4819262162a8d8519461c4ace57ee01cb5 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21489 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-09-13Update vboot submodule to upstream masterDaisuke Nojiri
Updating from commit id 3f3a496a 2017-09-01 09:20:19 (image_signing: Fix loem.ini pattern for unibuilds) to commit id 753e34e9 2017-08-31 10:12:40 (futility: Make rwsig sign command produce EC_RW image) This brings in 5 new commits. This also updates Depthcharge stable commit ID. Updating from a843f262 2016-08-16 08:41:04 (kahlee: select emmc boot first if available) to commit id f3bb31fe 2017-08-15 17:15:33 (vboot: Support EC early firmware selection) This brings in 14 new commits. Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12mb/intel/dg43gt: Fix smbus IRQArthur Heymans
This board uses the reset defaults for DxxIP and DxxIR. The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family" mistakenly says in the D31IP register that all function have INTB as default. This is however not true as documented in the reset default value. This fixes the DSDT such that the SMBus device gets a route for the INT C interrupt it uses. Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21442 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12mb/intel/dg43gt: Select right gmbus port for VGA outputArthur Heymans
TESTED: NGI works on VGA with adapter on DVI-I port Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-12mb/intel/dg43gt: Configure clockgenArthur Heymans
This makes the VGA output on the DVI-I connector usable. This reuses vendor settings. Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-12sb/intel/i82801jx: Add smbus block operationsArthur Heymans
Change-Id: I1a84b4451efe25c1c3b0ce33ddbcb6ed06c29f9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-12AGESA boards: Clean up Ids.h and Filecode.h includesKyösti Mälkki
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Drop heapManager.h includesKyösti Mälkki
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA CIMX: Remove empty set_pcie_(de)resetKyösti Mälkki
For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA: Drop unused northbridge/commonKyösti Mälkki
Change-Id: I8c783e966cf90c6def28d87f07903f50a11487d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up some includesKyösti Mälkki
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12cpu/intel/slot_1: Increase CAR size to 8KiBKeith Hui
Because cpu/intel/car/romstage.c assumes a 8KiB stack size when setting up stack guards, and all Slot 1 compatible CPUs have enough L1 cache available for the increase. Adjust DCACHE_RAM_BASE to match. Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz Tualeron. The latter actually requires this patch to boot successfully. Change-Id: I5b440e7be4f3149378db88872872012c92049c20 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-12cpu/intel/car/cache_as_ram.inc: Fix long standing issuesKeith Hui
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. Do not set %ebp before and switch directly to stack returned by romstage_main(). Remove an unneeded 4-byte gap in CAR stack. The caching strategy for flash XIP area should be WRPROT. Clarify the various comments in the file on the logic. Together they lay the groundwork for bringing EARLY_CBMEM_INIT to intel/slot_1 boards. Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21503 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove unused codeKeith Hui
Remove CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore. Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21502 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove broken HT codeKeith Hui
Remove Hyperthreading related code that was missing setup of SIPI vector and did not work. Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21375 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11ec/lenovo/h8: Add WWAN detection supportPatrick Rudolph
* Add support for detecting WWAN. * Allows to turn off power to WWAN if no card is installed. Add the following devicetree values: * has_wwan_detection Set to one to indicate that the following register are sane. * wwan_gpio_num SB GPIO num to read. * wwan_gpio_lvl SB GPIO level for card to be present (usually zero). Don't enable WWAN power if no card is detected. As there are no devicetree values yet, the new code doesn't have any effect. Change-Id: Ie53275b384c85df8adf71fe79b3d54211c868756 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-11mb/lenovo/*/devicetree: Add BDC detection supportPatrick Rudolph
Add support for BDC detection, based on the schematics for each board. Support for boards without schematics needs further testing. Needs test on all boards. Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-11soc/intel/skylake: Fix SPI WP disable status checkRavi Sarawadi
Use SPI write protect disable bit from BIOS_CONTROL register to check write protect status. Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21449 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11soc/intel/common/block: Update common rtc codeLijian Zhao
Move rtc init code into common area and update the implementation for apollolake to avoid build break. Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11mainboard/intel/cannonlake_rvp: enable eMMCBora Guvendik
Set SCS emmc enable FSP parameter. Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21409 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-09-11payloads/coreinfo: Free buffer before returningMartin Roth
Fixes coverity issue 1373370 - Resource leak Change-Id: I71e0d3ae7f9152e1f89f8b3206526f0d344e0351 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-11kahlee: Add RO_VPD region in FMAPMarc Jones
The RO_VPD region is required for ChromeOS. BUG=b:65408869 TEST=Build and check coreboot.rom with fmap_decode. Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin
The original purpose of adjust_cpu_apic_entry() was to set up an APIC map. That map was effectively only used for mapping *default* APIC id to CPU number in the SMM handler. The normal AP startup path didn't need this mapping because it was whoever won the race got the next cpu number. Instead of statically calculating (and wrong) just initialize the default APIC id map when the APs come online. Once the APs are online the SMM handler is loaded and the mapping is utilized. Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-10nb/intel/i945: Clear timeout bits after disabling watchdogNico Huber
Even with the watchdog disabled, these bits influence other hardware blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet before they started). Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-10AGESA binaryPI: Remove heapmanager from romstageKyösti Mälkki
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved from romstage to ramstage, heapamanager in romstage is no longer needed. Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-10sb/intel/common: Fix HAVE_DEBUG_SMBUSKyösti Mälkki
Failed to build with DEBUG_SMBUS=y, slave_bytes is not initialized until inb(). Change-Id: Ia53717756ed74bc797a9529e36fc6965d6872101 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21470 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-10vboot: Use "Google_" as VBOOT_FWID_MODEL prefix if CHROMEOS is setFurquan Shaikh
CONFIG_MAINBOARD_VENDOR is customizable by OEM for Chrome OS devices. However, VBOOT_FWID_MODEL indicates the firmware vendor and hence if CHROMEOS is selected, then VBOOT_FWID_MODEL should always prefix "Google_" instead of CONFIG_MAINBOARD_VENDOR. BUG=b:65493192 Change-Id: I0a2280bfd6d535586bc14d9a3c4a8198287f08bc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-09-10amdfw: Clean up makefiles a bit moreMartin Roth
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig. - Remove 2nd set of variables that are duplicates of the first set. - Delete duplicate set of Prerequisites Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21451 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-09sb/intel/common: Add HAVE_DEBUG_SMBUSKyösti Mälkki
Change-Id: Ifb1a1eff71968f31af9004ff00717f202d3ec29e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09sb/intel/common: Fix i2c block commandKyösti Mälkki
Coding style, sync implementation with SMBus counterpart. Change-Id: I75f24e2308de945fc03289636ae914bb87070838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09sb/intel/common: Tidy up SMBus block commandsKyösti Mälkki
I forgot to push these changes before merging commit 1b04aa2 sb/intel/common: Fix SMBus block commands Change-Id: I7217f8c0cc78f2161faf31a4c49e3e9515026d15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09ACPI S3: Handle LATE_CBMEM_INIT boardsKyösti Mälkki
Followup removes inlined acpi_is_wakeup_s3() from PRE_RAM, and new implementation depends of CAR_GLOBAL. Change-Id: Iea1c5ab2175f8d496baa09bd6137cacc912df2cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09sb/amd: Support CBMEM_TOP_BACKUPKyösti Mälkki
Change-Id: I8d2005e4f2aa5a3b46e30f52556ee66aeb3d10cc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-08soc/amd/stoneyridge: Update amdfw buildMartin Roth
- The SMU firmware used to be named *.sbin, now is named *.csbin. Update the makefile so that the files can be named as they are delivered and don't have to be renamed. - Add a Kconfig option to allow the secure os binaries to be excluded. BUG=b:64932297 TEST=Build with old and new firmware, verify file sizes. Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-08soc/intel/braswell: add USB2 PHY PERPORTRXISET UPDKevin Chiu
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add USB2 phy setting overrideMatt DeVillier
Adapted from Chromium commit 9756af8. Create hook function to override USB2 phy setting from board level. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add SoC stepping identify helperMatt DeVillier
Adapted from Chromium commit 9756af8. Add SOC helper to identify BSW SoC stepping. Will be used to override USB2 phy setting based on stepping in subsequent commit. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 14:28:05 +0000