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2015-12-06Makefile: Individualize help targets & set as non-compile targetsMartin Roth
- Including the help targets in the list of NOCOMPILE targets means they can run even if the toolchain is mucked up. Since they contain info on building the toolchin, this is useful. - Separate the three current parts of the help target into individual components: help_coreboot, help_toolchain, and help_kconfig. This is mostly for the help_toolchin target which will be printed out by toolchain.inc. Change-Id: I365d95fd63e22bddd122fb1fede6f04270e03d63 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12542 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06SeaBIOS: remove VERSION variable in coreboot MakefileAlexander Couzens
SeaBIOS dropped support of VERSION variable and is reproducible without it. Change-Id: Iea1dc20e18aa5c274060e3cd55cd9e95086a602d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12645 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2015-12-05build system: add dependencies for GRUB2 and FILOPatrick Georgi
Make sure the build system knows how to start building the various integrated payloads we support. Change-Id: I2128d09c78795e0a41b055975e9f7052e3d951ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12641 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-05build system: Drop useless variable and dependencyPatrick Georgi
We don't need COREBOOT_ROM_DEPENDENCIES anymore because the dependencies are taken care of by the cbfs-files mechanism. REFCODE_BLOB also doesn't need to be an explicit dependency. Change-Id: I3f32cce79683e57a174724179bc2ac59a8cdda94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12648 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-04google/oak: Add timestamps in romstageYidi Lin
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963 Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add APIs for PMIC GPIO controlBiao Huang
BRANCH=chromeos-2015.07 BUG=none TEST=verified on Oak rev3 Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297224 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add mt6391 PMIC driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04build system: actually provide revision information in defconfigPatrick Georgi
The config file added to CBFS is the short version created by defconfig. The build system tried to add a header describing the version for quite a while now, but failed because it wrote to the file, then had kconfig overwrite it with the config data. While at it, rely on build.h and its version information instead of calling git manually. Change-Id: I5e4d6c857594a55432c05bf1480973fc950f4d4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12558 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04esd/atom15: import esd atom15 boardMichael Tasche
This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04intel/minnowmax: Fix IRQ connection for legacy uart at 0x3f8Michael Tasche
The E38xx legacy uart fires IRQ4, not IRQ3. PCI based IRQ A is switched from IRQ4 to IRQ3, to get a working IRQ for the legacy uart. Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744 Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12622 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-12-04external/Makefile.inc: Update SeaBIOS version fileMartin Roth
SeaBIOS updated how versioning is done, and out/version.c no longer exists. The new file with version information is autoversion.h. Change-Id: I10abee73ecc51e52c9ff7a2e7a9099339b1a4b40 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12567 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-04SeaBIOS: update stable release from 1.8.2 to 1.9.0Alexander Couzens
* The default boot menu key is now the ESC key (instead of F12) * Initial support for Trusted Platform Module (TPM) hardware and BIOS calls * Initial support for chain loading SeaBIOS from Grub (via multiboot support) * Initial support for booting from SD cards on real hardware * virtio 1.0 device support * The build will no longer include the build hostname or build time on "clean" builds. This makes the build binaries more "reproducible". * Basic support for running SeaBIOS on Baytrail Chromebooks * SeaVGABIOS improvements: * Improved support for old versions of x86emu (the "leal" instruction is now emulated) * Several bug fixes and code cleanups Change-Id: Ifbd50f1884959fed4c4f666b87f2ef7b4769c6d3 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12566 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04northbridge/amd/amdht: Reduce excessive romstage array sizeTimothy Pearson
Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12573 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04arch/x86/bootblock_normal: Update to use fewer registersMartin Roth
- Move initialization of entry to later in main. - Make boot_mode an unsigned char - no need to use int. - Remove unnecessary variable filenames. - Only get and try to boot fallback once. Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a Test: compiled. Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12574 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04cbfs: Fix typo in cbfs_prog_stage_load()Julius Werner
The proper return value to signal an error from cbfs_prog_stage_load() is -1, not 0. Change-Id: Ie53b0359c7c036e3f809d1f941dab53f090b84ab Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-12-04braswell/skylake: Add FspUpdVpd.h to fix compilationStefan Reinauer
Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins)
2015-12-04mainboard/biostar/am1ml: Force basic SPI read modeSergej Ivanov
This patch force AGESA to use basic SPI read mode. Without it board hangs during spi configure if W25Q32 chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/12580 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-03SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY optionMartin Roth
This has been replaced by the PAYLOAD_CONFIGFILE option, allowing any SeaBIOS config option to be set by a platform. Change-Id: I584c4c481266740840158baba76581d68e69b448 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12570 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabiosMartin Roth
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12569 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03payloads/external/SeaBIOS: Add option for saved SeaBIOS .configMartin Roth
Instead of adding various SeaBIOS options into the coreboot Kconfig, just add a way to use saved SeaBIOS .config files. These files can contain full SeaBIOS .configs, but is really intended for individual options. The coreboot Kconfig options take precedence over the settings in the saved .config. Change-Id: Ia7f9c76555b8e290777207b3f637c94c4d67a782 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12568 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03add support for power8 to xcompile scriptRonald G. Minnich
power8 is set up by ibm as a powerpc subset, so we follow that rule here: we call it a powerpc but require -mcpu=power8 Change-Id: Ib5212be22db9584b0dc0eeed5c06ec1924347067 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/12624 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Add board_id() and ram_code() implementationCC Ma
BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Implement the code which reads GPIOs for ChromeOS.Yidi Lin
BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Initialize the necessary pinsBiao Huang
BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/chell: update dptf TSR1 & TSR2 critial pointsWisley
update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add GPIO driverBiao Huang
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I54755d81144b27cc9a674434609b2d99f1d486ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d88a3ed43ad32e245e54a9599fb8667ce288217b Original-Change-Id: I1142091650c0de2207c7635031aa7edfe487ad88 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292672 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12603 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2CYidi Lin
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE from SRAM_L2C to ensure that it can be switched correctly. BRANCH=none BUG=chrome-os-partner47952 TEST=none Change-Id: I255a0116148777d384dda43682365a5e2375cb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792 Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313888 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12602 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03cbfs_spi: Initialize spi_flash when initializing cbfs_cacheMary Ruthven
Most devices do not use SPI before they initialize CBMEM. This change initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram cbfs cache so it is not overwritten when boot_device_init is called later. BUG=chromium:210230 BRANCH=none TEST=confirm that the first cbfs access can occur before RAM initialized and after on panther and jerry. Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/314311 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12601 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Coreboot GPIO changes for FAB 4.Saurabh Satija
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID, AUDIO_IRQ and BOOT_BEEP. BUG=chrome-os-partner:47513 BRANCH=none TEST=Built for kunimitsu but not verified on Fab 4. Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7 Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311806 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12600 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/glados: Disable kepler deviceDuncan Laurie
Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03google/chell: Update mainboard for EVTDuncan Laurie
- Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/skylake: Add ACPI device for audio controllerDuncan Laurie
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if it has been set in NVS. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on glados and chell Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313824 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12597 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/skylake: Remove unused code to add SSDT2Duncan Laurie
This code is doing nothing and is not needed. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313823 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/fsp: Add post codes for FSP phasesDuncan Laurie
Add post codes for the various FSP phases and use them as appropriate in FSP 1.0 and 1.1 implementations. This will make it more consistent to debug FSP hangs and resets. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados and chell Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547 Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313822 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12595 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/fsp1_1: Add accurate print for full fsp versionDhaval Sharma
Adding print for full fsp revision which includes: 0:7 - Build number 8:15 - Revision 16:23 - Minor version 24:31 - Major version BRANCH=NONE BUG=chrome-os-partner:46050 TEST=Built for kunimitsu and tested fsp revision is printed properly. Change-Id: If2739e7cccd97e4b39da503a9d61222cde03bc95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c49be46f8d2085a620abac74126de5c3b634e649 Original-Change-Id: I2223cce22fb3d39faa37902d415d5fdbe321add6 Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310173 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12594 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/lars: SPD change for Proto boarddavid
Update Memory ID for Proto board Update detection of single/dual channel memory to use SPD Index (Memory ID) Remove boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Build and Boot Lars (Proto) Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8 Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313903 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12593 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Updated Micron SPD dataBrandon Breitenstein
Updated Micron SPD data to correct values BUG=none BRANCH=none TEST=Tested on FAB 4 with Micron Dimm CQ-DEPEND=CL:312546 Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735 Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313003 Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com> Original-Tested-by: Freddy Paul <freddy.paul@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12592 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: FAB 4 update for Rcomp Target tableBrandon Breitenstein
Changed index 3 to be an exception of the default Rcomp Value BUG=None BRANCH=None TEST=Tested on FAB 4 SKU 1 Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622 Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/12591 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/Kunimitsu: FAB 4 SPD changesBrandon Breitenstein
Updated Memory IDs and SKU IDs for FAB 4 Updated detection of single/dual channel memory to use SPD Index (Memory ID) Added spd files for new dimms Removed boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Tested on FAB4 SKU1 and SKU3 Change-Id: I60403c0e636ea28797d94cff9431af921631323e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4 Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312546 Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com> Original-Tested-by: Freddy Paul <freddy.paul@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12590 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add PMIC wrapper driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Id1e9244e33e34c2c30d7c87cc277ecb7524dfb09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b21abfdaac4eeb2b65d4c0269ca0b9beff4b5e2f Original-Change-Id: I84de32de3a09e7857b0695759b49d4db5fde87ec Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292668 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add PLL driverJames Liao
Add PLL init code. BRANCH=none BUG=none TEST=none Change-Id: I2dcea8cdea1a3812bd8b84b7e8d961e7f8d4d953 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6e2eecb2fad30db018685b61912103f5e2cd524 Original-Change-Id: Id67d8033f3b2a267a140d7d73daa5727bc032272 Original-Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292670 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add a stub implementation of the MT8173 SoCYidi Lin
BUG=chrome-os-partner:36682 TEST=emerge-oak coreboot BRANCH=none Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292558 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03cbfs_spi: enable CBFS access in early romstageMary Ruthven
Currently the CBFS mmap cannot be accessed at the beginning of romstage because it waits until DRAM is initialized. This change first loads CBFS into SRAM and then switches to using DRAM as the backing once it is initialized. BUG=chromium:210230 BRANCH=none TEST=confirm that the cbfs can be access at the beginning and end of romstage on different boards. Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83 Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312577 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12586 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03arch/arm64: introduce mmu to bootblock and romstageJimmy Huang
We need mmu interfaces in these two stages for, 1. bootblock: to support mmu initialization in bootblock 2. romstage: to be able to add dram range to mmu table BRANCH=none BUG=none TEST=build pass Change-Id: I56dea5f958a48b875579f546ba17a5dd6eaf159c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf72736bda2233f8e0bdd7a8ca3245f1d941ee86 Original-Change-Id: I1e27c0a0a878f7bc0ff8712bee640ec3fd8dbb8b Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292665 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12585 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03arch/arm64: add DMA_COHERENT region macros to memlayoutJimmy Huang
BRANCH=none BUG=none TEST=build pass Change-Id: Ia997ce97ad42234ab020af7bd007d57d7191ee86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 604ac738e33fdfbaf093989ea13162c8506b9360 Original-Change-Id: I636a1a38d0f5af97926d4446f3edb91a359cce4c Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292551 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12584 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03libpayload: get cbfs offset & size for default media from lib_sysinfoDaisuke Nojiri
This change revives the path which was made inert by CL:308520. When media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer to a default media. Thus, get_cbfs_range does not set cbfs offset & size from lib_sysinfo. BUG=chrome-os-partner:47772 BRANCH=tot TEST=Tested on Jerry and Glados Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89 Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313205 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12583 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02cbfstool: Fix checkpatch errorStefan Reinauer
ERROR: code indent should use tabs where possible +^I trampoline_len);$ Change-Id: If46f977e2e07d73e6cfd3038912a172236a7e571 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12620 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02cbfstool: remove trampoline_start and trampoline_sizeStefan Reinauer
It's not needed, so we can remove some extra file mangling, too. Change-Id: I80d707708e70c07a29653258b4cb6e9cd88d3de3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12508 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02cbfstool: autocreate trampolineStefan Reinauer
Add the code necessary to create the linux trampoline blob. Don't enforce this for the in-coreboot build or use objcopy to produce linux_trampoline.o as it is a bit trickier to get all the details right than I had hoped: - you have to know the elf architecture of the host machine - you might have to have more tools (xxd, perl, etc) installed Change-Id: I9b7877c58d90f9fb21d16e0061a31e19fffa2470 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12505 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02drivers/intel/fsp1_1: Don't hide build related options behind HAVE_FSP_BINStefan Reinauer
The right thing to do is to hide them behind PLATFORM_USES_FSP1_1. The only things that should depend on HAVE_FSP_BIN is the code that actually adds the file to CBFS, and the path to the file in Kconfig. Removing the HAVE_FSP_BIN check requires some default values for two Kconfig variables. Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02util/nvramtool: Use correct virtual address when mapping tablesTimothy Pearson
The existing code used a stale pointer from a previously unmapped region of memory when parsing the coreboot tables. Use the correct pointer from the currently mapped memory region when parsing. Change-Id: Id9a1c70655fe25bc079e5bee55f15adf674694f8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12619 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Emit some build output while adding files to CBFSPatrick Georgi
Change-Id: I167f570957ca7eaf71fc31e1bd84b9bbad0683eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12551 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: drop one level of indirectionPatrick Georgi
coreboot.pre1 was generated then copied into coreboot.pre, now without any additional manipulation. Get rid of that extra step. Change-Id: I138567cadbc2fa1a6b6c988e34bdaae0e92d5554 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Add more files through cbfs-files instead of manual rulesPatrick Georgi
verstage, romstage, and payload can be added through infrastructure now. Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: make cbfs-files mechanism spaces-safePatrick Georgi
Space is commonly used as separator in make variables, so escape them as * (which should be reasonably uncommon in file names and cbfstool options alike to not be a problem). Change-Id: Ia77b5559841b5eae3aa1c0c0027f2e7fb882ea2f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Allow giving additional cbfstool options to cbfs-files-yPatrick Georgi
This enables adding romstage, verstage, and payload, that may need additional options (eg. for XIP or for linux initrd arguments) to be added with the build system infrastructure instead of manual rules. Change-Id: Ifde4ec3ca4ab436aca9b51a3c2cc478ed493fbfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02lippert/frontronner-af & toucan-af: Fix IASL warningsMartin Roth
Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. Fixes warnings for both platforms: dsdt.aml 1143: Method(_OSC,4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 1143: Method(_OSC,4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12530 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02kconfig_lint: Fix check_is_enabled for 2 symbols on the same lineMartin Roth
The previous code would miss the first of two IS_ENABLED(CONFIG_symbol) sequences on a line. This patch saves the rest of the line and loops to check any other entries on the same line of text. Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02kconfig_lint: Change from '$file at line $line' to $file:$lineMartin Roth
Combine the file and line number into a combination that editors understand when opening files. This makes it easier to edit the errors. Change-Id: Id2fae6a0a2ca8d726b95e252d80ac918f4edbe23 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12561 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02kconfig_lint: Separate errors from warningsMartin Roth
- Create subroutines for printing warnings and errors - Change all the existing warning and error routines to use subroutines - Add new command line options to suppress errors and to print notes Change-Id: I04893faffca21c5bb7b51be920cca4620dc283c3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12555 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02coreinfo: use coreboot crosscompilerMartin Roth
Set up coreinfo makefile to use .xcompile and the coreboot 32-bit cross compiler toolchain. Restrict to x86_32 gcc compiler. Tested in QEMU Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12454 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: replace files on UPDATE_IMAGEPatrick Georgi
So far the build system only added files starting with CBFS_PREFIX/ in the UPDATE_IMAGE configuration, but there are a number of files that exist in the global namespace (eg. config, revision, but also cmos_layout.bin). Now, existing files are removed if necessary. Change-Id: I977ff85fe18115c84268103be72e91ca854e62a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12581 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
2015-12-02toolchain.inc: Add IASL test as part of coreboot toolchainMartin Roth
Even though coreboot has IASL as part of its toolchain, it was not being picked up when testing to make sure coreboot is being compiled with the coreboot toolchain. This patch adds an iasl test when testing coreboot toolchain. Change-Id: I5b989869417c3f60057a91842b911855d9528f1b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12543 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-02toolchain.inc: Improve help messages for coreboot toolchainMartin Roth
Show better help text on how to compile the coreboot toolchain or use an unsupported toolchain. Change-Id: I64a2159d324d673784669b2464c1a2769b048678 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-02mainboard/intel/d510mo: Add Intel D510MO mainboardDamien Zammit
Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/10074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-02northbridge/intel/pineview: Add native raminitDamien Zammit
Does native ram init for Intel Atom D5xx 8086:a000 northbridge Tested on Intel D510MO mainboard, board boots linux kernel - Works fully with both dimms populated (2x2GB), memtest passes 100% - Almost boots with only one dimm in one of the slots (suspect bad memory map with one dimm?) - Reads garbage with only one dimm in other slot Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02northbridge/intel/pineview: Add remaining boilerplate code for northbridgeDamien Zammit
This patch does *not* include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-12-01southbridge/amd/sb700: Fix boot hang when AHCI mode disabledTimothy Pearson
Existence of requested PCI device was not checked when enabling IDE mode on the SP5100. Fix incorrect PCI device ID and check for device existence before attempting setup. Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 linksTimothy Pearson
Decision Feedback Equalization (DFE) is a form of dynamic link training used to lower the overall error rate within the coherent fabric. Enable it on all capable HT links. Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12072 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setupTimothy Pearson
The existing code did not properly detect various link attributes on Family 10h/15h processors. With the addition of new HT3- and IOMMU-specific code, proper detection has become critical to avoid system deadlocks. Fix and streamline link attribute detection. Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUsTimothy Pearson
The existing code re-used the Family 10h XCS buffer setup on Family 15h CPUs, which set incorrect values leading to random system lockups. Use the Family 15h XCS buffer setup shown in the BKDG. Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0Timothy Pearson
Minor change to be more explicit about the binary state of the iolink detect variable. Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12069 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-01nb/amd/amdfam10: Fix incorrect channel buffer count configurationTimothy Pearson
The secondary bus number set code incorrectly overwrote the link buffer settings in F0x[F4,D4,B4,94]. Constrain the secondary bus number set to the appropriate bits of the registers. Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01mainboard/asus/kgpe-d16: Enable GART by defaultTimothy Pearson
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01nb/amd/mct_ddr3: Add Family 15h tristate enable codesTimothy Pearson
The Family 15h DRAM initialization did not set up the various tristate enable codes in the MCT. Add Family 15h tristate enable setup. This fixes multiple DIMMs on a single channel. Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12060 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01amd/pi/00630F01: Drop HT3_SUPPORTMartin Roth
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented. This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT) Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12556 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-01Makefile.inc: make sure .xcompile is removed when building toolsMartin Roth
Most of the toolchain build targets already ran clean-for-update, but there were a few that didn't. Add the clean to those targets. Change-Id: I7faad32ac8bb1815e0c58e7d142ca2dbfc877896 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01build system: strip quotes from CONFIG_CBFS_PREFIX in a single locationPatrick Georgi
Instead of having to remember to strip the quotes everywhere so that string comparisons (of which there are a few) match up, do it right at the beginning. Fixes building the image with a .config where CONFIG_CBFS_PREFIX contains quotes. Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12578 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-11-30fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbolMartin Roth
The symbol BAYTRAIL_SMM was never valid (there's no config statment initializing the symbol), but it was being selected and used in the code. Now that SMM is supported in fsp_baytrail, the code it was trying to switch can be removed, and just set up for SMM. Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12553 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-11-30build system: add dependencies for SeaBIOS outputPatrick Georgi
Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12577 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-30nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training timeTimothy Pearson
There is no need to continue testing a DCT configuration after data errors have already been detected; this just wastes time during boot. Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12066 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30mainboard/intel: Add Little PlainsMarcin Wojciechowski
This adds a new mainboard: Little Plains for Intel's atom c2000 It was based on Mohon Peak board with some minor changes This board is not available as standalone product It is a managment board for Intel Ethernet Multi-host Controller FM10000 Series The FSP package is available from Intel: https://www.intel.com/fsp Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: https://review.coreboot.org/12503 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHzTimothy Pearson
The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, and in fact function when only one CPU package is installed, dual CPU package systems will lock up after around 6 - 12 hours of uptime due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks. If applications are not being used that stress the coherent fabric, then the uptime before hang may be much longer. Users attempting to overclock the HT links are advised to "burn in test" the HT links by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixesTimothy Pearson
Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12065 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins)
2015-11-30nb/amd/mct_ddr3: Use antiphase to better center DQS windowTimothy Pearson
The BKDG recommends the use of an antiphase window detection algorithm to ensure that the DQS data eye is properly centered. TEST: Booted both with DIMMs known to move the data eye into the prior clock phase and DIMMs known to keep the data eye in the current clock phase. Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12059 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbolMartin Roth
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually existed in the coreboot codebase. I didn't see anything that it might have been a typo of. Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12563 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-29nb/amd/mct_ddr3: Fix odd rank data corruptionTimothy Pearson
The odd rank of each DIMM could experience data corruption due to incorrect DQS training. Fix the DQS training algorithm by executing the relevant portions of the training algorithm on the odd ranks. Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12058 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select errorTimothy Pearson
Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12057 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly setTimothy Pearson
Also fix incorrect Trfc[0-3] value on Family 15h. Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12055 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29x86/smm: don't hide harmless declarationsPatrick Georgi
Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: move defconfig creation into a cbfs-files filterPatrick Georgi
That allows this special case to become a normal cbfs-files instance, too. Change-Id: I896ffebe4cec64c9c11605b4f09c7790e5419928 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12539 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: break overly long lines into logical unitsPatrick Georgi
Change-Id: I37b716acb305a79614cea184f57b8488111eab7a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12540 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: Move manual cbfstool add* invocations to cbfs-filesPatrick Georgi
Use cbfs-files-y to deal with some of the manually added cbfs files, providing more structure to that part of the build. Change-Id: Iee1b8fec81dfa5e5f0e55637a62e5f69bd0257ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12538 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: don't try to add cbfs-files with no backing filePatrick Georgi
Change-Id: Idd05a552762be92d0d93b357b96442b25a614757 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12537 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29build system: establish priority levels for CBFS file additionsPatrick Georgi
Add files with fixed positions, then files with alignment requirements and finally those that can reside everywhere to prevent the most obvious collisions. This isn't perfect yet (the "aligned" group may need some additional sorting), but should avoid the worst instances ("free floating" files allocating space required by fixed location files, for example). Change-Id: I871e1a92ad90e63fc4e299fe1b228b4b00a35930 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12536 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-28nb/amd/amdfam10: Work around sporadic lockups when CC6 enabledTimothy Pearson
The silicon in control of CC6 appears to contain minor bugs and / or deviations from the BKDG; through trial and error it was found that these issues can be worked around by reserving the entire possible CC6 save region, regardless of currently installed node count. Change-Id: If31140651f25f9c524a824b2da552ce3690eae18 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-28libpayload: Remove redundant 8250 MMIO32 UART driverAlexandru Gagniuc
The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-28baytrail: fix missing brackets around ir_base to fix IRQ routingAlexander Couzens
The missing brackets caused other registers, including the IO APIC enable bit (EAN in OIC) to be overwritten. Bug introduced by bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-27crossgcc/buildgcc: add parameter to show version number of toolMartin Roth
By adding the version number of tools, we can help people keep up to date with their tool versions. This will be used now to determine whether the IASL version being used is the version supported by coreboot. Change-Id: I24a68b01c819871f90403869570125e71b96bd70 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 20:25:46 +0000