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device) and sets the chipset voltage from 1.6V to 1.5V.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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LDN 7 and 9 are
changed, but also a SPI flash interface which has enable on bit1 and not bit0.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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from a sio_setup. As side effect I can now
have GAME and MIDI portsenabled.
It has been tested with my board. It produces same results.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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mine W83627EHF.
This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but
maps to original LDN and bit position in register 0x30.
VirtualLDN = origLDN[7:0] | bitpos[10:8]
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.7.tar.gz
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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specifying custom CFLAGS/LDFLAGS from the make command line like:
make CFLAGS="..." LDFLAGS="..."
I need to do this when building flashrom in a cross compiler environment
like buildroot for a foreign target.
Signed-off-by: Clark Rawlins <clark@bit63.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Remove the "enable write to flash" message, as the caller appears to
already report that.
- Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
we get an error there already.
- Rename a perror string from "read" to "read msr", as we use the latter
already in this function for another read.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, move a big code comment to the top of enable_flash_cs5536().
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot Flash Chip Select).
We need to write enable it in the NORF_CTL MSR register for flashrom to
be able to write to it, including JEDEC probe commands.
This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
the DBE61.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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breaks buildrom.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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them to coreboot.rom
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The patch was followed by these svn commands:
svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force src/mainboard/emulation/qemu-i386/
src/mainboard/emulation/qemu-x86
svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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architectures supported by buildrom.
Myles
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Programmable Micro Corp (PMC) need this.
Both the serial and parallel flash JEDEC detection routines would
benefit from a parity/sanity check of the vendor ID. Will do this later.
Add support for the PMC Pm25LV family of SPI flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I think that since the directory specifies the architecture and the
board, it is redundant information to name it something else, and it
makes it more difficult to automate the build process (buildrom).
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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following mainboard files had identical Geode LX specific print_conf()
implementations:
mainboard/amd/db800/mainboard.c
mainboard/amd/norwich/mainboard.c
mainboard/digitallogic/msm800sev/mainboard.c
mainboard/pcengines/alix1c/mainboard.c
Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs.
Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
interface of the IT8716 SIO chip.
Changes :
1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
functions of a PNP device can have more than 12 resources (ex the GPIO function
of IT8716f), in which case one could have an "array overflow" inside the device
structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
device init time..)
2) - define resource masks for the GPIO function in
src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
by the init code
3) - enable the flash SPI interface into
src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
into the GPIO function). I know that this is problematic because not all m57sli
boards are SPI, but .. do anyone have a better idea how to handle this?..
Signed-off-by: Florentin Demetrescu <echelon@free.fr>
I (Ward) have verified your patch on a rev2 of this board (it works!) as well
as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse
side effects that I noticed, so I think this patch should go in.
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Tested on actual hardware by Sergei Antonov <saproj@gmail.com>.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Sergei Antonov <saproj@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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for each output device we support, so the payload can figure out
where to find consoles that the user cares about.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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DISTRO_CFLAGS were not being
included on the CC line for cache_as_ram_auto.c
Tested on ubuntu, where formerly it failed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(unlike 5 lines later where make syntax is emitted into a file)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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about a serial port. If a port is defined in the board configuration,
add it to lbtable.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Update website URL to http://coreboot.org/Lxbios.
- Use svn:keywords property to actually expand the $Id$ entries.
- Update COPYING to the latest version from
http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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working.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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That fixes a compilation failure.
Signed-off-by: Marc Karasek <marc.karasek@sun.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying.
"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write...
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.
This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.
"MX25L8005 found at physical address 0xfff00000.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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programming.
Minor formatting changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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are already in use, the patch uses 'R' (for release) and, of course,
'--version'.
Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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image. Even if the rom image size is not changed, it can make the linking fail.
It's almost a heisen-bug, only there if you don't watch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the impression that the cheetah on fam10 is broken just because we're using a
too new compiler for abuild. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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patch is tested on actual hardware.
As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).
So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I have test that on my board, it works ;)
Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Super I/O performing LPC-to-SPI flash translation.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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supported by superiotool (closes #91).
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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suspend clock (undocumented in datasheet, documented in 'W83627HG-AW').
Introduce sio_init function for all this.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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C7 bios programmer's guide explicitly states they're not necessary, and
leaves it at that. Even if they are possible and exist, we don't have
any info on it, nor any updates, so drop these unneeded references.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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After the patch [...] The line length is still below 80 characters.
Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For the old supported CAR sizes, the newly generated code is
equivalent, so it should be a no-brainer.
Benefits:
* a nice code size reduction
* less #ifdef clutter for Family 10h
* paranoid checks for CAR size
* clear abstractions
This has been tested by Marc Jones and Jordan Crouse.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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in GA-2761GXDK mptables.c.
Thanks to Torsten Duwe for initial code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: 蔡明耀 (Morgan Tsai) <my_tsai@sis.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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No code lines affected, so svn blame will not be messed up.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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generic x86 CAR code. For the old supported CAR sizes, the newly
generated code is equivalent, so it should be a no-brainer.
Add a copyright header to the code, the header is derived from the one
found in the same piece of code in v3.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Normalize used locale to "C" before parsing output.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Straight from the data sheet, not tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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similar smp_write_intsrc calls in preprocessor macros.
Also add some comments about the actual devices the INTs
belong to.
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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rather independent, lift the implicit (broken) assumption that
CONSOLE_VGA would also run the ROMs, and transfer it to a new
config option VGA_ROM_RUN.
This change is minimally intrusive, because all board configs
that previously assumed CONSOLE_VGA would also run the ROMs
didn't compile, they had to also specify PCI_ROM_RUN.
Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
(separate ROM_RUN from VGA console).
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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unknown.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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exactly the same ID. Improve model number printing.
Add EN29F002(A)(N)B support while I'm at it.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Markus Boas <bios@ryven.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.
(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)
Add support for EON EN29F002AT.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.
This patch should have no effect on code generation.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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mainboard directories, but the code was not referenced anywhere.
intel/jarrell
dell/s1850
supermicro/x6dhr_ig2
supermicro/x6dhr_ig
supermicro/x6dhe_g2
supermicro/x6dhe_g
Besides that, the contents of these files were either duplicates of
src/cpu/intel/model_f3x/microcode_M1DF340E.h or
src/cpu/intel/model_f3x/microcode_M1DF3413.h.
svn remove the following files:
src/mainboard/supermicro/x6dhe_g/microcode_updates.c
src/mainboard/supermicro/x6dhe_g2/microcode_updates.c
src/mainboard/supermicro/x6dhr_ig/microcode_updates.c
src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c
src/mainboard/dell/s1850/microcode_updates.c
src/mainboard/intel/jarrell/microcode_updates.c
Abuild tested, as expected no failures.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be nice, though.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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data sheet.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18
(verified on an v1.0 board).
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It's easier to tell users "copy your payload to /tmp/filo.elf" than have
them guess paths or modify Config.lb files etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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using the default from src/mainboard/*/Options.lb (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Removed local APIC INIT (don't worry the APIC and AP are still initialized).
The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
The Intel Multiprocessor specification indicated that a vector should be set
and a START should happen following an INIT. Then AP will execute the
instructions pointed to by the vector. There is no vector or start in
stop_this_cpu(). This seems to put the AP in an in-between state. In the case
of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
debugger.
The better solution seems to be to just put the AP in a hlt and allow the AP
to go into C1. Then APIC managing software running on the BSP can program the
AP as needed.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets and double checked.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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this is needed (at the very least) to make FILO work on these boards.
Disable UDMA/33 per default, which is slower but the safe choice, as we
don't know which IDE devices a user has attached, and some don't support
UDMA/33 very well or at all.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Print status register before erase to help debugging block locks.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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