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2020-12-14soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BPSridhar Siricilla
The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob and CSE RW boot are different. TEST=Verified on drawcia. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/braswell: Use Kconfig value for TSEG sizeAngel Pons
SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also, use SMM_TSEG_SIZE in place of a magic number. Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/braswell: Clean up devicetree settingsAngel Pons
Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero PowerLimit4 dt settingAngel Pons
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway. Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop never-set DdrFreqLimit dt settingAngel Pons
Only Google Eve uses a non-zero value, but it overwrites in C code. Drop the devicetree setting, since no mainboard uses it. Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/xeon_sp/skx: Hook up microcode blobArthur Heymans
TESTED on ocp/tiagopass: Microcode updates are properly applied (via FIT). Tested with out of tree patches to report the revision. Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14soc/intel/skylake: Drop unreferenced PttSwitch dt settingAngel Pons
The value for this setting is not used anywhere. Drop it. Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/purism/librem_cnl: move setting of FSP-M UPDs into variant.cMatt DeVillier
The upcoming Librem 14 variant won't use the same SATA HSIO adjustments as the Librem Mini, so move these settings into a variant-specific file. Rename existing gpio.h to variant.h, move to board root directory, and use for all variant-specific declarations; adjust references as needed. Add newly-created variant.c to Makefile. Test: build/boot Librem Mini, verify SATA functionality unchanged. Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48519 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/xeon_sp: Configure DPR on all stacksArthur Heymans
Configure DPR to span the region between cbmem_top and TSEG base. This region was already unavailable to the OS. Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14arch/x86: Combine bootblock linker scriptsKyösti Mälkki
Packing bootblock sections is somewhat easier to understand when these all appear in one .ld file. Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14nb/intel/ironlake: Add comment about MCH scan chainsAngel Pons
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14nb/intel/ironlake: Remove unused constantAngel Pons
Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48562 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14src/lib: Add Kconfig option for SPD cache in FMAPMatt DeVillier
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14drivers: Replace multiple fill_lb_framebuffer with single instancePatrick Rudolph
Currently it's not possible to add multiple graphics drivers into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics drivers can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace all duplications of fill_fb_framebuffer and provide a single one in edid_fill_fb.c. Should not change the current behaviour as still only one graphic driver can be active at time. Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/tigerlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I5f5da8dfcec7dd35981611830b555cab5d6af3e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48572 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/jasperlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/icelake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I6ce43071c95eeb41c35ddfdb734db52d863ea8e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/elkhartlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ia928c4bbddd1c160228a9af8faf5d4be787f73f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/cannonlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ia9c8347cad479c6b4e678630921f768e0fdee6d9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/alderlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14intel/common/block/lpc: Add new device IDs for Emmitsburg PCHJonathan Zhang
Add LPC/eSPI device ID of Emmitsburg (EMB) for setting LPC resources. Refer to Emmitsburg PCH EDS (606161). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie5a5d9ba7e4f664ada2dae2294d6e4d0280a2157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14Doc/mb/lenovo: Explain simpler GM45 flash method firstAngel Pons
Do not mislead newcomers into thinking the GM45 series laptops are hard to flash. Describe the simple coreboot flashing procedure first, then explain how to remove the ME firmware and use a custom flash layout. Also, reword a sentence on the simple flashing procedure for clarity. Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14Doc/mainboard: Sort Lenovo laptop generation groupsAngel Pons
GM45 is older than Arrandale, so swap their order. Change-Id: I5b94d940c0378dd561535257d3352700fd482527 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14mb/google/glados/var/caroline: Drop zero setting from dtAngel Pons
Unset devicetree options already default to zero. Note that this setting is not referenced anywhere else, and will be removed in a follow-up. Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48579 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/intel/ehlcrb: Remove unrelated Kconfig settingsTan, Lean Sheng
Update Kconfig to remove unrelated configs inheritted from JSL_RVP. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48544 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update IRQ routing settingsTan, Lean Sheng
Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update USB & PCIe devices in ASL filesTan, Lean Sheng
Update USB & PCIe devices in ASL files as per EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update USB_PORT_MID pin settingsTan, Lean Sheng
Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values for USB_PORT_MID. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48541 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update SerialIO devices detailsTan, Lean Sheng
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS. Also update device function number for GSPI #2 in asl file. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update HECI Control Status Register settingsTan, Lean Sheng
For EHL, SpiProtectionMode is added to HFSTS register #1. The original Manufacturing Mode is detected via FpfSocConfigLock instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode, and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update PCI device definitionTan, Lean Sheng
This change updates PCI device definition according to EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48444 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/mediatek/mt8192: Add ddp driverYongqiang Niu
Add ddp (display controller) driver that supports overlay, read/write DMA, etc. The output goes to display interface DSI, DPI or DBI directly. BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46577 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/mediatek/mt8192: Enable dsi driverHuijuan Xie
Enable dsi driver for display. BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com> Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46574 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/mediatek/mt8183: Move dsi driver to common/Yidi Lin
The mt8183 dsi driver can be shared with mt819x SoC. Move dsi.c to common/ folder and rename it to dis_v2.c to differentiate it from mt8173's dsi driver. TEST=emerge-kukuki coreboot Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-14soc/mediatek/mt8192: add i2c driver supportQii Wang
Add I2C controller for MT8192, and revise the common I2C driver to support I2C controller running in APDMA async mode. In that case we have to initiate a different handshake protocol and reset I2C differently. BUG=b:155715435 TEST=Asurada boots up to shell Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-13mb/google/kahlee: move SMI/SCI GPIO setup to ramstageFelix Held
SMIs and SCIs aren't used before ramstage or the OS, so there should be no need to already set them up in romstage. Not using this GPIO configuration functionality allows untangling the GPIO and smi_util code and only linking smi_util in ramstage in follow-up patches. In romstage the pins get initialized as inputs with pull-up, so that at least that part still matches the configuration before this patch. BUG=b:175386410 Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-13soc/amd/*/include/spc/gpio: fix pin numbers in commentsFelix Held
Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-13soc/amd/common/block/gpio: use all-y in MakefileFelix Held
Change-Id: Ib77e3d088cc07da4e43a63afb863bb90796f9a37 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-13soc/amd/cezanne: add caching setup in bootblockFelix Held
The code can likely be factored out to common code, but since I'm not entirely sure yet that there will be no differences, I'll copy for now instead. Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-13nb/intel/sandybridge: Clean up program_timingsAngel Pons
Clarify the clock, command and control programming sequence. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47770 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12soc/amd/common: Remove SMBus host word accessorsKyösti Mälkki
SMBus controller has byte-wide registers. Remove the word accessors. Change-Id: If396108308bc8303d84458039b9529ecd83276c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-12soc/amd/common: Refactor ACPIMMIO posted writesKyösti Mälkki
Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12Revert "src/amd/common: Exclude biosram from psp_verstage"Kyösti Mälkki
This reverts commit f38af663d2c2c854859715803da249e6c24032db. The build error was a spurious ENV_X86 guard in <cbmem.h> that called for a different clean up. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43067 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12nb/intel/sandybridge: Clean up stepping logicAngel Pons
Do not combine the host bridge device ID with the CPU stepping because it is confusing. Although Sandy/Ivy Bridge processors incorporate both CPU and northbridge components into the same die, it is best to treat them separately. Plus, this change enables moving CPU stepping macros from northbridge code into the CPU scope, which is done in a follow-up. Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-12nb/intel/sandybridge: Fix blunder in MR2 shadow codeAngel Pons
Commit 7f1363d9b4 (nb/intel/sandybridge: Program MR2 shadow register) has a bug where the system locks up and power cycles when booting Linux, but is still able to pass memtest86+ with flying colors. The issue will occur when the following conditions are true: - CPU is Ivy Bridge - Memory speed is not greater than 1066 MHz (DDR3-2133 or slower) - System contains dual-rank DIMMs - The second rank of the dual-rank DIMMs is mirrored - All DIMMs support Extended Temperature Range - At least one of the DIMMs does not support Auto Self-Refresh If all of these conditions are met, the final value of the MR2 Shadow registers configures the memory controller to issue a MRS command to update MR2 before entering self-refresh mode, but indicates that rank mirroring is not required (the first rank on a DIMM is never mirrored). Before the memory controller enters self-refresh, it sends MRS commands to all ranks to update MR2, but the missing address and bank mirroring means DRAM chips on mirrored ranks instead clobber MR1 with junk data. With garbage in MR1, the mirrored ranks no longer function properly, which ultimately leads to all hell breaking loose (undefined behavior). The condition is backwards, since only odd ranks can be mirrored. To avoid this problem completely, simply remove the condition. The final register value will still be correct, since the bits are always ORed. Tested on Asus P8Z77-V LX2, fixes booting Linux with dual-rank DIMMs. Change-Id: Iceff741eb85fab0ae846e50af0080e5ff405404c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-12mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8Subrata Banik
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable TEST=Able to detect PCIE SD card on 0x1 slot. Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12drivers/ipmi: Handle the condition when (dev->chip_info == NULL)Bill XIE
Some former commits (e.g. Ieb41771c75aae902191bba5d220796e6c343f8e0) blindly assume that dev->chip_info is capable to be dereferenced, making at least compilers complain about potential null pointer dereference. They might cause crash if truly (dev->chip_info == NULL). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I1d694b12f6c42961c104fe839d4ee46c0f111197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-11amdfwtool: Register APCB and APCB_BK respectivelyZheng Bao
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the same file. For picasso, they are. For later programe, they are not. Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11util/amdfwtool: Fix EFS generation polarityMarshall Dawson
The DWORD used to indicate the Embedded Firmware Structure's generation uses 1 to indicate a first-gen structure, e.g. a SPI device's erased value of 0xffffffff. A 0 in bit 0 is how Client PSPs will interpret the structure as designed for second-gen. This change and the original addition should have no effects on any current products as none interpret offset 0x24. BUG=b:158755102 TEST=inspect EFS in coreboot.rom Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11lib/fmap: Add null parameters handlingJakub Czapiga
Prevent null-pointer access when passed as parameter. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie712d040b1c2383dcc8884e5f779c3591ccf0163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-12-11mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only padsMichael Niewöhner
There is a whole bunch of pads being configured by the vendor firmware that are either unconnected due to unpopulated resistor pads, only connected to test points for vendor debugging purposes or just used as strap. Configure them as NC with an appropriate pull to disable the RX/TX functions. The pads have been determined by dissecting a dead board. This patch has been tested thoughroughly on a machine, normally used productive, to see if any issues arise. No problems occurred at all. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11hatch: enable genesis PCIe/USB devicesJoe Tessler
Updates PCIe registers and GPIO CLKREQ lines to match the schematic. BUG=b:173566597,b:173567124,b:173566890 TEST=build AP firmware; flash device BRANCH=none Change-Id: Ibf519b812022839f749e503436f097d3b48c4383 Signed-off-by: Joe Tessler <jrt@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11soc/amd/picasso: Add data fabric read helper functionJason Glenesk
Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/picasso: move chipset_handle_reset to commonFelix Held
The FSP integration code needs this function to be present. It's not supposed to be called, but if it is, it'll print an error and call the SoC's cold reset function. Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11mb/google/volteer: Clean up romstage and ramstage UPDsTim Wawrzynczak
Move the manual calls to fw_config_probe() into the devicetree; the AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are already guarded with probe statements in the baseboard devicetree, so the code in romstage.c was redundant. The variants seem to have their USB4 probe statements correct as well, so the manual UPD setting in mainboard.c was also unnecessary. BUG=none TEST=abuild google/volteer Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11mb/google/volteer: Make use of fw_config_is_provisioned()Tim Wawrzynczak
In cases when a volteer device is unprovisioned, the safest thing to do for GPIOs that will normally be used for audio codec buses is to leave them disabled (configured as PAD_CFG_NC). This patch adds support for that. BUG=none TEST=add debug print to new if branch; remove fw_config from CBI and see print on console Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47972 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisionedTim Wawrzynczak
A mainboard might want to configure some things differently when a device is in an unprovisioned state. In the case when fw_config comes from the Chromium EC, an unprovisioned device will not have a FW_CONFIG tag in its CBI. This patch will set the fw_config value to UNDEFINED_FW_CONFIG in the case of an error retrieving the value, as well as adding a function, `fw_config_is_provisioned()` to indicate the provisioning status. BUG=none TEST=remove fw_config from chromium EC CBI, add code to mainboard to print return value of fw_config_is_provisioned() (`0`), add fw_config back to CBI, run same test and see `1`. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib3046233667e97a5f78961fabacbeb3099b3d442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47956 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/intel/common/block/acpi: Skip UART debug table if not usedMarc Jones
Skip the ACPI UART debug table if common block UART isn't selected. Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48247 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11Kconfig: Show console debug options if loglevel override is setMarc Jones
Show console debug options that would only be available if console SPEW was selected when the override loglevel option is selected. Change-Id: I2fb22562688d6b0bc9235c9ebe5d427dc2a67767 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-11soc/intel/common/block/lpc: Move southbridge_write_acpi_tables declarationMarc Jones
Move the southbridge_write_acpi_tables declaration from acpi.h to common lpc_lib.h, as common LPC is always the caller. This removes a duplicate declaration since all soc/intel devices use common LPC, but not all use common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c with the other acpi functions. Note that this would have the reverse problem if there is ever a non-common LPC device. Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11sb/intel/x/smbus.c: Factor out common codeAngel Pons
Since common smbus.c gets built for romstage as well, create a new file to hold this common code. Account for ICH7 not having a memory BAR, too. Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11sb/intel/bd82x6x: Drop invalid SATA registersAngel Pons
Code was copy-pasted from older chips and has no effect on bd82x6x. Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47099 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/ocp/deltalake: Update GPIO configurations according to schematicsJingle Hsu
On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH (C621A) by util/inteltool and generate the header file by util/intelp2m. The DVT and EVT GPIO configurations are the same. The initial value of GPP_B20 (POST complete) should be high, otherwise BIC would get incorrect sensor readings and see events like PCH prochot. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229 Reviewed-by: Tim Chu <Tim.Chu@quantatw.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11util/cbfstool/fit.c: Add support for adding Boot Guard manifestsMichał Żygowski
Change-Id: I8221590cad16cffea3f8b50dd880a77934b78ea8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-11device/Makefile.inc: Do not require hda_verb.cAngel Pons
A mainboard-level hda_verb.c may not exist for variant setups. Change-Id: If2c92d9498cba7c084ef4c7065bc4ae83c7da761 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-11sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm`Angel Pons
There's no need to compare the vendor ID. Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45258 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11Drop many cases of .previous directive useKyösti Mälkki
Since most assembly files are no longer concatenated together but built separately, section changes with .previous at the end of the files have become spurious. TEST=BUILD_TIMELESS Change-Id: I2970eed2b114a53475ba385eec4e97bb7ae7095c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-11Makefile.inc: Remove the CBNT bootblock flagArthur Heymans
At the moment this was only used for aligning the bootblock to 64 bytes. At the moment this automatically done with CONFIG_C_ENV_BOOTBLOCK_SIZE. Change-Id: I0c879119e525b512eebe3f4c5ff9b2f426c6b6ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-11Docs/cbfstool: Add details about memory mapped window handlingFurquan Shaikh
This change adds details memory mapped window handling in cbfstool required for x86 platforms. It also captures the details about the newly added support for multiple decode windows. BUG=b:171534504 Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-11mb/google/volteer/variant/lindar: Correct IOM port configurationKevin Chang
Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip. BUG=b:173093980 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbinFrankChu
In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_tableAlex Levin
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset bluetooth on reset. BUG=b:171085081 TEST=volteer2 boots; scope shows assertion of the signal Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-12-11soc/amd/picasso: factor out write_resume_eip to common codeFelix Held
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: move UART console code to common folderFelix Held
Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: move UART Kconfig options to common folderFelix Held
The actual UART initialization code will be factored out in follow-up commits. Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UARTFelix Held
This allows factoring out the common initialization for the integrated UARTs. Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/piasso,cezanne: add warning about using all-y in Makefile.incFelix Held
all-y will also add a compilation unit to the verstage on PSP build that runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't have verstage on PSP support yet, but since it'll eventually land it doesn't hurt to already add the comment now. Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: use all-y for aoac targetFelix Held
Since aoac gets also linked into verstage on PSP, all-y can be used here. Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48506 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if usedFelix Held
FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in this case. Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48485 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10lib/edid_fill_fb: Support multiple framebuffersPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel and Aspeed on server platforms or Intel and Nvidia on consumer notebooks. The goals are to remove duplicated fill_fb_framebuffer(), to advertise multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Add an implementation in edid_fill_fb that supports registering multiple framebuffers, each with its own configuration. As the current code is only compiled for a single graphics driver there's no change in functionality. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPMDuncan Laurie
Configure the CFG2 register to set the latency to <64us in order to ensure the L1 exit latency is consistent across devices and that L1 ASPM is always enabled. This moves the setup code from device init to device enable so it executes before coreboot does ASPM configuration, and removes the call to pci_dev_init() as that is just for VGA Option ROMs. BUG=b:173207454 TEST=Verify the device and link capability and control for L1: DevCap: Latency L1 <64us LnkCap: Latency L1 <64us LnkCtl: ASPM L1 Enabled Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10drivers/intel/fsp1_1/cache_as_ram.S: Correct commentFrans Hendriks
Stack is set up for bootblock. Tested on Facebook FBG1701. Change-Id: I0dd3fc91c90bf76e0d93925da35dc197d68d3e88 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47802 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/google/zork: Remove unsused codeMathew King
Remove unused code that appears to be left over from grunt. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/google/volteer: Fix a few devicetree device refsTim Wawrzynczak
Commit b0e169ac85 included a few small omissions and typos when converting 'device pci xx.y' to 'device ref blah' after adding the new chipset.cb file for TGL. This patch fixes these errors: 1) MIPI camera support requires I2C2 & I2C3 enabled 2) Malefor SAR sensor is on I2C2, not I2C3 BUG=b:175165653 TEST=abuild -p none -t google/volteer -x -a -c max Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-10soc/intel/tigerlake: Check TBT & TCSS ports for wake eventsTim Wawrzynczak
Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes, so add checks for wakes from these devices in pch_log_pme_internal_wake_source. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/common: Adapt XHCI elog driver for reuseTim Wawrzynczak
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS or North XHCI block has a similar enough PCI MMIO structure to make this code mostly reusable. 1) Rename everything to drop the `pch_` prefix 2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI controller 3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI controller BUG=b:172279037 TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via EC; type on keyboard, verify it wakes up, eventlog contains: 39 | 2020-12-10 09:40:21 | S0ix Enter 40 | 2020-12-10 09:40:42 | S0ix Exit 41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1 42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109 which verifies it still functions for the PCH XHCI controller Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/xeon_sp/nvs: Use common global NVSMarc Jones
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there isn't anything uncommon with the soc NVS, use the Intel common NVS. This covers the NVS cases of common code used by xeon_sp. Update the mainboards for this change. Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-10sb/intel/bd82x6x: Make me_common.c a compilation unitAngel Pons
We need to make most things non-static so that the code builds. Also, we need to update ibexpeak as well, because it borrows files from bd82x6x. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42019 Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.hFelix Held
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10sb/intel/x/smbus.c: Add block read/write supportAngel Pons
Copy and paste the i82801gx code onto all newer southbridges. This will be factored out into common code in a follow-up. Change-Id: Ic4b7d657865f61703e4310423c565786badf6f40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10sb/intel/x/smbus.c: Rename parameterAngel Pons
This is for consistency among the various southbridges. Change-Id: Id0dcfeef6e220861212ce665201ce8cd31f3b054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10soc/mediatek/mt8192: Init SSPMTingHan.Shen
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. Signed-off-by: TingHan.Shen <tinghan.shen@mediatek.com> Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47786 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: Init DPMHuayang Duan
DPM is a hardware module for DRAM power management and for better power saving in low power mode. BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Add EHL CRB memory initialization supportTan, Lean Sheng
Update memory parameters based on memory type supported by Elkhart Lake CRB: 1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Update ehl_crb device treeTan, Lean Sheng
Update Elkhartlake CRB devicetree devices based on EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I88097ced03f4376f309487b9d5207473f77742ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Remove JSL sku id info in SMBIOSTan, Lean Sheng
Remove JSL specific SMBIOS sku id info as it is not required by EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48123 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRBTan, Lean Sheng
THis patch removes IPU & MIPI related support from EHL CRB as they are not supported in EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 09:14:15 +0000