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2018-06-14soc/intel/{glk,apl}: ensure C1E is disabled after S3 resumeCole Nelson
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume. Disable C1E for GLK as it is for APL. This gives a coherent state before and after S3 resume. TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3 resume with bit [1] set to zero (0x20005d). Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14soc/intel/common: defines constant for C1E enable maskCole Nelson
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E enable bit. Define POWER_CTL_C1E_MASK to be used subsequently. Change-Id: I7a5408f6678f56540929b7811764845b6dad1149 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27035 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14lib/device_tree: Add method to get phandlePatrick Rudolph
Add a method to retrieve a node's phandle. Useful for board specific devicetree manipulations. Change-Id: I966151ad7e82fc678ab4f56cf9b5868ef39398e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-14util/docker/coreboot.org-status: collect report generatorsPatrick Georgi
Move generators for the board status report and the kconfig options report into a common directory and wrap them in a docker container. Also rework to emit HTML not wiki syntax. Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14util/lint: Run lint-extended-007-final-newlines checks in parallelMartin Roth
Instead of checking each directory in series, kick off the checks in parallel and then wait for them to finish. Failures print out with file information, so mixing output isn't a problem. This reduces the time it takes to run on lumberingbuilder by 60%. This could probably be sped up even more by splitting up src/mainboard into smaller sections. This method does skip a few control files at the top level - .gitignore, .checkpatch.conf, gnat.adc, etc. These could be added to the list of files to check, but I didn't think it was needed. Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14coreinfo: Skip unpopulated PCI functionsKyösti Mälkki
Per PCI specification, function 0 must be present, so functions 1 to 7 can be skipped in this case. For a device that is not multi-function, it may not decode function number in the hardware at all. To avoid registering such a device eight times, skip scanning functions 1 to 7. Without the latter fix, a single-function PCI bridge may call pci_scan_bus() second time and secondary side devices would get appended second time in the array devices[]. At that point, quicksort() apparently hits an infinite recursion loop. Since pci_scan_bus() is called in part of the early modules->init() sequence early in main(), the errors here left coreinfo payload completely silent when PCI module was built-in on affected system. Terminal screen was cleared, though. Change-Id: Ifc6622f050b98afb7196de0cc3a863c4cdfa6c94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-14AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki
With platforms moved to RELOCATABLE_RAMSTAGE, these overrides no longer have a meaning. Overrides existed because AGESA ramstage did not fit within the default 1 MiB of RAMTOP - RAMBASE, when placed low. Change-Id: I0185875dc550de74877c94f36128d5979e5553d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26813 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14AGESA binaryPI: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: I4571e8b560559b3d7afe429eca8caa1512e244a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/stoneyridge: Add early MTRR setup for new calloutsMarshall Dawson
Enable the two ranges to be used for the new callouts, AgesaHeapRebase and AgesaGetHeapBaseInDram. TEST=Boot grunt w/experimental blob, try different addresses BUG=b:74518368 Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/pi: Add AgesaHeapRebase calloutMarshall Dawson
Implement an optional callout for AgesaHeapRebase which allows AGESA to override any internal hardcoded heap addresses. Designate a region in CAR that may be used for pre-mem heap and return that address before DRAM is configured. After DRAM is up, the address in cbmem is returned. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/pi: Add GetTempHeapBase calloutMarshall Dawson
Implement a new AGESA callout that may be used to find the correct temporary location in DRAM to store heap data. Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based location to a temporary region. Once cbmem has been established, the heap will be relocated again in AmdInitEnv from the temp location to the final one. This patch does not materially affect the behavior of AGESA's heap management. It only puts coreboot in control of the location. Future work may refactor the copying. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13vc/amd/00670F00: Sync AGESA.h with PI blobMarshall Dawson
Add a new callout definition for AgesaGetTempHeapBase and displace AgesaHeapRebase (which was merged too soon) in the ordering. Also add its structure. AGESA will be modified to ask coreboot for the location for temporary storage of heap data at the end of InitPost. The old methodology is to use 0xb0000 but the change will allow coreboot to determine the location. BUG=b:74518368 Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13Documentation: Add rules for writing DocumentationPatrick Rudolph
Change-Id: Ic3808a0a10ddc8064d185e0920dcd9f60c435419 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13src/mainboard/*: Remove empty vendor foldersAngel Pons
After removing most geode_lx boards, some mainboard directories are left empty. This patch cleans them up. Change-Id: I2e99eba3d49dec90ceb2ce0c7f61612a9840ce59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27092 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13sb/intel/common/firmware: Use the -S flag of me_cleanerNicola Corna
The -S flag of me_cleaner, in addition to the standard code removal, sets the the AltMeDisable bit (ME 6.x-10.x) or the HAP bit (ME 11.x), which asks Intel ME to stop the execution after the hardware initialization. This should bring some advantages: * The state of Intel ME can be easily obtained by reading the Current Operation Mode register to trigger specific adjustments in the raminit (as already done in bd82x6x) * Intel ME falls into a more defined state, instead of being in a generic "Image Failure" * Hopefully, less code is run by Intel ME, as the execution should stop before even trying to load additional modules Tested on: * Nehalem, Sandy Bridge and Ivy Bridge (Nicola Corna) * Broadwell, Skylake and Kabylake (Youness Alaoui) If needed, the -S flag can be removed or integrated with other board-specific options by overriding CONFIG_ME_CLEANER_ARGS. Change-Id: I2c12d09124dcc39924d1dc4eaf53a2dc1f69a2ac Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-13util/sconfig: Prepare sconfig to allow parsing multiple treesFurquan Shaikh
In preparation to allow devicetree overrides, it will be necessary to use the same parsing functions to prepare two separate parse trees. This change does the following things: 1. Updates root device and bus names to add base_ prefix. 2. Adds a function parse_devicetree that sets the root_parent and linenum before calling yyparse(). 3. Updates all uses of root_dev to refer to the next base_root_dev. BUG=b:80081934 TEST=Verified that static.c generated for all boards built using abuild is the same with and without this change. Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-06-13soc/amd/stoneyridge/acpi.c: Create GPIO acpigen proceduresRichard Spiegel
There are some acpigen functionality that have not been implemented. They are defined as week within acpigen.c, in order to not break the build. This adds stoneyridge specific versions. BUG=b:79546790 TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS, activate ACPI debug, activate S3 stress test. Interrupt stress test, do a "cat /var/log/messages" saving the serial output. Examine the serial output, see added debug code showing action taken. Confirm action by reading proper register. Debug code removed. Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parametersRichard Spiegel
PM1 and GPE0 are being stored directly to NVS, when actually what should be saved is the index of the bit responsible for waking. Fix the procedures and add definitions to the actual IO addresses to be read when recording status and enable registers. BUG=b:75996437 TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the message indicating which indexes are being save in NVS for _SWS. Try sleep stress test, verify that the index is different from that of power button. Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12soc/amd/stoneyridge/acpi: Create a GPIO libraryRichard Spiegel
There are some acpigen functionality that have not been implemented. In order to implement them, ACPI GPIO functions to read and write to the control MMIO of a particular pin is needed. So as a preliminary task to implementing acpigen functions, create a library with functions to be accessed by acpigen generated ACPI code. BUG=b:79546790 TEST=Build grunt, more tests with commit 0f2acbd6b1. Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-12stoneyridge: Move agesa out of bootblockRaul E Rangel
This is Garrett's patch with a bit of cleanup. BUG=b:65442212 TEST=Was able to boot, suspend and resume on grunt. Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12util/lint: Run lint-extended-007-checkpatch checks in parallelMartin Roth
Instead of checking each directory in series, kick off all the checks in parallel and then wait for them to finish. Failures print out with file information, so mixing output isn't a problem. This reduces the time it takes to run on lumberingbuilder from 31 seconds to 6. Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12drivers/i2c/generic: Ensure config is not NULL before accessing itFurquan Shaikh
This change checks to ensure that config is not NULL before it is accessed for the first time. Reported by: Coverity CID #1393312 Change-Id: Ic248c79783da9c2bfdf3b7f737e5963feff7558c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-12Documentation: Add Gigabyte GA-H61M-S2PVAngel Pons
Change-Id: I0064710362a1c7882d5a40b469d6aacad5c60218 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/26964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12arch/x86: Fix payload loading via bounce-bufferKyösti Mälkki
Fix regression (supposedly) after commit: 23d62dd lib/bootmem: Add more bootmem tags Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite memory regions of the running ramstage. This case is handled gracefully via a bounce-buffer implementation in arch/x86/boot.c. Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-12bootmem: Clarify usage with bounce-bufferKyösti Mälkki
Add bootmem_targets_usable_with_bounce() to handle cases of payload loading via bounce-buffer. Change-Id: I9ebbc621f8810c0317d7c97c6b4cdd41527ddcbb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26985 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-12kconfig: add script to manipulate .config files on the command linePaul Menzel
Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the newly created directory `scripts`. Here is the original commit message from 2009. > commit 8e54701ea85b0ab0971637825a628f5aa2b678a4 > Author: Andi Kleen <andi@firstfloor.org> > Date: Sat Jan 3 03:21:41 2009 +0100 > > kconfig: add script to manipulate .config files on the command line > > I often change single options in .config files. Instead of using > an editor or one of the frontends it's convenient to do this from > the command line. It's also useful to do from automated build scripts > when building different variants from a base config file. > > I extracted most of the CONFIG manipulation code from one of my > build scripts into a new shell script scripts/config > > The script is not integrated with the normal Kconfig machinery > and doesn't do any checking against Kconfig files, but just manipulates > that text format. This is always done at make time anyways. > > I believe this script would be a useful standard addition for scripts/* > > Sample usage: > > ./scripts/config --disable smp > Disable SMP in .config file > > ./scripts/config --file otherdir/.config --module e1000e > Enable E1000E as module in otherdir/.config > > ./scripts/config --state smp > y > Check state of config option CONFIG_SMP > > After merging into git please make scripts/config executable > > Signed-off-by: Andi Kleen <ak@linux.intel.com> > Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Change-Id: Ie32a4459398df8694956dd644f38692017a26388 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/26243 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11util/optionlist: show location of a commentPatrick Georgi
Change-Id: Ib417f435011f0331a1b0228734874ef0a62fb587 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-11util/optionlist: move kconfig2wiki to kconfig2html and adapt to htmlPatrick Georgi
This also removes a "chapters mode" that we never used. Change-Id: Ib301e2f4db0b9678081fa987a5dcc7108bb103a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-11inteltool: Add dumping of full PCR portsYouness Alaoui
SoCs from Skylake on have many settings as so called private con- figuration registers (PCRs). These are organized as 256 ports with a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's BAR to access them. Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19593 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11google/kukui: Add MediaTek MT8183 reference boardTristan Shieh
BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mediatek/mt8183: Add a stub implementation of the MT8183 SOCTristan Shieh
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26659 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/*/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: If1f032d097224a1102ba29d8d45dce46aad3a91a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11google/fizz: fix LAN driver chip_info attachmentMatt DeVillier
As a result of commit: [711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device fizz's chip_info for the LAN driver is being overwritten/nulled, as the LAN device is on function 2 (PCIe port 3), but the driver info was set for the post-swapped PCIe port (1). Move the driver chip_info to function 2/port 3, so that it follows the PCI device function when swapped after FSP-s, and is correctly passed to the LAN driver. Test: boot google/fizz (teemo variant), check cbmem console and verify ethernet MAC address and LED config correctly set. Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11sb/intel/common: Include SPI driver into postcar stageNico Huber
Change-Id: I2ea07cdeb8fc70dbf516831f4da5949fef136b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-11drivers/spi: Remove Kconfig prompt from SPI_FLASH_SMMNico Huber
Why would that be a user visible option? Drop the prompt and the `default n` and select it automatically when needed. I hope I caught all its users. TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile and link. Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-11drivers/spi: Treat all stages commonly when adding driversNico Huber
Clean it up and add all flash chip drivers to postcar stage thereby. There seem to be SPI controllers that don't need the individual flash chip drivers. For those postcar support was added in b6b1b23 (console/flashconsole: Enable support for postcar). However for SPI controllers that need the individual drivers (i.e. those with CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar stage was broken. For all other stages, the set of compilation units stays the same. Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26871 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11drivers/spi: Remove DEBUG_SMI guardNico Huber
Let the linker take care of it. Change-Id: I67d2636ceb042f833c1b44888b98135d728940e0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-11mainboard/google/kahlee: Remove unused baseboard codeMartin Roth
This code is no longer needed. BUG=b:107537694 TEST=Build & boot on grunt Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/kahlee: Remove Kahlee variantMartin Roth
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized. BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed. Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/eve: add vendor to subsystem idMatt Delco
The initial subsystem ID had a device ID but not a vendor ID. This change adds the Google vendor ID to the subsystem ID. Change-Id: I14897da115fd6f2ddd492b6c565bd23227197232 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/26987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-11selfboot: Move x86 quirk under archKyösti Mälkki
Making exceptions for some payload to be loaded near and under 1 MiB boundary sounds like a legacy 16-bit x86 BIOS thing we generally do not want under lib/. Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-11mb/google/poppy/variants/nami: Add EC_ENABLE_TBMC_DEVICEShelley Chen
Add tablet motion control config to nami devices. BUG=None BRANCH=None TEST=run evtest make sure tablet switch value is 1 in tablet mode and 0 when not in tablet mode Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26970 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/google/poppy/variants/nocturne: enable nvmeNick Vaccaro
- configure GPP_B7 (PCIE_NVME_CLKREQ_ODL) for NF1 - enable root port 9 - add nvme register settings to devicetree BUG=b:78122599 BRANCH=chromeos-2016.05 TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage', boot to kernel, and verify /dev/nvme* entries exist. CQ-DEPEND=CL:1090070 Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-11Fizz: Remove BJ adapter configurationDaisuke Nojiri
This patch removes BJ adapter configuration, which has been moved to the EC. BUG=b:109762580 CQ-DEPEND=CL:1089328 BRANCH=none TEST=Verify BJ adapter is set expectedly on Teemo. Change-Id: I3041b984e7f02624b94ba2713b084d001fa155f9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/26965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11crossgcc: Update to clang 6.0 & cmake 3.11.3Martin Roth
Change-Id: I1a0db60b527c2f7ffe77743c0d75b78a7c8bc4cc Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26877 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-09sb/intel/lynxpoint: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-09sb/intel/fsp_bd82x6x: Use pci_devfn_t instead of device_tElyes HAOUAS
Change-Id: I775f5482970905134bb395b03845eb798d88d209 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-08soc/intel/skylake: Enable low power S0Idle capabilityHaridhar Kalvala
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0 if S0ix is enabled for the platform. BUG=b:79559085 TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table - FADT.Flags[21] bit. Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210 Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/26940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-08util/sconfig: Get rid of rescnt in struct deviceFurquan Shaikh
This change gets rid of rescnt member in struct device since it is redundant. "res" member can be used to determine if resource list is present or not. BUG=b:80081934 TEST=Verified that static.c generated with and without this CL is exactly the same for all boards built using abuild. Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08util/sconfig: Re-factor device structure in parse treeFurquan Shaikh
This change re-factors the device structure in parse tree to be able to support multidev devices just like non-multidev devices. With this change, every device has a bus under it which is the parent of all devices that fall on the bus. If there are duplicate entries in the devicetree, then there will be multiple buses under the device and each bus will have its own set of children. The tree starts out with a root device which has a root bus under it. This is a special device which is created statically and its parent is its own root bus. When parsing the device tree file, devices get added under the root bus as children. Since this change re-organizes the way devicetree is represented, it gets rid of latestchild and next_sibling pointers from struct device. Also, the tree traversal to generate static.c is changed to breadth-first walk instead of using the next_sibling. BUG=b:80081934 TEST=Verified using abuild that all boards compile successfully. Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08util/sconfig: Make queue handling more generic within main.cFurquan Shaikh
This change updates queue handling routines to be more generic so that it can be used by more than just chip queue. Additionally, it provides functions to dequeue element from head and peek head of a queue which will be used in a follow-up commit. BUG=b:80081934 TEST=Verified that abuild compiles successfully for all boards. Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08mainboard/google/kahlee: Turn on backlight for all SKUsMartin Roth
Careena uses a different keyboard backlight method, so let the EC handle the different SKUs and backlight methods. BUG=b:80106042 TEST=None Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08src/mainboard/kahlee: Use common mainboard and romstage filesMartin Roth
Until these need to be separated out, use a common file for mainboard and romstage to make upkeep easier. BUG=b:80106042 TEST=Build Grunt and Careena Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08southbridge/intel/lynxpoint: add hard_reset to postcarPatrick Georgi
This fixes the following failure on certain google/peppy configs: build/postcar/lib/reset.o: In function `__hard_reset': /home/pgeorgi/coreboot/src/lib/reset.c:24: undefined reference to `do_hard_reset' Change-Id: I448a8702a30108f1fc82179a766cbdd209336df7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26986 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08mainboard/google/kahlee: Use 66MHz SPI clock for fast readMartin Roth
Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08sconfig/main.c: Fix number of arguments in fprintfMaulik V Vaghela
During compilation sconfig/main.c gives an error regarding number of arguments passed in fprintf. BUG=none BRANCH=none TEST=check if compilation warning has been fixed Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26972 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08arch/x86: Drop leftover ROMCC console supportKyösti Mälkki
Change-Id: I3e52569a34e1f7bfea8be9da91348c364ab705e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-08util/sconfig: Get rid of unused parameter to walk_device_treeFurquan Shaikh
This change gets rid of unused 3rd parameter chips to the function walk_device_tree. BUG=b:80081934 TEST=Verified that abuild compiles successfully for all boards. Change-Id: I255ff030562073b16310fc22a0981808bf2c062f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
Change-Id: Ia637d32ffaa5d280320955d34141eddc8b7df981 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22222 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-083rdparty/libgfxinit: Update submodule pointerArthur Heymans
Update to current master. This includes: - G45 support - fixes scaling on eDP (needed for working textmode on eDP) - gfx_test drawing and moving cursors - Adding support for Tiling on <= Haswell - Allow changes to the framebuffer configurarion without resetting the pipe. Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26823 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI sourceDaniel Kurtz
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake the AP from S3 on keyboard presses. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) press a key on the internal keyboard => system resumes from S3 Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOsDaniel Kurtz
By default we use a 1:1 mapping between GEVENT bits and the corresponding SCI_MAP entry. However, we still must program the SCI_MAP entries with the GEVENT number. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) move finger on touchpad for ~1 second => system resumes from S3 Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26930 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/octopus: Fix GPIO to GPE mappings in devicetreeFurquan Shaikh
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus variants) changed the GPE mappings to accomodate for WiFi wake pin. However, this resulted in TPM interrupt pin being removed from the GPIO to GPE mapping. Since we do not support true interrupts in coreboot, GPE_STS registers are used to identify if an interrupt has triggered. Change in GPE mapping resulted in this information to be lost when talking to TPM thus resulting in "Timeout wait for tpm irq". This change fixes the above issue by assigning GPIO block for TPM interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to DW3. DW3 was mapped to NW_31_0 which only has debug header pins and CNVI pins (none of them are used for reading GPE_STS or as wake sources). BUG=b:109824918 TEST=Verified that there are no "Timeout wait for tpm irq" messages when talking to TPM. Change-Id: I30768177a838a684948f7485d760c8b83c3190f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-06-07soc/intel/common/pch: Add pch lockdown codeSubrata Banik
pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy: Select right TPM interfaceNaresh G Solanki
TPM over SPI/I2C config selection got changed in https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the same. BUG=None BRANCH=None TEST=Build for Soraka & make sure that TPM is probed over I2C interface rather than SPI. Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26890 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07Makefile.inc: Skip -fconserve-stack flag if running scan-buildMartin Roth
Scan-build refuses to run if the -fconserve-stack flag is added to cflags. It fails with the cryptic message "could not find clang line". Change-Id: Ib1b56ef7d217138a1a195fe993d8e8dd965bd855 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for SonaAmanda Huang
Since there are two cameras on Nami and only one camera on Sona. We need to disable rear camera/DMIC on all Sona sku. BUG=b:109710674 BRANCH=master TEST=Verify if only front camera/DMIC shown on Sona Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for PantheonAmanda Huang
Since there are two cameras on Nami and only one camera on Pantheon. We need to disable rear camera/DMIC on all Pantheon sku. BUG=b:109720689 BRANCH=master TEST=Verify if only front camera/DMIC shown on Pantheon Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07Documentation/release: Add some of the things we added since 4.8.1Patrick Georgi
From here on, changes should directly touch the release notes, but these are notable, too. Change-Id: I602d67f8dd38391663094212cdb4609cdad458ee Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-07console/hw-debug_sink: Do not cache state of log levelNico Huber
As we suppress output now before console_init() is done, the log level read at start of ramstage is always -1. Change-Id: Ia078d647c47aaa41ca9f2df9cf8506148ef86538 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07Documentation: inject the current git revision into the websitePatrick Georgi
Change-Id: I79cceca7373f8bdf9bbfba5d84b8fa589afa838b Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07util/docker/doc.coreboot.org: Add git to the imagePatrick Georgi
Required to get a current version string onto doc.coreboot.org Change-Id: Iac54c4be2d4e783b7bf9ed529a431e72c67abab7 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07util/docker: rename docs.c.o to doc.c.oPatrick Georgi
Make the directory name match the name of the subdomain. Change-Id: I2dcf2385e6d953b7fe02caef72413149a332ec24 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26887 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07util/docker/docs.coreboot.org: reduce container sizePatrick Georgi
We don't need the .deb files in the image forever Change-Id: I67a56faf8f9466e5162f7662708a5abb2971d2f9 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07util/docker/docs.coreboot.org: Downgrade sphinxPatrick Georgi
Sphinx >= 1.6 can't use recommonmark. debian/stable is ancient enough to have an older version. Change-Id: I287deab9168ab6124b05d0c6d6e8cdbd7fdc2eec Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07mediatek: Move uart, timer and cbmem code to a common directory.Tristan Shieh
This patch moves uart, timer and cbmem code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-07mediatek: Refactor to sharing code among similar SOCsTristan Shieh
This patch refactor cbmem and timer code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26881 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mediatek: Refine whitespace and formating changesTristan Shieh
This patch fix whitespace and formating issues: 1. Using two spaces between code and single line comment. 2. No space after asterisk. 3. Fix checkpatch error. 4. Remove spaces after cast operators. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07tint: change the tint download link from HTTP Debian to HTTPS FSFMike Banon
Last time there was a request to change a link from HTTP to HTTPS, also it seems more ethical to use a link to the Free Software Foundation server. SHA1 is the same - 7fcaa428c6d0de7096d1e4fbfd14848096ae5aad. Change-Id: I55147ee2668de03ba6e9feb84936de24b2a001df Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07tint: fix the "Paused - Press any key to continue" message for pauseMike Banon
Earlier this message has not been shown even at the corner of screen. This fixes it by refreshing the screen, and moves it to the center. Change-Id: If4e33e884c00c17f19ab330167d9293c8396ff3e Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07tint: make it possible to reboot by pressing 'q' key two timesMike Banon
Earlier it was impossible to exit without pressing the power button. Change-Id: Ia56d639fa8e563047fb3d2723695626a449ead40 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23853 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07tint: upgrade the outdated tint payload from 0.03b to 0.04+nmu1Mike Banon
Fixes two buffer overflows and opens a road to further improvements. All the previous adjustments to libpayload_tint.patch (including the latest "use the current time as random seed") have been preserved. Change-Id: I22e65d18a0b1551f7049c4afe7f95868f584cf9b Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23852 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07arch/x86/smbios: Conditionally call SMBIOS opsNaresh G Solanki
Check whether device is enabled before calling smbios ops. BUG=None BRANCH=None TEST=Build & boot Soraka. Change-Id: I79681c10679e1de3a2d177503f29239968d0c157 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07google/chromeec: Set proper dev opsNaresh G Solanki
For enable_resource & set_resource, use default DEVICE_NOOP so that they are not reported as missing during enumeration. BUG=None BRANCH=None TEST= Build & boot soraka. Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07util/lint: Add filename checkerMartin Roth
Check that filenames have only alphanumeric characters plus underscore, dash, and period. Change-Id: I7bf0be15d588aa1a5ece628b56e871662d6af44b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07Documentation: Rename file with space in filenameMartin Roth
Change-Id: I10203de578c4dd0b8915dad4b0d456531049328f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06mb/google/octopus: Update GPIOs as per latest schematicsFurquan Shaikh
Update GPIOs in baseboard to match latest schematics: 1. Get rid of STEST GPIOs(GPIO_{62,84-89}) 2. Get rid of SD_CD_ODL(GPIO_134) 3. Get rid of KB control GPIOs(GPIO_{144-146}) 4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the configuration for other pen GPIOs. BUG=b:109764138 Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26874 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06mb/*/*: Add a few VBT filesArthur Heymans
These files are directly extracted from the vendor firmware. Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06drivers/intel/gma: Include mainboard data.vbtArthur Heymans
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path to point to the mainboard dir and to select INTEL_GMA_ADD_VBT_DATA_FILE by default. Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06arch/x86: Always select RELOCATABLE_MODULESKyösti Mälkki
All boards except those with NO_RELOCATABLE_RAMSTAGE or explicit select already had this feature built. Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
Choose codepath as if ROMCC_IF_BUG_FIXED was set. Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>