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2019-05-04src/Kconfig: remove duplicate entry for drivers/fsp1_0/KconfigMatt DeVillier
The entry for drivers/intel/fsp1_0/Kconfig was added under the chipset menu before addtional FSP versions were added, and the drivers/*/*/Kconfig entry added to support them. This results in the fsp1_0 Kconfig items being duplicated in the Chipset and Generic Drivers menus. Remove the chipset entry since it's no longer needed. Test: select FSP 1.0 mainboard (e.g. intel/minnowmax) in menuconfig, observe FSP 1.0 Kconfig entries listed only under Generic Drivers menu. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: If1e78fb9259b1a46d308db829881eb3b3d17cf40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32565 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03{soc, southbridge} : Correct typo in commentFrans Hendriks
BUG=N/A TEST=N/A Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03mainboard/google/cyan/acpi: Serialize _CRS methodFrans Hendriks
IASL reports warning 'Control Method should be made Serialized'. Change _CRS method to Serialized. BUG=N/A TEST=Build Google Banon and Google Cyan Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-03sdm845: Add QCLib to RomStage to perform IP initT Michael Turney
CB acts as I/O handler for QCLib (e.g. DDR training data) This interface allows bi-directional data flow between CB and QCLib Tested and working interfaces: DDR Training data QCLib serial console output DDR Information (base & size) limits cfg data TEST=build & run Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-03sdm845: Combine BB with QC-Sec for ROM bootT Michael Turney
TEST=build & run Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03drivers/fsp 1.1: clean up Kconfig optionsMatt DeVillier
Now that support has been added for using the public FSP repo for Braswell platform, clean up Kconfig options and set sane defaults when using it. The following changes have been made: - add option to use the 3rdparty/fsp repo for Braswell platform - reorder FSP 1.1 Kconfig entries for improved flow/readability - set the default path for the FSP binary based on use of FSP repo and platform - set the CBFS location for the FSP binary based on platform Change-Id: Ie2f732bf0ac4d4551908caa56360b8bb2869b4c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-03soc/intel/braswell: add default option to use public FSPMatt DeVillier
The current Braswell FSP 1.1 header in vendorcode/intel, for which there is no publicly available FSP binary, contains silicon init UPDs which are not found in the publicly available header/binary in the FSP Github repo. This prevents new boards from being added which use the public Braswell FSP header/binary. To resolve this, move the UPDs not found in the public header from the soc's chip.c to ramstage.c for the boards which use them. Add a Kconfig option to use the current non-public FSP header and select it for boards which need it (google/cyan variants); set the public FSP option as the default. Use the Kconfig option to set FSP_HEADER_PATH to ensure the correct header is used. Test: build google/cyan and intel/strago using non-public and public FSP header/binaries respectively. Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-03Makefile.inc: Update fsp submodule for all FSP platformsMatt DeVillier
Rather than selectively update the fsp submodule based on FSP version or platform selection, update it when building for any FSP-enabled platform, so all have latest version available. Change-Id: If07d55828a1863623e04a4ecdd1514c3cb6d9c11 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-03mb/google/arcada: Add settings for noise mitgationNathan_chen
Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com> Change-Id: I395b2fc527705ab207325cfd7147e6af5f300fce Reviewed-on: https://review.coreboot.org/c/coreboot/+/32521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-03mb/google/poppy/variant/atlas: enable USB acpiGaggery Tsai
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:122540489 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage $cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat & retrieve ssdt.dat from DUT & $iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio" under _DSD object Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-03nb/intel/haswell: correct a typo in KconfigJoel Kitching
Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-02sdm845: Add USB support on cheza platformChandana Kishori Chiluveru
This patch adds code to initialize two USB DWC3.0 controllers and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to initialize USB3.0 on the cheza mainboard. Synopsis controller initialization and configuration sequences taken from USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy programming. Includes Super speed mode support. TEST=USB keypad and mass-storage device enumeration tested with this patch Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02qualcomm: Add QCLib interface support to common/T Michael Turney
Change-Id: I38d086c379a3c2f54d1603a2fed5b33860f7f4d7 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02sdm845: Select VBOOT_MIGRATE_WORKING_DATA, now requiredT Michael Turney
Change-Id: Idebbbd89de05d949e6f953aa49d8662d64383d1a Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02mainboard/intel/icelake_rvp: Add support to read board ID from ECSubrata Banik
This patch selects EC_ACPI kconfig to identify Intel Ice Lake RVP board by querying EC. Change-Id: I0082e04ef1b21d533e40d232209ee630f748aec6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-05-02soc/intel/icelake: Correct the GPE DWx mapping for GPIO groupsSubrata Banik
This implementation corrects the GPE DWx mapping for GPIO groups. The assignments is done in GPIO MISCFG register for all GPIO communities. And configures the which GPIO communities get register as Tier1. Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02soc/intel/icelake: Select FSP_M_XIPSubrata Banik
This patch ports CB:32275 changes from CNL to ICL. Ice Lake require that FSP-M component should be XIP. This change selects FSP_M_XIP so that the right arguments are passed into cbfstool when adding this component. Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32507 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02soc/intel/icelake: Move power_state functions to pmutil.cSubrata Banik
This patch ports CB:31787 and CB:31908 changes from CNL to ICL. This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. Also fix GEN_PMCON bit checks as below: ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B. Change-Id: Ib7ab95b7bbcc97a076d27a11db2105f7b976b521 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32506 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02soc/intel/{broadwell, skylake}: Remove unused pch_log_state() declarationSubrata Banik
This patch removes unused pch_log_state() function declaration from pch.h because elog.c has static implementation of pch_log_state(). Change-Id: Ib0f3831dc3b60af2ee432a76866e401a51b96fb7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32505 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02soc/intel/icelake: Add chipset event loggingSubrata Banik
This patch ports CB:30718 and CB:31908 changes from CNL to ICL. Add logging of chipset events on boot into the flash event log. This was tested on a google/dragonegg board to ensure that events like "System Reset" are added to the log as expected. Also fix GEN_PMCON bit checks as below: ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B. Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02soc/intel/icelake: Clear PMCON status bitsSubrata Banik
This patch ports CB:31902 changes from CNL to ICL. The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02x86emu: add console.h header to fix compilationMartin Kepplinger
Commit 351e3e5 ("src: Use include <console/console.h> when appropriate") has broken the build here, see below, so we include console.h here again. In file included from src/device/oprom/x86emu/x86emui.h:65, from src/device/oprom/x86emu/debug.c:40: src/device/oprom/x86emu/debug.c: In function 'x86emu_dump_regs': src/device/oprom/x86emu/debug.h:46:22: error: implicit declaration of function 'printk'; did you mean 'printf'? [-Werror=implicit-function-declaration] #define printf(x...) printk(BIOS_DEBUG, x) ^~~~~~ src/device/oprom/x86emu/debug.c:366:5: note: in expansion of macro 'printf' printf("\tAX=%04x ", M.x86.R_AX ); ^~~~~~ Fixes: 351e3e5 ("src: Use include <console/console.h> when appropriate") Change-Id: I75d0b7c08bfa6dcb07778bbb762223b62cfc3da7 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-05-01mb/google/sarien: Disable S5 wake on LAN by defaultEric Lai
Chromebook doesn't require support wake on LAN in S5. Disable it by default for power saving. BUG=b:131571666 TEST= check LAN indicator is off under S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-01google/cyan,intel/strago: increase default CBFS sizeMatt DeVillier
a 1M CBFS size is inadequate when adding the FSP binary to image due to default FSP location in CBFS, so bump to 2M to ensure autobuilds succeed. Change-Id: I0683bea43cc71fad32bc42bfbd72f3913256d53c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-01arch/x86/acpi: Update VT-d DMA remapping structure flags settingJohn Zhao
DMA remapping structure flags settings are Bit 0: INTR_REMAP, Bit 1: X2APIC_OPT_OUT, Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG, Bits 3-7: Reserved (0). BUG=b:130351429 TEST=Image built and kernel booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iaf4764a9062756cadc335d1932b0da8628797f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32516 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-01soc/intel/common: Set RX_DISABLE for pads configured as NCFurquan Shaikh
For GPIO pads that are configured as no-connect (PAD_NC), setting it as GPI (with Rx enabled) leads to GPE0_STS being set incorrectly. Though this is not an issue in practice (GPE0_EN is not set, so no events triggered), it can confuse users when debugging GPE related issues. This change configures PAD_NC to have Rx disabled along with Tx to ensure that it does not end up setting GPE0_STS bits for unwanted GPIO pads. P.S.: IOSSTATE config does not have a TxDRxD setting, so leaving that configuration as is. BUG=b:129235068 TEST=Verified that GPE0_STS bits are not set for pads that are marked as PAD_NC. Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2019-05-01mainboard: Add MSI MS-7707Max Blau
* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) * SandyBridge Intel P67 (BD82x6x) * Winbond 25Q32BV (4MB) * Fintek F71808A * Intel 82579V Gigabit * NEC uPD720200 USB 3.0 Host Controller * IME 7.0.4.1197 Working: * PCIe gfx adapter * PS/2 Keyboard * USB3.0 * Ethernet * S0/S3/S5 * HWM Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3 Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-01superio/fintek/f71808a: Add more optional ramstage registersMax Blau
Add more registers and make them optional, so they keep untouched/ their default if omitted. Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-04-30rockchip: rk3399: increase memory for fit payload.Marty E. Plummer
Increase ramstage to 2M, required to actually embed the 7.2mb uImage into the coreboot.rom, increase the postram cbfs cache in order for the fit image to be loadable (without this increase the fit payload is found but not loaded) Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-30vboot: refactor OPROM codeJoel Kitching
The name OPROM is somewhat inaccurate, since other steps to bring up display and graphics are needed depending on mainboard/SoC. This patch cleans up OPROM code nomenclature, and works towards the goal of deprecating vboot1: * Rename CONFIG_VBOOT_OPROM_MATTERS to CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig description * Remove function vboot_handoff_skip_display_init * Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY * Add |flags| field to vboot_working_data struct * Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild TEST=build and flash eve device; attempt loading dev/rec modes BRANCH=none Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-30mb/google/hatch: Modify IRQ configuration to enable RT5682 headset INTNaveen Manohar
Patch corrects IRQ and GPIO configuration for RT5682 codec's Jack INT. Switching IOAPIC to GpioInt because ACPI Interrupt() doesn't support jack triggering on both edges. BUG=b:130180492 TEST=build and boot on a CML EVT board. Use evtest & verify headset jack detection functions as expected. Change-Id: Ia9bf8d554b54554f9ac1e78fd44a508964c8a14d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Suggested-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32474 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-30Documentation: Add FITPatrick Rudolph
Describe the Firmware Interface Table and reference useful documentation. Change-Id: I00abc1fd13be7b48d56ba8cb65d2542ed07f9017 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-29sb/intel/bd82x6x: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-29ich7/i945: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: Ieff4271c4a09d564d5f3415d8bc2c3843c8460f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29src/mb: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29nb/intel/pineview: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I32c731de0c30940d15fd01fec6f10b3b33c04370 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29nb/intel/nehalem: Use system_reset() and full_reset()Elyes HAOUAS
Use already defined system_reset() and full_reset() functions. Change-Id: Ib7e399b5186aa704d0388c4a4b18480f2e3799f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29nb/intel/haswell: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I436f62c4402736fb74c59d8b359d0b3963f0e659 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29nb/x4x: Use system_reset() and full_reset()Elyes HAOUAS
Use already defined system_reset() and full_reset() functions. Change-Id: I0a05f3ac5c5340a509024de2b444960f498c3e99 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29rockchip/rk3399: Select VBOOT_MIGRATE_WORKING_DATAJulius Werner
Trusted Firmware places some components in SRAM on RK3399 and therefore restricts accesses to SRAM to the secure world. This makes the vboot working data inaccessible to normal world payloads, so we need to migrate it into CBMEM. Change-Id: Ic7c95790f2f118ccbdd897550f13b5f987bdd831 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-04-29mediatek: Add function to raise the CPU frequencyTristan Shieh
Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency. Move the function declaration to common header. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29mediatek/mt8183: Set CPU frequency to 1417MHzTristan Shieh
With the default CPU voltage (0.8v), CPU frequency should be 1417Mhz at most. We have to raise CPU frequency to 1989MHz after increasing CPU voltage to 1.05v in romstage. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: I4c3e0fa27ccda8e0efe422b6ab503a1efb1697e9 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29vboot: specify NEED_VB20_INTERNALS when neededJoel Kitching
NEED_VB20_INTERNALS should always be specified when peeking into vboot internal data structures. BUG=b:124141368, chromium:956474 TEST=make clean && make test-abuild BRANCH=none Change-Id: I5a47a28350fd5a68efeff0d06ca150c1ae145412 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29mb/google/sarien: Update GBB flagsDuncan Laurie
Disable the GBB flag forcing manual recovery now that we can read the manual recovery from H1. Enable the GBB flag to skip EC software sync, since images built from coreboot.org do not include the EC binaries by default. Change-Id: I0e1d6304e3e29eda68c7b807cf0774275c37d710 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29Revert "soc/intel/common/block: add VMX support"Nico Huber
This reverts commit 9aae51ad1141a47d5c2f7133b02f5f0ab6168860. Proper code in cpu/intel/common/ shall be used instead. Change-Id: I4a5d558b03497d106083eece10c5b34e0e7cbb2d Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29683 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29arcada: add internal pull to ISH UART RXJett Rink
We do not want the RX signal to be floating on the board as that could cause the ISH to remain in a higher power state (because there is logic to keep the ISH in an higher power state when there is an active UART). Add an internal 20K pull up on the RX line. In normal configuration this will burn an additional 544uW. BRANCH=R75 BUG=b:131241969 TEST=verify that ISH console still works with rework Change-Id: Ifc9621bcafe4c86edfa9cd6d58b307254d3a81ca Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-29soc/skl: set IGD resources only if device is enabledMaxim Polyakov
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space. Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card. The following boards were used for testing: - Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU. Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS) - Intel KBL-R U RVP board (mobile i5-8350u) without GFX. Payload: tianocore edk2-stable201811-216-g51be9d0. Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29mediatek/mt8183: Init audio related clockJiaxin Yu
Enable audio clock, intbus clock, infra clock and mtkaif 26m clock.Needed by audio playback in firmware. BUG=b:117254418 BRANCH=none TEST=Build pass and verified on kukui p1 board Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-29mb/google/sarien: Add psys_pmax setting to 136WGaggery Tsai
This patch adds the setting of psys_pmax to 136W. According to the design, Rpsys is 11.8Kohm. Here is the equation to come out the Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm / 2 = 1.2V Hence, Psys_pmax is 136W. BUG=b:124792558 BRANCH=None TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-29soc/intel/apollolake/bootblock: Clear the GPI IS & IE registersKarthikeyan Ramasubramanian
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29soc/intel/common: Add support to clear GPI IS & IE registersKarthikeyan Ramasubramanian
Add support to reset the GPI Interrupt Status & Enable registers so that the system does not experience any interrupt storm from a GPI when it comes out of one of the sleep states. BUG=b:130593883 BRANCH=None TEST=Ensure that the Interrupt status & enable registers are reset during the boot up. Ensure that the system boots fine to ChromeOS. Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29soc/intel: Add GPI interrupt config register offset infoKarthikeyan Ramasubramanian
Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup. BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS. Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29Makefile: Check for errors in ACPI decompilation, tooNico Huber
We only grep'ed for "ACPI Warning" resulting in an actual more severe "ACPI Error" being ignored. Change-Id: I9cec8a388f5558b1ffc383cc2fc69405252cbb37 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-29nb/intel/sandybridge: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: Ic4716a3bb1dc6c6b29a028fc0ab28f9195f08416 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-29soc/intel/braswell: Move LPE ACPI code to mainboardFrans Hendriks
The ACPI code of LPE device is included regardless of the availability of the LPE controller. Linux remains requesting the status of device LPEA even if this device is disabled. Include ACPI LPE controller code at Braswell mainboards with LPE enabled. BUG=N/A TEST=Linux 4.17+ on Portwell PQ7-M107 Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-04-29mb/google/hatch/variants/baseboard: remove unused dqs_mapPaul Fagerburg
The dqs_map array is used only for LPDDR3 and LPDDR4. It is not used for DDR4, and so it can be removed from the baseboard memory initialization code. BRANCH=none BUG=b:129706819 TEST=ensure the firmware builds without error; I don't have hardware available to test this just yet. Change-Id: I07fac3097d68f37b4630d3f0010f987da2f03bd7 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29mb/google/hatch/variants/kohaku: Add support for LPDDR3 configurationsPaul Fagerburg
First configuration supported is 8 GB system memory: 4 x 2 GB (K4E6E304ED-EGCG). BRANCH=none BUG=b:129706819 TEST=ensure the firmware builds without error; I don't have hardware available to test this just yet. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ibd92d585118ff75492e8a7188dcdb2a286836d56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29soc/intel/cannonlake: Modify dq_map to provide for 6 entriesPaul Fagerburg
Intel's DQ_DQS_RComp_Info_Utility generates data for 6 entries. MRC will return errors if we don't have all 6 entries in the map. BRANCH=none BUG=b:131103736 TEST=ensure the firmware builds without error; I don't have hardware available to test this just yet. Change-Id: I20a768de0e4440d7dde7b717794c4e2d0c62819c Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-28mb/ocp/monolake: add TPM and IPMI supportLukasz Siudut
Changes includes: - enable TPM1 + add entry in devicetree - configure LPC IO to make IPMI work + add entry in devicetree - introduce DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-28Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addressesDaniel Maslowski
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: Daniel Maslowski <dan@orangecms.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-26mb/google/sarien: Enable LTR for PCIe NVMe root portDuncan Laurie
Enable LTR for NVMe so it can use ASPM L1.2. BUG=b:127593309 TEST=build and boot on sarien and check L1 substate with lspci before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
2019-04-26ACPI: Add RHSA and ANDD structures for DMAR tableJohn Zhao
Remapping Hardware Status Affinity (RHSA) structure is applicable for platforms supporting non-uniform memory. An ACPI Name-space Device Declaration (ANDD) structure uniquely represents an ACPI name-space enumerated device capable of issuing DMA requests in the platform. Add RHSA and ANDD structures support for DMAR table generation. BUG=b:130351429 TEST=Image built and booted to kernel Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-26soc/intel/apl/acpi: Do not report 8259 PICsNico Huber
The IRQ tables don't support this path, so we shouldn't report presence of the legacy PICs. As the _PIC method is optional and we ignore the passed parameter anyway, drop it. Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-26x86/acpi: Add Kconfig to toggle 8259 reportingNico Huber
Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-26Revert "mb/google/arcada: Add settings for noise mitgation"Duncan Laurie
This reverts commit 77fb3632a4a3d3004b3aa4950967be9164d9711d. Reason for revert: This change inadvertently added a submodule. Change-Id: I6cc2a3cd9d88986a2599a5ff2e5a066b1396a8c0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32472 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-26mb/google/poppy/variants/atlas: Revise AC/DC loadlineGaggery Tsai
This patch revises the AC/DC loadline settings because some major layout changes between proto and evt boards. BUG=b:130740639 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS. Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-04-26soc/amd/stoneyridge: Generate MCFG tableRaul E Rangel
BUG=crbug:948241 TEST=Booted and decompiled the table [000h 0000 4] Signature : "MCFG" [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : 15 [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 8] Reserved : 0000000000000000 [02Ch 0044 8] Base Address : 00000000F8000000 [034h 0052 2] Segment Group Number : 0000 [036h 0054 1] Start Bus Number : 00 [037h 0055 1] End Bus Number : 40 [038h 0056 4] Reserved : 00000000 Change-Id: I46dc1959971af4685a7ffd285429175d6882ae86 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-25cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans
CPU's featuring a non eviction mode cache the whole ROM. Therefore XIP stages don't need to follow some alignment constraints. Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-25soc/cavium/common/bootblock: Remove unused variablesElyes HAOUAS
Change-Id: I4835ca3e20f2e53598bfc77b633aca946d3fde9c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25src/lib/selfboot: Remove unused variablesElyes HAOUAS
Change-Id: I8d80084095912c30bfd8fc100bf27b522485a08a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25drivers/spi/sst: Remove unused variablesElyes HAOUAS
Change-Id: Ic6eb9c7dbfc5fde97f0f45f09431c617cb850c38 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25device/dram/ddr3: Remove unused variableElyes HAOUAS
'param' variable is unused because 'printram' function only expands to something in debug builds (not default ones). Change-Id: I0cdf34cbb9aaed5045db5294eeefeaac642aeb1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-25src/southbridge/intel: Remove unused variablesElyes HAOUAS
Change-Id: I3b5092aa076b9693f78c86ffb9b99805696bb0bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25src/southbridge/amd: Remove unused variablesElyes HAOUAS
Change-Id: I143f3395a385e170cce0979707d6a7f61107f40b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25src/soc/intel: Remove unused variablesElyes HAOUAS
Change-Id: Ie81377a31e6527c5fd5aaea99f08527912e870a0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25northbridge/via/vx900: Remove unused variablesElyes HAOUAS
The `printram` function only expands to a value only in debug builds. This isn't done in default builds. Change-Id: Ic88c4cc730ae2d0d0718c7f71260cd2b45a3ddcd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25src/northbridge/intel: Remove unused variablesElyes HAOUAS
Change-Id: Idd339e324b833d2d024edb45e33c3d74af4473e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25src/northbridge/amd: Remove unused variablesElyes HAOUAS
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-253rdparty/fsp: Update submodule pointer to upstream masterMatt DeVillier
Update submodule pointer to pull in newly-updated Braswell FSP. Adjust FSP_FD_PATH for soc/cannonlake due to filename case change. Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-25mb/google/hatch/: FPMCU not rebooted when DUT rebootsTim Wawrzynczak
Add FP_RST_ODL to early GPIO table, configured as low, so that the FPMCU will get reset when coreboot enters bootblock. BUG=b:130229952 BRANCH=none TEST=Compiles (no Hatch device w/FP to test) Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-04-25mb/supermicro/x10slm-f: Do SIO setup in bootblockTristan Corrick
Lynx Point switched to doing mainboard-specific super I/O setup in the bootblock with commit d893a2635fdd ("sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock"). The X10SLM+-F was added while that commit was in review, and hence did not receive the necessary changes to SIO setup. This patch has not been tested on hardware. Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-25mb/google/hatch: Pull up GPP_C13 for hatch and hatch_whlPhilip Chen
On EC end, we want to change this pin from push-pull to open-drain. And since there is no external pull-up resistor on the board, we'll have to configure this pin as internal-pull-up on AP end. BUG=b:129306003 TEST=None Change-Id: Ibc1f89fc25773220db009c6571400b01390dd756 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24src/Kconfig: increase heap size if using flattened image treeMarty E. Plummer
FIT support takes more heap memory than most coreboot payloads. Change-Id: Id17f25e94d97e937b0e9a9cee3dd1a8aef1d525d Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-24mb/google/kohaku: Update overridetree.cbTim Wawrzynczak
Add common SoC config. Disable PCIe WiFi. Add digitizer. Turn off native SD card interface. No WWAN. Add DA7219 driver to Kconfig. BUG=b:130310626 BRANCH=none TEST=compiles (no Hatch ref or Kohaku device to test) Change-Id: I17d5ba6ce4ec412384e4a1678474b8d26499ba40 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24mb/google/hatch: Move SD card detect GPIO.Tim Wawrzynczak
Not all Hatch variants utilize the SoC's native SD card support. Move the support to board-specific variants instead of the base device tree. BUG=none BRANCH=none TEST=compiles (no Hatch device to test with) Change-Id: Iae24114aad2c4d042c25da6f8cb740ccc8960082 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32417 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24util/sconfig: Throw an error if override tree has no devicesFurquan Shaikh
If override tree does not have any device, then the chip info structure in it cannot be associated with the correct device and ends up being added as a standalone chip info structure without any device actually using it. This change prevents this condition by throwing an error during compilation. BUG=b:130342895 Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-24mb/google/hatch/var/kohaku: Skip UART0 config in FSPFurquan Shaikh
Similar to hatch(CB:32278), this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. This change also adds a device to kohaku override tree to ensure that the settings in it take effect. BUG=b:130310626 Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-24mb/google/arcada: Add settings for noise mitgationNathan_chen
Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com> Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32403 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/sarien: Disable POWER_OFF_ON_CR50_UPDATEKeith Short
Disable the POWER_OFF_ON_CR50_UPDATE option on sarien/arcada. This is needed so that platform properly boots after doing a Cr50 firmware update when running on battery. BUG=b:126632503 BRANCH=none TEST=Build coreboot on sarien/arcada. TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots normally after sending TURN_UPDATE_ON to the Cr50. Change-Id: I0b687285eb95070eaffb68611a7d98eb8434ce2c Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24security/tpm: Change POWER_OFF_ON_CR50_UPDATE so it can be disabledKeith Short
Modify the POWER_OFF_ON_CR50_UPDATE Kconfig option so that specific mainboard implementations can disable the option. BUG=b:126632503 BRANCH=none TEST=Build coreboot on sarien/arcada. TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots normally after sending TURN_UPDATE_ON to the Cr50. Change-Id: I3beefaae21de61e53ae232dbdc8ea9dbb2c78cd5 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24mb/google/sarien: Add power control for Sarien touchscreenEric Lai
This change will save touchscreen power leakage 2-3mW in S0iX and increase T2 display time delay to meet display panel requirement. BUG=b:129899315 TEST= Measure touchscreen power from Sarien during S0iX Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32330 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/sarien: Remove touch VPD support and Melfas HID touchEric Lai
Sarien will change Melfas from HID to I2C and change address from 0x10 to 0x34. So we don't need VPD to separate Elan and Melfas anymore. BUG=b:131194574 TEST=boot up and check no Melfas HID device exist Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32437 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/sarien: Disable touch by strap pin GPP_B4Eric Lai
We want to disable touch for non-touch sku. We can use strap pin GPP_B4 to identify it is connected with touch or not. touch sku: GPP_B4 is low non-touch sku: GPP_B4 is high BUG=b:131132419 TEST=boot up and check no touch device exist Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If6681262c25e4b01e061a8520e38905d40345509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mediatek/mt8183: Set CPU frequency to 1989MHzTristan Shieh
Set CPU frequency from 1100MHz to 1989MHz to improve booting time. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: Id41c7ea8905c4db2537a5c32f96eb7c6b2c008ea Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32397 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mediatek/mt8183: Set processor voltage to 1.05vTristan Shieh
The maximum CPU frequency is 1417MHz with current processor voltage (0.8v). Set processor voltage to 1.05v for higher CPU frequency. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: I24ecdac2c85d3f012d9235449c0d727d727dc185 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-24payloads/seabios: Update the stable git hash of 1.12.1Martin Kepplinger
The Kconfig file has been updated to show 1.12.1 but this is only what gets displayed for the "stable" option. Fix this by updating the actual git hash for the SeaBIOS 1.12.1 release tag. Fixes: fb83ff1a8b ("Update stable from 1.12.0 to 1.12.1") Change-Id: I76dc0dc8b651df0c6ff6f3c02819a70bab8c04cd Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-243rdparty/opensbi: Add submodulezaolin
* Add opensbi for RISC-v Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-24mb/google/sarien: Toggle SSD reset pin on DVT2Lijian Zhao
SSD reset pin had been added on DVT2, the power sequnence requires toggle in boot stage. BUG=b:130741066 TEST=Boot up with simulated DVT2 platform and confirm SSD can be detected during warm reboot. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24mb/google/octopus: I2C clock tuning for bloogTony Huang
Tune I2C params for I2C buses 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:131132499, b:128998988 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 22:24:57 +0000