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2020-04-04mainboard/purism: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22515873a28333607ad2552c1a417e649cfbaac8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04mainboard/packardbell: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ia380dd3faaaf7bdb16c8c877f5488dbbf01a4146 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04mainboard/msi: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ia5985bd013f68f5510dcad1de5a233f899a63ca0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04mainboard/lenovo: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7b7670bb541cf4814fd4958d5c0d8c68cbee80c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04mainboard/kontron: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5aeaaf267a187105f08f48a010323baa77e06989 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/ibase: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic2989038a5f11981682443e77d8f639a3ef280f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/hp: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I42ab3846c75adca1fe74dfa5114c9b697127bb76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/gizmosphere: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1135a495053b1c1229c94c794664b23f50d50362 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/gigabyte: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I90691355cfc73f0834d45024a2885998b5652f88 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/getac: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I9528563399d8f47570a602a378583487f3cacc8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/foxconn: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8da7a1a2ae85eb0a5a33c18f233228d81f6938f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/emulation: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I68d2a8ac6f201f3c1131252b2b53b2b17ece1db6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/biostar: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib697a4b1eb74cced9f22c3c602215f0dcac81f20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/apple: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I6537288b326172d70aac7849b8d9e33c7f5aff9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/sapphire: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I840a776c237a630c0ff6df7d2ee065be51224658 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/razer: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8fb7bc8056bbd940a2286b6a11a819335aa77ace Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/ti: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Idcf639102b041ae46952df28c69dce02e1d3d689 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/system76: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2aa745e03e62ff8b9b5c9cb6f91d7f832f599f8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/sifive: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8c9d06fd4d369ae18447dadf6ca9107e7bdbc727 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/supermicro: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie43c93c371073b4fe071b08522f351d0e20ed561 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/up: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I4d37fabe34265166019cdbbbe4ccb9772b87bff8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Iaabbc58a7089b28ebe23df3a04464234ff465486 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/compulab: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Iab4fb613bd33bc29630126a487525087c0fe7177 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/elmex: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I957a5e19c5ce39203e4afb94cbcb3d2961fdfb43 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/bap: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic93a89a2d5cbae851a3ed0d1f04055a182bbb85b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04mainboard/asrock: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I32c5f5e865b5455ddb7034612ecea1383932cef9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-04mainboard/facebook: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I311c62e8321afa43fdb442e10158973ecdcca793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-04mainboard/portwell: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id24c3a4fa195ccaafeb1932482c17562213505a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-04src/device: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id5fe26564147ec532850430ea55b19ee94d5c5a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04sb/intel/bd82x6x: Use SPDX headersAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I08b4f5f53e493371848f588e6976d349e56b0620 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40019 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04src/vendorcode: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I49dc615178aaef278d6445376842d45152759234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-04src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04soc/intel/xeon_sp/cpx: Add multi-core initAndrey Petrov
Add minimal MP init. No SMM, no turbo, not c/p states. TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-04src/commonlib: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I29e746115e3b0630238176a0f913a3b5340962eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04src/console: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib8a40e5633faf840e19a35bcdc8edc7e7cdd0ad9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-03libpayload: malloc: Change memcpy() to memmove() in reallocJulius Werner
Our realloc() works (somewhat suboptimally) by free()ing the existing allocation and then reallocating it wherever it fits. If there was free space before the old location, this means the new allocation may be before the old one, and if the free space block is smaller than the old allocation it may overlap. Thus, we should be moving memmove() instead of memcpy() to move the block over. This is not a problem in practice since all our existing memcpy()s are simple iterate and copy front to back implementations which are safe for overlaps when the destination is in front of the source. but it's still the more correct thing to do (in case we ever change our memcpy()s to do something more advanced or whatever). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I35f77a94b7a72c01364ee7eecb5c3ff5ecde57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-03mb/google/auron: Add support for ACPI backlight controlsMatt DeVillier
Test: build/boot lulu and samus variants, verify backlight control functional under Windows 10. Change-Id: I4725fdea5206ae03df14a8b07e51fdf09f1edebd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-03mb/google/rambi: Disable console output by defaultMatt DeVillier
Disable SoC serial output by default, since no production devices have this exposed, but leave it as a user option so it can be selected as needed (eg, for use with a Google debug servo). Same change as made for google/cyan in CB:39872 Change-Id: Id6b2c28658aca03d8c5042d719a0f6f504c29288 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-03mb/google/rambi: Convert to use override devicetreeMatt DeVillier
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/cyan: Adjust ACPI interrupt triggering for audio codecsMatt DeVillier
The jack detect GPIOs are initialized as dual edge-triggered GPIs, and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or ActiveBoth -- a single interrupt is detected on jack insertion or removal. The Windows drivers on the other hand, will not function unless the codec and LPE ACPI interrupts entries are set as in the Intel Cherry Trail Tianocore platform reference code. So adjust the ACPI interrupt triggers to make Windows happy, since Linux doesn't care either way. Test: boot Linux (GalliumOS 3.1) and Windows 10 on google/edgar, observe functional audio output for both built-in speakers and headphones. Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/24989 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/cyan: Adjust CID for realtek audio codecMatt DeVillier
Adjust CID to allow for Realtek's Windows drivers to attach without breaking functionality under Linux. Both Linux and Windows use ACPI HID/CID matching for driver attachment. Since the Realtek 5650 isn't used in standard Windows laptops, the '10EC5650' HID/CID isn't contained in the Windows drivers' lookup file (.inf), but a catch-all 'INTCCFFD' entry does exist, so concatenate that to the existing CID to allow the drivers to attach. Test: build/boot google/edgar, verify working audio under both Windows 10 (with Realtek drivers 10.0.10586.4393) and Linux (GalliumOS 3.1 / kernel 4.16.18, Manjaro 18.1 / kernel 5.1.x) Change-Id: Idca5cc86ba1f5ef3978cfba291a0c06e56ef5958 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40003 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/cyan: Switch eMMC and SD from ACPI to PCI modeMatt DeVillier
Braswell boards don't work well with the eMMC and SD controller in ACPI in payloads other than depthcharge - SeaBIOS requires an onerous workaround (manually determining the PCI BAR0 address for each eMMC and SD controller, then adding adding etc/sdcard entries to the CBFS), and Tianocore can't see the devices at all. To make the common use-case work better, switch to PCI mode. Test: build/boot cyan variants with SeaBIOS and Tianocore payloads, verify eMMC and SD card visible and bootable to both payloads and OSes. Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40002 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/cyan: convert to overridetreeMatt DeVillier
Simply cyan variants by converting to overridetree format. A few differences were ignored as there appears to be no reason behind them: - cyan had PCIe RP2 enabled, but nothing is attached to it - kefka had the SPI 1 device disabled - reks, relm, and ultima had HSUART 1 disabled - edgar had I2C1 UPD disabled Test: build/boot cyan and edgar variants, verify everything still works Change-Id: I9928cc59adcfda4661ddfdfa95f53a7820053b4a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/glados: convert to overridetreeMatt DeVillier
Simplify glados variants by converting to overridetree format. Change-Id: I6dd7a4b1ae7f1d3ce9fadb06ea95e021a1c880a5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39983 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/glados: drop VR configs from devicetreeMatt DeVillier
The VR config values used in the variants' devicetrees is identical to the domain defaults in vr_config.c, with the exception of the icc_max value, which is calculated dynamically based on SKU, and again matches the default values for each domain and each varaint. Test: add a print function to dump the VR config values for each domain from the UPDs after setting, verify same output before/after. Change-Id: I4307f6e19ae6f99d4f5e475b181fd66c5b92f28c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39982 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/glados: clean up variant devicetreesMatt DeVillier
In preparation for conversion to overridetree format, clean up the variant devicetrees in order to minimize the differences across glados variants. This entails: - minor reformatting and reordering of devicetree entries - addition of setting default values on boards which skipped them - disabling unused I2C2 on boards which left it enabled - ensuring TCC offset set for all SKL-Y boards - setting VR mailbox command 1 for caroline - skipping init for UART2 on cave and glados - dropping unused PCIe RP5 for sentry Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03soc/intel/skylake: vr_config: enable PSI3 and PSI4 by defaultMichael Niewöhner
There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled since at the time the defaults have been defined (2015) there were bugs in FSP in this regard. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series These boards have a MPS MP2955 which we can assume support for PS3 (the MP2965 and MP2935 support it, too). S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and since only C10 makes use of PS4, those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. - 51nb/x210: Needs testing and/or VR datasheet check for PS3/PS4 support Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03mb/google/auron: Convert variants to use override devicetreeMatt DeVillier
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. As part of the cleanup, drop unused PCIe RP5 for buddy as well. Test: build all auron variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-03Doc/mb/index.md: Fix mainboard vendor orderAngel Pons
Oops, Libretrend "stole" all the Thinkpads from Lenovo. Correct that. Change-Id: I15f189dedab98fdbea8c26ceb8ac84486df2519b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40118 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/intel/braswell: add ACPI backlight supportMatt DeVillier
Add hook to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0adccc6c8bee71d3c1b7840518308c8dc8ea2d81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02soc/intel/baytrail: add ACPI backlight supportMatt DeVillier
Add hook to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0b7fc45bda3aaf89306bedb579fb1e9f8ce07926 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02mb/google/beltino: drop ACPI brightness control stubMatt DeVillier
beltino variants are Chromeboxes without built-in displays, so now that default_brightness_levels.asl is no longer required for all boards in a platform, drop it. Change-Id: Ie8147763fc9fdf4f184d3d000bffd6794e134d9e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02mb/google/poppy: Add support for ACPI brightness controlsMatt DeVillier
Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02drivers/intel/gma: drop intel_gma_get_controller_info()Matt DeVillier
Drop function prototype, since all implementations have been removed. Change-Id: I2e7b5ac7352a1434652b5e6d37bb3744c68b2328 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02mb/emulation/qemu-q35: drop unused intel_gma_get_controller_info()Matt DeVillier
No longer needed anywhere. Change-Id: Ifeea76af44377d917ec46cac0d9d7375d1a68204 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/pineview: drop intel_gma_get_controller_info()Matt DeVillier
No longer used by southbridge, no longer needed since pineview doesn't utilize drivers_intel_gma_displays_ssdt_generate() Change-Id: Ia386f8fcd208e201fb8bc2a37cdbecd6f45a044b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39960 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02nb/intel/gm45: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Ideddfc3d327c4421faffb6583e347cd2b094e155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/i945: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: I68848516fab2058d4aa96ac0342c883fd1df2d6d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/x4x: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Iacce01ab7d6c220779e84c2b695fbb597b493586 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/ironlake: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: I1b6d57c091441aa7431061b1f16135d54cc97b47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/sandybridge: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: If34ebe0edc46674244c9d5afc7ed165c2ad685ba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/haswell: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Icd9caf622dd4c46b13589ebb772138b25888752f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/ibexpeak: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ibb7898ab4fbbbfcd29b6ba72367cc55a02cd4b1e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/i82801jx: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Iecd8559f660cc748c417ec94b7a822e16603cbd8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/i82801ix: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Remove direct setting of gnvs->ndid in qemu-q35 board since build will otherwise break. Change-Id: Ifbf08f43291c1fff7ccbc85272dc97334207983b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39954 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02sb/intel/i82801gx: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: I51a11e7ed6686ab67dac3f02097457ea9c6a7e6a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/bd82x6x: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ie7491409681d8c2721dd6d6a16a8d5004cd0cf8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/lynxpoint: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Iec3a18871725fd5f5c4c568c2bd771bb56245bc7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02soc/intel/broadwell: add ACPI backlight supportMatt DeVillier
Add framework to generate ACPI methods in SSDT for screen backlight control. Adjust params for gtt_ methods to match prototypes in i915.h and avoid conflicts. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: If93b7690ef36b5d19ca43957e8a1bef91ec5821d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02drivers/intel/gma/acpi: Bail out on empty display listNico Huber
Whether the GMA is used depends on the mainboard, so we shouldn't rely on the presence of the static ACPI code around `GFX0`. Change-Id: I4d20b459b8361e43435b535b2b395f51ce1704e6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/intel/tigerlake: Add macros and SPD information for DDR4Furquan Shaikh
This change adds new memory topologies (SODIMM, MIXED) that are supported by DDR4 and macros required for DDR4 support. Memory initialization support for DDR4 will be added in a follow-up change. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-02soc/intel/tigerlake: Reorganize memory initialization supportFurquan Shaikh
This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added. 1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration. TEST=Verified that volteer still boots and memory initialization is successful. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-02soc/amd/common/psp: Move definitions into a private fileMarshall Dawson
Declutter psp.h by removing internal details the caller doesn't need to know. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: I2fb0ed1d2697c313fb8475e3f00482899e729130 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020366 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40015 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/amd/common/psp: Move early init to socFelix Held
The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-02soc/amd/common/psp: Consolidate FW blob load functionsMarshall Dawson
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands. Consolidate the two functions used for interpreting the command and applying the command into a single one. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Tested-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-02soc/amd/common/psp: Make common function to print statusMarshall Dawson
Consolidate commands' printing of status into one static function. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020363 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39998 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02mb/google/volteer: Create Malefor variantWilliam Wei
This commit creates a malefor variant for Volteer. The initial settings override the baseboard was copied from variant ripto. Fine tune GPIO and memory DQ based on malefor schematics. BUG=b:150653745 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Idbeebb13e537287686344740211143df35b7863a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02google/trogdor: Add 'Lazor' derivativeJulius Werner
This patch adds GOOGLE_LAZOR which is just a copy of GOOGLE_TROGDOR for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0dca8e1c29bdd91625d58b3cb583b530ed925e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-01security/tpm: Fix compile-time elimination for SEPARATE_VERSTAGEJulius Werner
CB:35077 pulled TPM measurement code into the bootblock, with the catch that we'll only cache PCR extensions and not actually write them to the TPM until it gets initialized in a later stage. The goal of this was to keep the heavy TPM driver code out of the size-constrained bootblock. Unfortunately, a small mistake in the tspi_tpm_is_setup() function prevents the compiler from eliminating references to the TPM driver code in the bootblock on platforms with CONFIG_VBOOT and CONFIG_SEPARATE_VERSTAGE. In those cases vboot_logic_executed() is known at compile-time to be 0, but that still makes the final expression `return 0 || tpm_is_setup;`. We know that tpm_is_setup can never be set to 1 in the bootblock, but the compiler doesn't. This patch rewrites the logic slightly to achieve the same effect in a way that the compiler can follow (because we only really need to check tpm_is_setup in the stage that actually runs the vboot code). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idc25acf1e6c02d929639e83d529cc14af80e0870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39993 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-01soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoCAamir Bohra
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-01drivers/pc80/rtc: Always load cmos.default if measured boot is enabledBill XIE
cmos.default used to be loaded only when cmos is needed to be reset, but conditional loading of CBFS files may change the calculated PCRs if measurement is hooked on each loading. In order to resolve this, loadings should be made less conditional, (if a file might be used, it should be loaded and measured) but the use of loaded data remains conditional. Change-Id: If6ea0d1cbaa7d96f7dea7e77b7548ca2b30efe9e Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39906 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-01cros_ec: add chrome EC headers to include pathCaveh Jalali
This adds the path to chrome EC headers to the depthcharge build. Depthcharge currently includes a manually maintained copy of the EC headers which are perpetually out of sync with the real interface definitions. By adding the include path, we can build depthcharge with the actual EC interface definitions and eliminate the manual maintenance of copies of EC headers. Once the include path is in place, we can remove the copies of the EC headers from depthcharge. BUG=b:152373049 Change-Id: I1ce0ad9dc99ea52f177d4fb034fd23efd95a7864 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-01Remove myself from MAINTAINERS filePhilipp Deppenwiese
I will pass my responsibilities to Christian Walter. I have hardly any time left for the coreboot project. Change-Id: Ia60e71c5cbd361486dbc924ad954db203e285a5a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-03-31superio/fintek: Improve code formattingElyes HAOUAS
Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31vendorcode/intel/fsp: Update FSP header for Tiger LakeRonak Kanabar
Update FSPM header to include DisableDimmCh Upds for Tiger Lake platform version 2457. BUG=b:152000235 BRANCH=none TEST="Build and Boot on Ripto/Volteer" Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-31superio/{acpi,common}: Improve code formattingElyes HAOUAS
Change-Id: I879ac7b558781d559a65c97fc8b914ecc4ad3f0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/ite: Improve code formattingElyes HAOUAS
Change-Id: I014659aaddeb9fa2d5c3c3583e9379be4f9db69b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39929 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31superio/nuvoton: Improve code formattingElyes HAOUAS
Change-Id: I8cdfa5c3e3508ea8ad969df6513401611a066fc5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39930 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31superio/winbond: Improve code formattingElyes HAOUAS
Change-Id: Ia63e21b957d89690f36929f9ffbe8a7bf8f0e84c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/smsc: Improve code formattingElyes HAOUAS
Change-Id: Ia9a3f7795178400de39b36471f4169a9f5a3b08b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESAMichał Żygowski
Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31soc/intel/common/block: Add missing includeRizwan Qureshi
Include types.h in src/soc/intel/common/block/include/intelblocks/cse.h to use type bool. Without this, there can be a build error like below, src/soc/intel/common/block/include/intelblocks/cse.h:208:1: error: unknown type name 'bool'; did you mean '_Bool'? bool cse_is_hfs1_com_soft_temp_disable(void); ^~~~ _Bool src/soc/intel/common/block/include/intelblocks/cse.h:214:1: error: unknown type name 'bool'; did you mean '_Bool'? bool cse_is_hfs3_fw_sku_custom(void); Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I92ee533bca7dc255f7a341b2a68bbc09900996a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31device/Kconfig: fix circular dependency for RUN_FSP_GOPMatt DeVillier
Change Graphics Init default for RUN_FSP_GOP to depend on INTEL_GMA_HAVE_VBT rather than INTEL_GMA_ADD_VBT, since RUN_FSP_GOP selects INTEL_GMA_ADD_VBT for several Intel SoC's. Test: create default config for gogle/cyan, RUN_FSP_GOP still default display init selection but no more circular dependency warning from config. Change-Id: I8b978d9938c3d0024d4dd40000b988430664cee7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-31drivers/intel/gma: fold gma.asl into default_brightness_levels.aslMatt DeVillier
Including gma.asl at the platform level (vs the board level) means that even desktop boards need to include the default brightness levels, which makes no sense. To begin to clean this up, include gma.asl in default_brightness_levels.asl (as well as the handful of board-specific brightness files) and remove it from the various platforms. A follow-on commit will remove default_brightness_levels.asl from all boards which lack an internal display. Change-Id: I8063deeef4ab6d6ab34ed9b0be5b1d541d6e9b6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39878 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31mb/emulation/qemu-q35: Enable CHROMEOS as an optionDuncan Laurie
Allow Chrome OS to be enabled for this QEMU target. By default this does not change anything unless it is selected in the build configuration, but it makes it possible. Native VGA init is not forced when Chrome OS is enabled because the drm-bochs driver does not work with chrome (even the latest upstream kernel driver with drm atomic support) but it does work with virtio. The coreboot graphics init needs to match what is selected with qemu (with -vga std or -vga virtio) which in turn will determine which kernel driver is used. A second FMAP is added with both RW-A and RW-B regions which is required by chromeos. Recovery mode can be entered by supplying a custom fw_cfg option when launching qemu: -fw_cfg name=opt/cros/recovery,string=1 Change-Id: I24b4532ea961e68558663292c99d121f0a30ce3b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31mb/emulation/qemu-q35: Enable option for TPMDuncan Laurie
This enables the mainboard to use a TPM if it is selected in the configuration. By default this does nothing, but it allows the TPM to be enabled and used with the CONFIG_USER_TPM2 Kconfig option. Using a TPM with QEMU requires either a physical TPM backend or the swtpm package with a socket: -chardev socket,id=swtpm,path=/tmp/swtpm/socket -tpmdev emulator,id=tpm0,chardev=swtpm -device tpm-tis,tpmdev=tpm0 Change-Id: I0d79a5a0f590c57998ababb660b52d9e3ed2d484 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31mb/emulation/qemu-i440fx: Add acpi_name handler for QEMUDuncan Laurie
QEMU does not have a separate northbridge chip, so the mainboard needs to handle the ACPI name and paths so that devices can get generated into the SSDT properly. This fixes the PIRQ and TPM table generation. This issue can be seen in the coreboot output: ACPI_PIRQ_GEN: Missing LPCB ACPI path Change-Id: Ifc7d4359eea38ac0b55d655e39191ae7f8655fe4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>