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2015-04-13storm: Fix timer init order problemJulius Werner
Commit 257aaee9e3a (arm: Add bootblock_mainboard_early_init() for pre-console initialization) inadvertently moved the timer initialization after console initialization for IPQ806x, which is apparently not a good idea for this platform. This patch solves the issue by moving init_timer() to bootblock_mainboard_early_init(), which is the new hook explicitly provided to perform pre-console tasks. BRANCH=None BUG=None TEST=Built and booted Storm with 257aaee9e reverted. Noticed that it was already broken. Bisected coreboot and tracked down breakage to commit a126a62f (ipq8064: use the new utility to build bootblock). Built and booted successfully with this patch and a revert of a126a62f to confirm that the bug in question here is fixed. Change-Id: I4a3faa2aec8ff1fbbe6c389f1d048475aa944418 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 752d1f879f9bd841f18bd84842491f747458cf52 Original-Change-Id: Ie4aa2d06cb6fda6d5ff8dd5ea052257fb7b8a24b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233290 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9574 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ipq806x: copy i2c, qup, and gsbi drivers from depthchargeDaisuke Nojiri
this is a preparation for porting these drivers to coreboot. the code will be modified by the following patches. BUG=chrome-os-partner:33647 BRANCH=ToT TEST=None Change-Id: I2baeed5b6130ace2515d6e28115f8d1008004976 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7c03a186a599be9d274c6fcdea1906529cc117d7 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I9f3428ef02d2ba15ae63c99b10fe0605dd595313 Original-Reviewed-on: https://chromium-review.googlesource.com/231461 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13storm: add hard_reset templateDaisuke Nojiri
this is required to do early firmware selection using vboot2. actual implementation can be done later. BUG=chrome-os-partner:33755 BRANCH=ToT TEST=Booted storm. Change-Id: I8e9e168ea6fa3af149d5ad4ca51c5c9bba4d986d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 611c24773478c8c212d567bb4f2cb9a09898ddc8 Original-Change-Id: Idd1a1de4991a19902ffe45f01be89d47f4413779 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229425 Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13util/ipqheader: Add utility to create uber-SBL for IPQ8064Vadim Bendebury
With the Storm image layout reworked, the very first blob read out of NOR SPI flash by the IPQ8064 maskrom is supposed to be a concatenation of three binaries: one to run on RPM, another one to run on AP, and the third one - the actual coreboot bootblock. This layout allows to greatly reduce the size and complexity of the two first blobs, as they do not need to include the SPI driver. The first binary in the input file list starts with the combined header, describing the rest of the blob. This utility copies the first input file into output, updating the combined header with the total size of the concatenated binaries. The second and third binaries in the combined image are required to be aligned at 256 byte offsets in the file as counted from the end of the combined header. The new utility allows to concatenate two or three files, always expecting the first file to be prepended by the combined header. For further reference below is the utility's help message: mbncat.py: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock] Concatenates up to three mbn files: two SBLs and a coreboot bootblock -h This message -v verbose -o Output file name, (default: sbl-ro.mbn) BRANCH=none BUG=chrome-os-partner:34161 TEST=run the new utility and compare the result with the output of the vendor provided tool. The output files are exactly the same. Change-Id: I1d3b3634ecc3f46ea88adb9b6c4fbfc017cc06ac Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 94008340bc5eaf19d286b3feaa4091e5c5e285aa Original-Change-Id: I00724f7c75703fc90d7971c3cb337c33ca96f2b5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232047 Original-Reviewed-by: Manoj Juneja <mjuneja@qti.qualcomm.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9572 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13mips: disable caches in bootblock startup codeVadim Bendebury
Until proper MIPS cache management is available it is necessary to disable data and instruction caches, otherwise code placed in memory stays in data cache and is not available for instruction fetched. BRANCH=none BUG=chrome-os-partner:31438,chrome-os-partner:34127 TEST=coreboot loading rombase and rambase now succeeds. Change-Id: I4147e1325edc0b9bb951cd7ce18d5f104f3eaec0 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 93d5bfa1d01fbbabbabef33a22287ceeea28b15b Original-Change-Id: Ib195ed6e5f08ccaa6bbe3325c2199171bfb63b88 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232191 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9569 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13tpm: Only expose base address Kconfig option when enabledPatrick Georgi
Change-Id: Ia8ddd689a3bf09ed68f94907ea19d4d2ee874542 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/9594 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13rk3288: Move UART initialization to bootblock_mainboard_early_init()Julius Werner
This patch uses the new bootblock_mainboard_early_init() hook to run the UART pinmuxing on rk3288-based boards before initializing the console. This allows us to get rid of the hacky second console_init() call in bootblock_soc_init(). We can also simplify the pinmux selection a bit since we know that a given board always uses the same UART (still keep an assert around to be sure, though). BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Change-Id: I3da8b0e4bd609f33cedd934ce51cb20b1190024b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: caabda8fc1ddb4805d86fd9a0d5d2f3cf738bfaf Original-Change-Id: Ia56c0599a15f966d087ca39181bfe23abd262e72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13arm: Add bootblock_mainboard_early_init() for pre-console initializationJulius Werner
On most platforms, enabling the console and exception handlers are amongst the very first things you want to do, as they help you see what's going on and debug errors in other early init code. However, most ARM boards require some small amount of board-specific initialization (pinmuxing, maybe clocks) to get the UART running, which is why bootblock_mainboard_init() (and with it almost all of the actual bootblock code) always had to run before console initialization for now. This patch introduces an explicit bootblock_mainboard_early_init() hook for only that part of initialization that absolutely needs to run before console output. The other two hooks for SoC and mainboard are moved below console_init(). This model has already proven its worth before in the tegra124 and tegra132 custom bootblocks. BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Daisy, Storm and Ryu. Change-Id: I510c58189faf0c08c740bcc3b5a654f81f892464 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f58e84a2fc1c9951e9c4c65cdec1dbeb6a20d597 Original-Change-Id: I4257b5a8807595140e8c973ca04e68ea8630bf9a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231941 Reviewed-on: http://review.coreboot.org/9603 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13arm: Redesign mainboard and SoC hooks for bootblockJulius Werner
This patch makes some slight changes to the way bootblock_cpu_init() and bootblock_mainboard_init() are used on ARM. Experience has shown that nearly every board needs either one or both of these hooks, so having explicit Kconfigs for them has become unwieldy. Instead, this patch implements them as a weak symbol that can be overridden by mainboard/SoC code, as the more recent arm64_soc_init() is also doing. Since the whole concept of a single "CPU" on ARM systems has kinda died out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had already been done on Storm/ipq806x, which is now adjusted to directly use the generic hook.) Also add a proper license header to bootblock_common.h that was somehow missing. Leaving non-ARM32 architectures out for now, since they are still using the really old and weird x86 model of directly including a file. These architectures should also eventually be aligned with the cleaner ARM32 model as they mature. [pg: this was already partly upstreamed. These are the remains. Further cleanup is necessary and on the short-term TODO, but beyond the scope of this commit] BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Storm and confirmed in the disassembly that bootblock_soc_init() is still compiled in and called right before the (now no-op) bootblock_mainboard_init(). Change-Id: Idf655894c4fec8fce7d3348d3b3e43b1613b35db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 257aaee9e3aeeffe50ed54de7342dd2bc9baae76 Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231940 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9602 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13rush: Add and select DO_SOR_INIT config optionJimmy Zhang
Select DO_SOR_INIT to enable dp display api BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Iddf19195722856865a7c06ce96492012ab729184 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 31492f51c030aeb7a3ac792a02665642ec999405 Original-Change-Id: I4daca43239235ca6d233c4457096d3b98fcaf65c Original-Reviewed-on: https://chromium-review.googlesource.com/234274 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: Add and select DO_DSI_INIT config optionJimmy Zhang
Enable display supporting functions by select DO_DSI_INIT BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: Ie0e03506702ddab03d7f3fd2528c67c02126c7be Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7133dfcd1afa221be92c6398221cf210d9eddf17 Original-Change-Id: I3a9f93107333ebf83ff235eb1b1e02fc747df3c6 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: display: Move display api to mainboardJimmy Zhang
Display configuration is board specific. The change here is preparing for supporting other than dsi interface. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and test dev/rec mode, also build rush ok Change-Id: Ied39d5d539d2be4983ab70976bffbe51fccba276 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 36be6b2e35c6246d5384d71b9ab9d4ddbf17764a Original-Change-Id: I494a04f7d6c0dbad2d472f4c2cd0aabfb23b8c97 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234271 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: display: Split dc functions from dsi display codeJimmy Zhang
dc supporting functions can be used for other than dsi display interfaces. This change is preparing for supporting sor display interface. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and test dev/rec mode, also build rush ok Change-Id: I8a310e188fae70d7726c4360894b392c4546e105 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a7ab7225e3419a0fd93894dbb9a959390f29945b Original-Change-Id: Id14cbd89457cb91c23526927a432f4eb7cc6291b Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234270 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: audio: Setup I2S1/DAP2 and EXTPERIPH1/MCLK muxes correctlyTom Warren
This configures I2S1 and the codec MCLK muxes to pass the PCM audio data to the RT5677 codec. Once depthcharge RT5677 codec driver changes are in, audio 'beeps' should be heard on boot (Ctrl-U / devmode/recmode). BUG=chrome-os-partner:32582 BRANCH=none TEST=Built and booted Ryu/A44. Change-Id: I2143d544c75ee7e03ffc809561171920650e8d7d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 600c12ddf3543d2dcb47fd3e2f0704803dac5957 Original-Change-Id: Ib071bcb41fba8f6d628a386ed233ec84a54b0323 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233945 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13rush: audio: Setup I2S1/DAP2 and EXTPERIPH1/MCLK muxes correctlyTom Warren
With this change, audio 'beeps' are heard on boot if Ctrl-U is pressed, or devmode/recmode is entered. I also tested via an explicit call to VbExBeep in the kernel boot path. Note that a couple of Rush CLs for depthcharge are needed for audio, too. BUG=chrome-os-partner:32582 BRANCH=none TEST=as above. Built and booted Rush/Norrin64. Change-Id: I43c65a4d11c5ab7b16289e19f3b42cfc0300ea7c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4a682fb2403f7c6d53e74bfa945481242577f6c3 Original-Change-Id: Ia37f077569afd806ce6574c4c58813fd7aca1644 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233671 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9579 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13rk3288: Increase the delay after DDR reset de-assert to 10us.Dailunxue
After DDR PHY reset de-asserted, DLL automatically starts to lock, and the lock time is maximum 5.12us. The output clock of DLL supplies the clocks of DDR controller and PHY digital logic. So before DLL lock, the clocks of DDR controller and PHY digital logic are indeterminate. When programming DDR in the period of DLL unlock, the programming maybe unstable because of the indeterminate clocks. So we need wait for at least 5.12us after de-asserting reset, then start to program DDR registers. 10us provide some safety margin. BUG=chrome-os-partner:33148 TEST=I'm using the following command line test ok(15000 cycles). "while sleep 4 && dut-control cold_reset:on sleep:.1 cold_reset:off; do : ; done" BRANCH=None Change-Id: Ie7d615f5a2264c615c4b4413d6b828cd3d78cd2b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 54e1a439c0e29aaf4fc542ae756f7bb036ceaf3e Original-Change-Id: I55f8cb11ed3d7962567c5f40a31e6c8aed8fdcb0 Original-Signed-off-by: DaiLunXue <dlx@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/232894 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lunxue Dai <lunxue.dai@rock-chips.com> Original-Tested-by: Lunxue Dai <lunxue.dai@rock-chips.com> Reviewed-on: http://review.coreboot.org/9578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13t132: Add I2S1 support to funitTom Warren
Used for audio on Rush/Ryu. I2S1/DAP2 provides the audio 'stream' for the dev/rec mode 'beeps'. BUG=chrome-os-partner:32582 BRANCH=none TEST=With follow-on CLs that make use of this support, audio beeps (via VbExBeep) can be heard on Rush. Built both Rush and Ryu OK. Change-Id: Iea5559db4431e48001adbbce17fa0f3aaaf8387c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2bd701a5f4186e49739b25f4afd5000d5d9b4970 Original-Change-Id: Ia8c32303979f25300e22b5a14609d9d9d5ce3132 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233670 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9576 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13rush: Add gpio config for PWR button and LID open switchJimmy Zhang
Due to CL https://chromium-review.googlesource.com/231250, depthcharge now detects gpio state based on gpio configurations done by coreboot instead of redoing configuration at depthcharge. However, PWR button and LID open pins have not been configured in coreboot. So, add the missing code here. Otherwise, TOT coreboot/depthcharge rush build can not load in kernel. BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush and test with pwr button press and lid switch Change-Id: I7acc5e021fa769f68d4cbfd7202df325d4ea73c2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a25dff24a2dcd33fcd15eb766432414af215c3ab Original-Change-Id: I6c322cd987967920f236aae653294db079678408 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13nyan/rush/veyron: Align ChromeOS GPIOs to new modelJulius Werner
This CL makes slight changes to the ChromeOS-specific GPIO definitions of Tegra and Rockchip boards to prepare them for new features in depthcharge. It adds descriptions for the EC in RW and reset GPIOs, changes the value Tegra writes into the (previously unused) 'port' field to describe the complete GPIO information, and removes code to sample some GPIOs that don't need to be sampled at coreboot time (to help depthcharge detect errors and avoid using a stale value for something that should always represent the current state). BRANCH=None BUG=None TEST=None (tested together with depthcharge patches) Change-Id: I3774979dbe7cacce4932c85810596d80e5664028 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: df295d0432fbf623597cf36ebb170bd4f63ee08d Original-Change-Id: I36bb16c8d931f862bf12a5b862b10cf18d738ddd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231222 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9570 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13Fix dependency issue in Chrome OS vendor codeStefan Reinauer
make *config was complaining about mainboards selecting a virtual dev switch when CONFIG_CHROMEOS is not enabled. While the long term cleanup should be to move the option out of CONFIG_CHROMEOS and make it not be a user changeable option, this approach is contained to vendorcode/ and gets rid of the warning. Change-Id: Id090eb31d1307af7a0d1f9fbe641534dc24b24a9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9301 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13spi: support controllers with limited transfer size capabilitiesVadim Bendebury
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI read and write transactions. Limiting transfer size in the wrapper allows to provide the API user with unlimited transfer size transactions. The tranfer size limitation is added to the spi_slave structure, which is set up by the controller driver. The value of zero in this field means 'unlimited transfer size'. It will work with existion drivers, as they all either keep structures in the bss segment, or initialize them to all zeros. This patch addresses the problem for reads only, as coreboot is not expected to require to write long chunks into SPI devices. BRANCH=none BUG=chrome-os-partner:32441, chrome-os-partner:31438 TEST=set transfer size limit to artificially low value (4K) and observed proper operation on both Pistachio and ipq8086: both Storm and Urara booted through romstage and ramstage. Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45 Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232239 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13broadwell: Fix incorrect SATA port map maskWenkai Du
WPT-LP has 4 SATA ports. Current code assumes 6 SATA ports and as a result, some reserved bits are written with 1. No specific issue has been observed so far. BUG=None BRANCH=None TEST=Verify SATA PCI configure space dump on Auron Change-Id: I737719b3d5cd788158cd5b6991405ba098be4078 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2b55587a74ac5d45354dc123937b562290468855 Original-Change-Id: I9c53ac86e2bf72901647bd2cfa48ac0ce31abea0 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233661 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9479 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13tpm: wait for valid bit to be set in TPM access register before using tpmSourabh Banerjee
As per the TCG PC Client TPM Interface Specification v1.2, bit 7 of the access register (tmpRegValiSts bit) stays "0" until the TPM has complete through self test and initialization. This bit is set "1" to indicate that the other bits in the register are valid. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:35328 TEST=Booted up storm p0.2 and whirwind sp3. Verified TPM chip is detected and reported in coreboot logs. Change-Id: I1049139fc155bfd2e1f29e3b8a7b9d2da6360857 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 006fc93c6308d6f3fa220f00708708aa62cc676c Original-Change-Id: I9df3388ee1ef6e4a9d200d99aea1838963747ecf Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242222 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9567 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot: remove vboot_handoff.h from chromeos.hDaisuke Nojiri
chromeos.h includes vboot_handoff.h, which includes vboot_api.h. since vboot_api.h is not available to non-chromeos projects, build fails for some boards (e.g. glados). this change removes (unnecessary) inclusion of vboot_handoff.h in chromeos.h and fixes other files which rely on indirect inclusion of vboot_handoff.h by making it direct. BUG=none BRANCH=tot TEST=built for cosmos, falco, lumpy, nyan_blaze, parrot, rambi, rush_ryu, samus, storm, veyron_pinky Change-Id: I465e3657c6a0944bc75a669e5e52e74d46b3ec6c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6ace70d721aceae9257288815ce8fd7c6c74b8f5 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I12612773372e358584d12fffaf5f968a46083fab Original-Reviewed-on: https://chromium-review.googlesource.com/245864 Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9566 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot2: Fill vboot1 handoff with correct TPM firmware versionJulius Werner
sd->fw_version represents the version of the *current* firmware, which is not necessarily the same as the one stored in the TPM (and may be 0 in recovery mode). Use the newly added sd->fw_version_secdata instead which contains a more correct value. CQ-DEPEND=CL:244601 BRANCH=veyron BUG=chrome-os-partner:35941 TEST=Booted Jerry in recovery mode, confirmed crossystem tpm_fwver was corrent (and not 0). Change-Id: I30f5998da5ac518d6fcb7a651eba4e1fabc14478 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: eb8142f69cea34e11f9081caafcaae7a15cc3801 Original-Change-Id: Id95bd8c6412f2e8b2ae643c3b5a3dee13d0d47be Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/244591 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9565 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13The vboot_reference fwlib2 target has changed to fwlib20Bill Richardson
There are multiple vboot APIs (1.0, 2.0, 2.1). We have to be explicit about which library we want to link with. When building firmware, the vboot_reference Makefile should be invoked in one of three ways: TARGET OUTPUT VERSION fwlib vboot_fw.a 1.0 fwlib20 vboot_fw20.a 2.0 fwlib21 vboot_fw21.a 2.1 BUG=chromium:228932 BRANCH=ToT CQ-DEPEND=CL:243980 TEST=manual emerge-veyron_pinky vboot_reference coreboot emerge-samus vboot_reference coreboot emerge-daisy_spring vboot_reference chromeos-u-boot Change-Id: I7dde513c49b8148bf46e8768ae438e1a85af4243 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 5e339cadad4815f061d4e5e20a9c9733f64cc90b Original-Change-Id: I850646117211930d9215693c48f2c30d55a984d3 Original-Signed-off-by: Bill Richardson <wfrichar@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243981 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9564 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13chromeos: add get_recovery_mode_from_vbnv() to vbnv_flashDavid Hendricks
The first platform that used flash-backed VBNV data has a physical recovery switch, get_recovery_mode_from_vbnv() was never implemented. This patch adds get_recovery_mode_from_vbnv() similarly to how it's implemented for other vbnv storage in other places. BUG=chrome-os-partner:34436 BRANCH=none TEST=needs testing Change-Id: Ifd795c5c1ff0f23619fd2125b4795571af03ece1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 09f1bf96089bf9d159e4220c1f4d99388d709545 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9cf18c988eaa4b7e720d6c66a02b1c5c63b473e9 Original-Reviewed-on: https://chromium-review.googlesource.com/239978 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9563 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13chromeos: Reverse FMAP signature constant to avoid having it in .rodataJulius Werner
Even though coreboot always hardcodes the FMAP offset, the same is not possible for all other tools that manipulate ROM images. Some need to manually find the FMAP by searching for it's magic number (ASCII "__FMAP__"). If we do something like 'memcmp(fmap_buffer, "__FMAP__", ...) in coreboot code, it has the unfortunate side effect that the compiler will output that very same magic number as a constant in the .rodata section to compare against. Other tools may mistake this for the "real" FMAP location and get confused. This patch reverses the constant defined in coreboot and changes the only use of it correspondingly. It is not impossible but extremely unlikely (at the current state of the art) that any compiler would be clever enough to understand this pattern and optimize it back to a straight memcmp() (GCC 4.9 definitely doesn't), so it should solve the problem at least for another few years/decades. BRANCH=veyron BUG=chromium:447051 TEST=Made sure the new binaries actually contain "__PAMF__" in their .rodata. Booted Pinky. Independently corrupted both the first and the last byte of the FMAP signature with a hex editor and confirmed that signature check fails in both cases. Change-Id: I314b5e7e4d78352f409e73a3ed0e71d1b56fe774 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1359d2d4502eb34a043dffab35cf4a5b033ed65a Original-Change-Id: I725652ef2a77f7f99884b46498428c3d68cd0945 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240723 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9562 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vbnv flash: use proper SPI flash offset for NVRAMVadim Bendebury
The current vbnv flash code mistakenly uses the offset into the NVRAM area as the absolute offset into the SPI NOR. This causes overwrites RO section of the flash (when it is not protected) and causes failures to retrieve the NVRAM contents by the user space apps. This patch makes sure that the correct offset is used when accessing NVRAM area in the SPI flash. BRANCH=storm BUG=chrome-os-partner:35316 TEST=run the update code on storm. - no more RO section corruption observed - running 'crossystem recovery_request=1' at Linux prompt causes the next boot happen in recovery mode Change-Id: Iba96cd2e0e5e01c990f8c1de8d2a2233cd9e9bc9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9fd15ff4b7aa77536723edbb94fa81f0ae767aed Original-Change-Id: I86fe4b9a35f7c16b72abf49cfbfcd42cc87937e3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240143 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9561 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13chromeos: Move common VBNV offsets to a headerDavid Hendricks
Some common VBNV variable offsets were defined in multiple vbnv_* source files. This moves them to a header so that we can avoid duplicating them in the future. BUG=none BRANCH=none TEST=compiled for nyan_blaze and rambi Change-Id: Ic292e546b665b40678b4de598783c1f6bfa35426 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fd776f303a3d057d4b70997e7bb6bc85767e2278 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ifcc13c90a910b86d4f9bb0027d913572c1d6d00b Original-Reviewed-on: https://chromium-review.googlesource.com/239977 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9560 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot1: Set BEFORE_OPROM_LOAD flag for VbInit()Duncan Laurie
This sets the new VB_INIT_FLAG_BEFORE_OPROM_LOAD flag for VbInit() to indicate that we are running from early firmware before option rom loading has occurred so it can do the right thing when it checks whether or not to tell the system to reboot after setting the VbNv flag. BUG=chrome-os-partner:32379 BRANCH=samus TEST=pass FAFT tests on samus Change-Id: Id432dc154736baa799d9ddf5a6a25bccc66217ef Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8a576b0bf4b912f85a4e82bfe2cf13c838a069cc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I6968fcb6cda74e88f56bea6ea9bbf77cc795b8d6 Original-Reviewed-on: https://chromium-review.googlesource.com/230887 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9559 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13elog: Fix regression that caused elog to omit "System boot" eventJulius Werner
CL:243671 moved the initialization of elog_initialized around, which is now unfortunately so late that the ELOG_TYPE_BOOT event gets omitted because the code believes the log to be broken at that time. Good thing we now have a FAFT test for these things that I had of course been too lazy to run. -.- The real reason for moving that line was to put it after any point in elog_init() that could still error out. The problem is that we might add the "cleared" event before we try to shrink (which can fail and cause an error)... but those two things cannot happen at the same time, so it should be okay to flip them around and mark the elog as initialized in between. BRANCH=none BUG=chrome-os-partner:35940 TEST=Ran firmware_EventLog on a Pinky, manually confirmed that I once again get "System boot" events. Change-Id: I12dcf4a8e47d302f6cd317194912c31db502bbaf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4a1c0b861017ca25229b1042c4b37dda33e869f9 Original-Change-Id: I4103779790e1a8a53ecabffd4316724035928ce6 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246715 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9503 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13elog: Correct behavior when FMAP section doesn't exist on ChromeOSJulius Werner
The elog driver has a really stupid bug that checks a result which is stored in an unsigned variable for < 0. Surprisingly GCC does not catch this nonsense right now, and I spent an hour trying out different warning options without finding one that doesn't also bring a load of stupid and unavoidable false positives (the biggest offender being -Wtype-limits, which does exactly what we'd want except for flagging things like if ((u8)var >= CONFIG_VAR_MIN) where the VAR_MIN Kconfig may or may not be 0). So, the only thing we can do is fix this one and wait for the next time something like that blows up. -.- Also change some more code to make the behavior more explicit (the old code already intended to work this way since flash_base is statically initialized to 0, never assigned in the error path and checked later in elog_init()... but there was an error message that incorrectly claimed a different fallback behavior, and explicitly assigning the values makes this easier to see). Finally, add another state to the elog_initialized variable to avoid trying to reinitialize a broken eventlog on every event (if it doesn't work the first time, chances are that it won't work later on during the same boot either). BRANCH=None BUG=chrome-os-partner:35940 TEST=Flashed Jerry with RO 6588.4 and RW 6588.23, observed how it now cleanly enters recovery mode without blowing its bootblock away with stray eventlog entries. Change-Id: I0e5348ba961ce4835c30f7108a2453522095f2ee Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f9798dbf0c2b2e337062ecd84d0f45434343c0d9 Original-Change-Id: I4d93f48d2d01d75a04550d419e023aa42ca95a7a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243671 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9557 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13urara: add support for DMA coherent memory areaIonela Voinescu
The information about the DMA memory area is further passed through the coreboot table to the payload. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; DMA memory area was used to test the functionality of the DWC2 USB controller driver; behavior was as expected. BRANCH=none Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/235910 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9593 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13t132: add RAM repair to cluster 1Yen Lin
RAM repair has to be performed to cluster 1 also. BRANCH=none BUG=none TEST=Test on Rush and make sure RAM repair completes Change-Id: I0daf969a995a2be152270bc06501eaf086a13a97 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6b07894cc737cb192f68e254d522b55d8ca3b2f3 Original-Change-Id: I458e0a66d76318c6a4aa82547c9037c7b969f1e1 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239360 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9592 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot1: Fix compilation error with CONFIG_ARCH_ROMSTAGE_ARM64 enabledYidi Lin
make: *** No rule to make target `build/lib/memset.rmodules.o', needed by `build/vendorcode/google/chromeos/vboot1/vbootstub.elf'. Stop. Fix the error by refering to ./src/arch/arm64/Makefile.inc: rmodules_arm64-y += ../../lib/memset.c rmodules_arm64-y += ../../lib/memcpy.c BRANCH=none BUG=none TEST=build pass on our own MT8173 board Change-Id: Ic870136db1ec9405e3d30caf6085f056bc46a5c2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d317dbe8732abbf7e785466e7d1e07425aac326f Original-Change-Id: I69a7db83154a23f7878e9c604c9b541fb6fa308d Original-Reviewed-on: https://chromium-review.googlesource.com/237974 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/9591 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13broadwell: Enable double self refresh by defaultDuncan Laurie
Rather than enable this in every mainboard just enable it by default for all broadwell devices and let a specific mainboard disable it if needed. BUG=chrome-os-partner:34420 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I6e47c20abf29abfbd1f4b7905914b4c9fadb0ae7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25d3a685893e1c85f7b78e302da3187947a1f84f Original-Change-Id: I26d9f2e2a12d3f2f888ecb5af0d949eec5928f57 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9590 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13pistachio: increase the size of romstage to 36KIonela Voinescu
This is necessary for the subsequent changes that will add to the size of romstage. BUG=chrome-os-partner:31438 TEST=coreboot builds successfully;tested on Pistachio FPGA BRANCH=none Change-Id: I132215bd44708913d878bbd8b6147bef535b52df Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7 Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233871 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13vboot2: use offset to vboot2 work buffer instead of absolute addressDaisuke Nojiri
this change makes vb2_working_data struct point to the vboot work buffer by the offset instead of by the absolute address, which can be different depending on the context (e.g. subprocessor v.s. main cpu). BUG=none BRANCH=tot TEST=booted veyron pinky Change-Id: I2191ca756c4f49441b3a357338f9c84564b58918 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 93f8b1da2b2c81aa3a33892987a71e9e1e7a8eff Original-Change-Id: I4e4c12613304586b7395c5173cf08b8093f59521 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236583 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13arch: armv7: Fix cache sync instructions.Deepa Dinamani
When the i-cache is on and the d-cache is off, the L1 i-cache is still fetching information through L2 cache. Since L2 cache is never invalidated, it has stale information. BRANCH=storm BUG=none TEST=Resolves the invalidate data fetch from i-cache while jumping from bootblock to romstage. Change-Id: Ibaca1219be2e40ce5bbbd1c124863d0ea71d0466 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a13e20f9b242d8193dcb314a2bdc708c6bdfea51 Original-Change-Id: I252682d372bd505f525f075461b327e4bcf70a1a Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236422 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9587 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-11hp/pavilion_m6_1035dx/cmos.layout: Remove unused optionsAlexandru Gagniuc
Some of the options in cmos.layout date back to the K8 days, and have not been used anywhere else, but K8. This makes nvramtool expose a very confusing set of options, most of which have no effect. Clean up the layout before it gets forked again. TEST: Booted linux, and checked 'nvramtool -a' output. Change-Id: I1c5f83790ec89ced4dcf954e4949f8554aef6087 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8378 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-10fmap: allocate memory as much as discovered fmap sizeDaisuke Nojiri
fmap_find used to read 4096 bytes from the fmap offset blindly. instead, we read the fmap header first to calcurate the size of the fmap. Then, we read flash again exactly as much as the discovered fmap. BUG=none BRANCH=ToT TEST=Booted Storm and Peppy. Built all current boards. Change-Id: Iaa50c1bc3401c77b433af11406d4b9d2e4e722e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 755ff66ab0a4d05e6d5410c11a6badb9fcb77a0d Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ie5058d181e6565acb70bf108464682dd0e6c1f64 Original-Reviewed-on: https://chromium-review.googlesource.com/231685 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9556 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rk3288: reset edp after edp clock source selecthuang lin
edp must reset when device power up, otherwise the edp register maybe uncertain, now the edp source clock default select 27M, and in pinky and jerry board we use 24M as edp sourec clock, if we want to reset edp, we must after the clock source select 24M. BUG=chrome-os-partner:34023 TEST=Booted Veyron jerry and read edid normal BRANCH=None Change-Id: I4b03dbabe5d3d595d2d56efb0cd82f510f8d2e1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2292da77cc2322b85c4b4f4f20e4ebcc4c4d060d Original-Change-Id: Ica031d2d52deb539c1a0a56968786d6952b3d0e8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231336 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: http://review.coreboot.org/9555 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10Add google/veyron_mighty boardKatie Roberts-Hoffman
Essentially a copy of veyron_jerry for now. BUG=chrome-os-partner:33269 TEST=build Change-Id: Ie2d115d57fe4b6359fa6bb16a2e85e88ec99e991 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9ec25b9cf2985786e55f0b85c3849ccbd42bddd4 Original-Change-Id: Icc45c8f8bf9f6916ba7187dde277d15cc60df8a2 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230961 Original-Commit-Id: 407b8b74a068220d8051dd0d85d9c4ec3ea14d51 Original-Change-Id: I546dbc41ccd191159e96b851424fcb37902a57ec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231691 Reviewed-on: http://review.coreboot.org/9554 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rockchip: support displayhuang lin
Implement VOP and eDP drivers, vop and edp clock configuration, framebuffer allocation and display configuration logic. The eDP driver reads panel EDID to determine panel dimensions and the pixel clock used by the VOP. The pixel clock is generating using the NPLL. BUG=chrome-os-partner:31897 TEST=Booted Veyron Pinky and display normal BRANCH=None Change-Id: I01b5c347a3433a108806aec61aa3a875cab8c129 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4f863b0b57f2f5293ea8015db86cf7f8acc5853 Original-Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: select VIRTUAL_DEV_SWITCHDavid Hendricks
Like most newer Chromebooks, Pinky and Jerry do not have physical dev switches. BUG=chrome-os-partner:33395 BRANCH=none TEST=built and booted on Pinky, crossystem prints a valid value for devsw_cur instead of an error. Change-Id: If97ffa6f99eb31c05915f3ee82aaf6bd252d29e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db302d7286d3e7df9442928dac1d611a2c103163 Original-Change-Id: I186518a59699d293c7938221b3ae45b27361c255 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229680 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Adapt to new board revisionsJulius Werner
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the power button GPIO changed polarity to low, the 5V_DRV pin for USB power was moved to the AP again (welcome back!), and the EMMC_RST_L is now finally on a port with the right IO voltage so we don't need any weird pull-up tricks anymore. Since there are very few Jerry rev1s around, we'll just move it over to the new code directly without introducing board ID differences (also, because I have no idea how they stuffed it this time... is this one actually called rev2?). BRANCH=None BUG=None TEST=Still boots on my Pinky rev2, though that doesn't say much. Change-Id: Id11044cedcaac5a4ae07e696893823925107a6db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55344a9518ff04edcef01bcd40817e9e4b613717 Original-Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229010 Original-Reviewed-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9551 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Port CPU overshoot preventionJulius Werner
This patch ports commit 567f616f (rk3288: slowly raise to max cpu voltage to prevent overshoot) to Veyron_Jerry. It also fixes include ordering and some comment grammar in the affected code. BRANCH=None BUG=chrome-os-partner:32716 TEST=None Change-Id: I4ac14a38e4b3acc4926d4f51f409ff12d9c841cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 679014bc843788e8d4d5f5c7470ae76f8be5e942 Original-Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228938 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: sdram_get_ram_code() -> ram_code()David Hendricks
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the generic gpio_get_binaries() function to read RAM_ID GPIOs. BUG=chrome-os-partner:31728 BRANCH=none TEST=built and booted on pinky Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115 Original-Reviewed-on: https://chromium-review.googlesource.com/227249 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: use gpio_base2_value() in board_id()David Hendricks
This makes board_id() use the generic gpio_base2_value() function to obtain the value of the board ID straps. BUG=none BRANCH=none TEST=tested on pinky Change-Id: I15c1310889b989c34638fd342011aef5fe7bcec1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcbb8a6998a66531326afe16b232395d49fee64d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I5847bf1c5b26bcaf7d36103f31bb255b31ff8185 Original-Reviewed-on: https://chromium-review.googlesource.com/228370 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5VJulius Werner
LDO7 (VCC10_LCD_PWREN_H) is essentially just a glorified GPIO that turns the real VCC10 regulator on or off. We tried setting it to 3.3V since it matches the VCC33_SYS voltage on the input of that regulator. However, we didn't notice that the LDO only supports going up to 2.5V. This patch changes the voltage to the allowed maximum, which should still work fine as an enable line (and is the same value used by the kernel). This removes an assertion error in the ramstage. Also change the PMIC driver to assert maximum VSEL values based on the LDO, because the lower-voltage ones support one more setting. (LDO3 is actually listed to only go up to 0b1111 in the manual, and has a weird jump from 0b1101 -> 2.2V (skipping over 0b1110) to 0b1111 -> 2.5V. I don't know if that's a documentation error or what they were smoking when they designed that, but we don't need to care for now.) BRANCH=None BUG=None TEST=Booted on Pinky, no more ASSERTION FAILED. Change-Id: I38bf99e38822fd0883fd4d0bd9a1b01143545a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f3149efbc3aa9a03ab3fd5be99d17d9c5e1c87 Original-Change-Id: I68a3bb882cf25d98aca8922ede2a17e1ef6524de Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228292 Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Jerry Parson <jwp@chromium.org> Reviewed-on: http://review.coreboot.org/9547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Remove board ID based assumptionsJulius Werner
The veyron_jerry board code was just copied over from veyron_pinky 1-to-1. The Jerry board IDs start at 1, but there has never been a Jerry rev0 so we can remove the code for board ID 0 from it. BRANCH=none BUG=None TEST=Booted Jerry image on a Pinky rev2, worked fine. Change-Id: I0f2ffdc577934c1695e8d2dcf71512696ac1d5a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aa36da69ac584b845e15282dae100eec27fc7f12 Original-Change-Id: I45a18b288c8d8b1399ceedf582addcce1c7e857d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228254 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9546 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change eMMC enable pin to be pulled (not driven) highDoug Anderson
The eMMC enable pin is in a 3.3V IO domain. Unfortunately the eMMC expects this pin to be 1.8V. The way we were driving this pin would cause the eMMC to pull power through this pin and that was causing current leaks. In future revisions of hardware we should move this pin somewhere more legit. However, in the current hardware we can get things working pretty well by using a pullup to "drive" this pin. This will work in conjunction with the external 100K pullup to give a somewhat reasonable voltage. The eMMC will also not be able to pull much current through this pin, so it can't leak too badly. BRANCH=none BUG=chrome-os-partner:33319 TEST=Boot a kernel that doesn't touch the mux/pulls and see no leak: dut-control --port=${SERVO} vcc_flash_ma -t 5 Change-Id: Ibc25cd090d826c8215be24a0b5c11d97b5281700 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e7a9d7e067ed4dd859387ee63bf654ab9dc529 Original-Change-Id: Iadfc1477cd478773cc9d159e3fbc22b66b8f0f78 Original-Signed-off-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226039 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9545 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10Add google/veyron_jerry boardKatie Roberts-Hoffman
This is essentially a copy of veyron_pinky for now. BUG=chrome-os-partner:33269 TEST=build and boot Change-Id: I151c82f54ece4620953d0db5aedf027a3293926f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 267611f2354be4384de3f05d2459a4e421ee6b4f Original-Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225301 Reviewed-on: http://review.coreboot.org/9544 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: copy WiFi calibration data in the CBMEMVadim Bendebury
Invoke the function which copies WiFi calibration data in a CBMEM table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=verified that the WIFI entry is added to CBMEM when the calibration data is present in the VPD. Change-Id: Icab0a2343e88e1d44575eeb608fdf6588aff255b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 68b96f158633cb3a1f157b5a19da39fa7e78f975 Original-Change-Id: I5fa77da98e37b88da01fb7884e713535fc178006 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9543 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: psci: add cpu_on/off supportJoseph Lo
The CPU on/off functions are the method for the Kernel to support CPU hot-plug function in PSCI. To support this, we still need flow controller support to capture the WFI from the CPU and inform PMC to power gate the CPU core. On the other path, we turn on the CPU by toggling the PMC and use flow controller to let go when the power is steady. BUG=chrome-os-partner:32136 BRANCH=None TEST=built the kernel with PSCI enabled, check both of the CPUs are coming up, test the CPU hot-plug is working on Ryu Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5 Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231267 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: No need of invalidating cache line for secondary CPU stackFurquan Shaikh
With support for initializing registers based on values saved by primary CPU, we no longer need to invalidate secondary CPU stack cache lines. Before jumping to C environment, we enable caching and update the required registers. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu. Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e Original-Reviewed-on: https://chromium-review.googlesource.com/231563 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add support for save/restore registers for CPU startup.Furquan Shaikh
startup.c provides function to enable CPU in any stage to save register data that can be used by secondary CPU (for normal boot) or any CPU (for resume boot). stage_entry.S defines space for saving arm64_startup_data. This can be filled by: 1) Primary CPU before bringing up secondary CPUs so that the secondary can use register values to initialize MMU-related and other required registers to appropriate values. 2) CPU suspend path to ensure that on resume the values which were saved are restored appropriately. stage_entry.S provides a common path for both normal and resume boot to initialize saved registers. For resume path, it is important to set the secondary entry point for startup since x26 needs to be 1 for enabling MMU and cache. This also ensures that we do not fall into false memory cache errors which caused CPU to fail during normal / resume boot. Thus, we can get rid of the stack cache invalidate for secondary CPUs. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu without mmu_enable and stack cache invalidate for CPU1. Change-Id: Ia4ca0e7d35c0738dbbaa926cce4268143c6f9de3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f5e78469313ddd144ad7cf5abc3e07cb712183a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I527a95779cf3fed37392b6605b096f54f8286d64 Original-Reviewed-on: https://chromium-review.googlesource.com/231561 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add macro to invalidate stage 1 TLB entries at current ELFurquan Shaikh
BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles successfully for ryu. Change-Id: Ia4941a864dd3394689121a8c9ddfaaf6f5c150a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1e43a081f7394b2014d89e723f816f1eca83ef49 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I60d77456573a2a1e854d9f3ca730237acfb77728 Original-Reviewed-on: https://chromium-review.googlesource.com/231698 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9539 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add conditional read/write from/to EL3 assembly macros.Furquan Shaikh
Some registers are available only at EL3. Add conditional read/write functions that perform operations only if currently we are in EL3. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: Ic95838d10e18f58867b6b77aee937bdacae50597 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 62a0e324a00248dba92cb3e2ac2f4072d0e4e2a7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Ia170d94adb9ecc141ff86e4a3041ddbf9045bc89 Original-Reviewed-on: https://chromium-review.googlesource.com/231549 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9538 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add function for reading TCR register at current ELFurquan Shaikh
TCR at EL1 is 64-bit whereas at EL2 and EL3 it is 32-bit. Thus, use 64-bit variables to read / write TCR at current EL. raw_read_tcr_elx will handle it automatically by accepting / returning 32-bit / 64-bit values. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I96312e62a67f482f4233c524ea4e22cbbb60941a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae71f87143f899383d8311a4ef908908116340d7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I459914808b69318157113504a3ee7cf6c5f4d8d1 Original-Reviewed-on: https://chromium-review.googlesource.com/231548 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9537 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Make non-vboot2 memlayout more usefulFurquan Shaikh
Update non-vboot2 memlayout: 1) Add timestamp region 2) Increase ramstage size 3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot upstream board can also use this layout. BUG=None BRANCH=None TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of vboot2. Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f Original-Reviewed-on: https://chromium-review.googlesource.com/231547 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9536 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Change memlayout to have PRERAM and POSTRAM CBFS CacheFurquan Shaikh
Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split them into PRERAM and POSTRAM CBFS_CACHE. BUG=None BRANCH=None TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu. Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf Original-Reviewed-on: https://chromium-review.googlesource.com/231546 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9535 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Bump up ramstage to 256KFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Ia4875948e0be5e084f54f1acb1c5acf5cdabad94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038e9abe2c6e1813cad50bb768e1f66cdd056ccd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: If5df6e0dbf85c837f9ada6a967fd3d01b5230307 Original-Reviewed-on: https://chromium-review.googlesource.com/232002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9533 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add speaker amp config for AD4567 on P0/P1Tom Warren
A couple of regs need to be poked to allow audio output from this part on Ryu P0/P1. It will be replaced by two non-configurable amps on P3. BUG=none BRANCH=none TEST=Build/flashed on Ryu P1, dumped AD4567 (I2C6 dev 0x34) regs and confirmed settings. Change-Id: Ie602b056fb1488546ab233f8f81cfacb96624ebb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75dabe378b561e939381e2ef5113a2b28bfcedf8 Original-Change-Id: I8999843646927dbd07a179ede973ba5f1eb97167 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: prepare cpu startup in psciAaron Durbin
In order to start CPUs while in secmon/psci one needs to set up the proper SoC state. Therefore, refactor the current CPU startup API to allow for this by adding cpu_prepare_startup() and start_cpu_silent(). BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and booted kernel. Change-Id: I1424500f6c9398f7d44350949c25bb3d4832cec7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f9cf67085b345b529b41dd6554e37d38a5b350 Original-Change-Id: I842a391d3e27ddbfcdef1a2d60e3c66e60f99c77 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231936 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9531 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: psci: actually inform SoC layer of CPU_ON entryAaron Durbin
psci_soc_init() was added to allow SoC PSCI initialization. However, actually calling said function was omitted accidentally. BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and noted correct on entry point was used. Change-Id: I84a397e2dabf149fe8f252ef69d0a7362fa1f194 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a0e6ad41f049bbab483423231db59390894e9b2 Original-Change-Id: I1a4e25fde64ecdc98fa9231f7d9cafc21119630d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231935 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSIJimmy Zhang
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested the default delay of 500us when calling function pmic_write_reg(), it is safe to remove this 100ms delay. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I2cfda38728db223c26f9122b70d37e828921459a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 271b7e95f66f4b8611a0d408e59f428c315074f3 Original-Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331 Original-Reviewed-on: https://chromium-review.googlesource.com/231170 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase size of bootblock due to overflowTom Warren
The bootblock on Rush had bumped up into the verstage allocation, causing the build to break. Reduced verstage from 60K to 58K and increased bootblock from 20K to 22K. Rush and Ryu both build fine now. BUG=none BRANCH=none TEST=Built both Rush and Ryu OK. Verifed verstage size using cbfstool and it's around 55K, so plenty of room. Change-Id: Iaa3a5838c5235ec78c740a977bc032d8b5e270ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 928a4d2d1efabe1e1d6a7fadc22ee0ac4269190e Original-Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/230824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: ensure secondary CPU's stack tops are not in the cacheAaron Durbin
Secondary CPUs were intermittently not coming online as expected. Upon investigation it was found that a cache line needed to be invalidated that corresponded to the top of the stack for the failing CPU. Currently the secondary CPUs come online with caching disabled. However, the code paths are using C and thus the stack it is assigned. The MMU is enabled in C after it's pushed its return path onto the stack that went directly to ram. When the cache line corresponding to its stack is valid in the cache it will hit once the MMU is enabled. That hit will have invalid data w.r.t. the return addresses pushed directly into ram. This is not the best solution as the only way to guarantee we don't hit such a situation is to tightly manage resource usage up until the point of MMU enablement. That can be done in a followup patch. BUG=chrome-os-partner:33962 BRANCH=None TEST=On ryu where secondary CPUs weren't coming online consistently, they now come up. Change-Id: I03237656da180d1f74df3a8e00029ba8d778bca8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06ab6afc996cf92c45d4cd6850e31167c2946a95 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: I32de749ea48c19e23442e6dc5678c5369ac3b2b6 Original-Reviewed-on: https://chromium-review.googlesource.com/231219 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9527 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: add timeout waiting for CPUs to come onlineAaron Durbin
The initial MP code assumed all CPUs would come online. That's not very defensive, and it is a bad assumption. Provide a timeout mechanism for bring CPUs online. BUG=chrome-os-partner:33962 BRANCH=None TEST=Multiple times with CPUs working and not working. Boot to kernel. Change-Id: Ib0aef31f5c732816d65c2e4b3c6a89e159974fdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9cf5bc2844c8f4ad987cfcb69ef33c73551f0083 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: Ifb3b72e3f122b79e9def554c037c9b3d6049a151 Original-Reviewed-on: https://chromium-review.googlesource.com/231070 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: always bring up PLLDAaron Durbin
The kernel does not correctly function without PLLD being enabled. Additionally, PLLD can be the source for other clocks in the system. Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT time in ramstage. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted ryu with display coming up both in dev mode as well as normal mode. Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740 Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230774 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: rename clock_display() to clock_configure_plld()Aaron Durbin
Provide an explicit name for configuring PLLD. The new name, clock_configure_plld(), provides an explicit semantic to what it is doing. Also, provide the printk() about actual frequency vs requested frequency as most of the callers were doing this themselves. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted on ryu. Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48 Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.Tom Warren
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz) for MCLK1, I2S1 for input. AHUB needs all of its child peripherals taken out of reset and enabled, too. This just sets up the audio clocks. More work still to be done in the codec driver, and some kind of stub needs to be created/hacked to set up the AD4567 speaker amp regs for mono output on P1. BUG=chrome-os-partner:32582 BRANCH=none TEST=Dumped clock regs and saw correct values Change-Id: Ifb6551f1e09b38f440f3bb7c759b5e6c0b9e4e44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 48f989a0291044f5fb4340cc89546325d819d82f Original-Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229993 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9523 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Set dc to resize the difference between framebuffer and panelJimmy Zhang
Scale framebuffer resolution to panel resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Idb19f5871605e878ea380cc8f701a377350681fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2f08a704fe3a7be1e0448e4ed864c69b50d6838 Original-Change-Id: I5ac01539da3712cd6afdb8d08513da399ace0f92 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229494 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add framebuffer resolution settingsJimmy Zhang
When displaying a 800x600 bitmap on 2560x1800 panel, the image is shown very small. So, set the fb to 1280x800 (based on tegra dsi driver default mode setting), a 800x600 image can be shown relatively proportional to panel size. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I1e360aeaec97b9df5d86e46951ab1326610260d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c2a381322721a24b1b7f9ac366073b7e3c490c Original-Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa Original-Reviewed-on: https://chromium-review.googlesource.com/229912 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9521 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add framebuffer parametersJimmy Zhang
Framebuffer line size and number of lines can have different values than panel's resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229915 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9520 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Expand ramstage size to 208k (from 192k)Jimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Ief81194381193ef9acc7c1786915945d66f2efdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 826ce3730f6d26c9f7a8c3f0429ab14a213172e8 Original-Change-Id: Icc62c776db6f8d8b27615c467518e9753627e72c Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229914 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9518 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add dsi driverJimmy Zhang
Add dsi and related dc, panel configuration functions. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I8440b6dfccc7ed7cd280a0df3a98cbc7b7d66070 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb08563f67daf9a616b60609c4523b823d34f8e3 Original-Change-Id: I87b8047e23ebe114af353fcce5924a46621d16d2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227202 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add dsi panel mode settingsJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624 Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229911 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add panel mode specJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I23dae7bfdeb8e33a6ea5c9de0fb953a7c4d31345 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6cac26deeea0e024f2f6bd1850a41894f801bc5f Original-Change-Id: Ie77f8df4ba3425e0dd4e4243dd38157480de0efb Original-Reviewed-on: https://chromium-review.googlesource.com/229913 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9515 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: dsi: Enable panel related vdd and clocksJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Ia10bf7ae3bde389e883970f9a6ee931c32b8172b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f26902364b6a453adb850abfb0c4ce9686e99b5d Original-Change-Id: I68b92608098959cca14324bfc7e1e58389205989 Original-Reviewed-on: https://chromium-review.googlesource.com/226905 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9514 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Disable EC SW sync for proto boards before proto3Furquan Shaikh
BUG=chrome-os-partner:33583 BRANCH=None TEST=No EC SW sync messages seen in depthcharge boot flow. Change-Id: I62b7061a833ba607457a580fb2b217b9c2df0e74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 552b1d19bacd6692ffb6257fc81220ba0ed89344 Original-Change-Id: I5c1df5a23977f461011a2937adda5770b4742378 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229081 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase space for romstage in memlayoutFurquan Shaikh
Stack and Timestamp need lesser than 2K and since romstage is running out of memory, adjust the overall memory assignment. BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I5076252ae87268bd4e964c282d1cc337e0ea4e70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2d5d29e6f0f5058a41ed30aae98f79574e31609 Original-Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9512 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10urara: support building with CHROMEOS enabledVadim Bendebury
Chrome OS support needs to be enabled on urara. This patch adds a placeholder file to keep Chrome OS support code. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I0731469934f04bd68914f09db5d64758c5d01545 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 169c62c9443c3b9fcab23b312b5cb18ba79437f4 Original-Change-Id: I8ec328d4f965ff80d17847f2f8ce62b402c42a46 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226179 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen
According to BYT platform design guide chap 14.2.2, the NC GPIOs need to be configured to GPO. BRANCH=none BUG=none TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591 Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/249060 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9509 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Log EC panics to eventlogShawn Nematbakhsh
Log the new EC panic host event. BUG=chrome-os-partner:36985 TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in previous boot" is seen in /var/log/eventlog. BRANCH=Samus Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7 Original-Reviewed-on: https://chromium-review.googlesource.com/252391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: http://review.coreboot.org/9508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10cros_ec: Retry failed VBNV transactionsJulius Werner
This patch adds a few retries to NVRAM read/write transactions with the EC. Failing to read the NVRAM is not fatal to the boot, but it's still pretty bad... especially since a single initial read failure will cause vboot to blindly reinitialize the whole NVRAM with zeroes, destroying important configuration bits like dev_boot_usb. The current EC transaction timeout is one second, so the three retries added here can potentially increase boot time by three seconds per transaction... but this shouldn't happen in any normal case anyway, and if there are errors a little extra wait is probably preferrable to nuking your NVRAM. (Also, added a missing newline to an error message in the EC code.) BRANCH=veyron BUG=chrome-os-partner:36924 TEST=Booted a Jerry with the power button bug with a 2 second press, noticed that the first two transactions failed but the third one succeeded. Change-Id: I5d1cf29ac1c555ea2336ebb0b0e0a3f7cbb9c3fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 894a8a0b4a9805e92544b5e3dfa90baf6d36649a Original-Change-Id: I6267cdda2be2bad34541b687404c2434d3be345b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251694 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Enable vr_slow_rampShawn Nematbakhsh
Enable slow ramp rate to reduce idle noise / crackle. BUG=None TEST=Performance/noise/power tested by others. BRANCH=Samus Change-Id: I3b0083bdb19f96fc018356bd744fdff3baaf8962 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 041fca21b863d3fd94dd5bebf89fe48f5ac74285 Original-Change-Id: Id7e55f3710304369a79150129db18300ae38f93a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248791 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10x86: Support reset routines in bootblockLee Leahy
Expand the boot block include file to allow for a file containing reset routines to be added. Prevent breaking existing platforms by using a Kconfig value to specify the path to this file, and have the code include this file only if the Kconfig value is set. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I604f701057d7018f2ed9c3ba49a643c4bca13f00 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c109481d9503916e19ed300c1a3f085e0d2b5c51 Original-Change-Id: I3214399f8156b5ea2ef709ce77e3915cea1523a3 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9504 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
Looks like Intel has added two more USB 2.0 ports from LynxPoint to Broadwell, which shifted the port offsets of the USB 3.0 ports behind them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to 0x560 (at least according to what my kernel seems to think). The offset of the first USB 3.0 port is hardcoded and seems to have been copied over without accounting for this, meaning when we try to operate on all USB 3.0 ports we actually operate on the last two 2.0 and the first two 3.0 ports instead. This patch should fix the bug for now. In the future, we might want to consider dynamically detecting port locations through the Protocol Capability structures at the end of the XHCI register set instead. BRANCH=samus BUG=chrome-os-partner:35320 TEST=TODO Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397 Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247351 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-on: http://review.coreboot.org/9502 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
This changes the PCIe replay timeout value in the root ports to be 0xD to fix correctable AER replay timer timeout errors. BUG=chrome-os-partner:31551 BRANCH=broadwell TEST=build and boot on samus Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28 Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245359 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9501 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Use codec internal 1.8V as DACREF sourceBen Zhang
This is needed for audio playback after we disconnect PP1800_CODEC from DACREF to avoid noise coupled on PP1800_CODEC, which makes recording noisy. For recording, DACREF comes from mic vref pump voltage. For playback, DACREF comes from internal 1.8V. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241179 Reviewed-on: http://review.coreboot.org/9500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set MICBIAS1 to 2.970VBen Zhang
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does not match what's specified on the schematic. This patch sets the voltage to 2.970V (3.3V * 0.90) according to the schematic. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus and verified with a scope Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241178 Reviewed-on: http://review.coreboot.org/9499 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: add code for supporting 2x ddr refresh rateKane Chen
this code change provides a way to enable 2x refresh rate in RW image In baytrail, it enables 2x refresh rate by default BUG=chrome-os-partner:35210 BRANCH=none TEST=check the register is set properly on rambi Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c740d403708862514be9fa24f56b2764328979eb Original-Change-Id: I84f33d75ea7ebfea180b304e8ff683884f0dbe8a Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9498 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie
Add some configuration options that allow tuning the VR for C-state settings that may be able to reduce noise. - Add option to enable slow VR ramp rate for C-state exit - Add variable to configure the minimum C6/C7 voltage BUG=chrome-os-partner:34771 BRANCH=broadwell TEST=build and boot on samus Change-Id: I01445d62fbfcf200b787b924d8d72685819a4715 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ed8f355e60292c82791817ae31bff58ac2390a72 Original-Change-Id: I8af75b69c8b55d3e210170ee96f8e22c2fd76374 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9497 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Adjust SATA Gen3 TX voltage amplitudeDuncan Laurie
Reduce the SATA Gen3 TX voltage amplitude by 210mV based on the provided test results to help with SATA validation. BUG=chrome-os-partner:34121 BRANCH=samus TEST=build and boot on samus and ensure SATA is still working, firmware image will be provided for full validation. Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241800 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9496 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Preserve VbNv around cmos_initDuncan Laurie
To ensure that boot flags (legacy, usb, signed-only) are properly restored from CMOS and used in the first boot after a battery removal or RTC reset then the VbNv region needs to be preserved around the cmos_init call. When using vboot firmware selection and VbNv is stored in CMOS then that region of CMOS will have been re-initialized by the time we call cmos_init and reset CMOS if the chipset flag was set indicating a problem. BUG=chrome-os-partner:35240 BRANCH=broadwell TEST=manual testing on samus: 1) boot in dev mode, enable dev_boot_legacy and ensure it works 2) on EC console pulse PCH_RTCRST_L low for a second 3) ensure first boot after RTC reset will still boot legacy mode 4) remove battery for a time 5) ensure first boot after battery is re-inserted will still boot legacy mode Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241529 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie
This function will use the next available/free protected range register to cover the specified region of flash and write protect it until the next reset. This will be used by the common MRC cache code to protect the RW_MRC_CACHE region after it is updated. In order to communicate to the common NVM code that this function is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241129 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9493 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 11:52:36 +0000