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Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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The limitation for SD-Card was originally only made for mc_apl2
mainboard. Since other mc_apl mainboards also use the SD-Card interface,
the speed mode setting is made in the parent mainboard_final.
In additional, all UHS-I bus speed modes are disabled because of a
limitation for industry use cases. This means that only HS mode is
permitted.
Change-Id: I2f1b51f13a53c2507c52d6a169d6384b8570b3bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch makes VGPIO_3 GPIO PIN output and low independent of
cnvi is connected or not.
BUG=b:123062346
BRANCH=None
TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low.
Change-Id: I629b99676f56747de1b244724709e14069250097
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Taken from
"Intel 6 Series Chipset and Intel C200 Series Chipset"
Document Number: 324645-006 and
"Intel 5 Series Chipset and Intel 3400 Series Chipset"
Document Number: 322169-004 and
"Intel 6 Series Chipset"
Document Number: 324645-001.
UPDCR was found in GNU/Linux's drivers/pci/quirks.c.
DMC2 was guessed as it's close to DMC and defined for 5 series chipset.
Test:
Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences.
Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This CL allows that everyone can use main() in lib/bootblock.c
even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main
functions used in some soc/ to avoid the collision with the
main function defined at lib/bootblock.c.
Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GCFC (Graphics Clock Frequency Control) read is not used at
the line below.
As the default value is zero, let's remove unused read.
Found-by: scan-build 7.0.1-8
Change-Id: I82c567e3a5b0c0c4a8596ea0cb7693667c71b720
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch fixes inconsistent issue with stage cache enabling with
HAVE_ACPI_RESUME config enable. Only enable stage cache if
CONFIG_HAVE_ACPI_RESUME=y
Change-Id: I7c3b3ec4642a615e17fb3dbdedca6af8ca95ea2b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The code currently checks that 4 <= dev_index <= 10, which after
subtraction by 4 can index into an array of length at most 7. This is
fine for the largest cpl array (which does have length 7), but is
too large for some of the others, which are smaller. This adds bounds
checks for each array access to ensure they are all within bounds.
Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229676
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Only needed in ramstage, and only for MP tables.
Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Makefile.inc allows extending site-specific configurations.
This change is to allow make utility to list supported options,
irrespective of a .config file availability.
Change-Id: I7c968c773c368ea74689b9741c4c978c35110187
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The speed argument should be one of the six values from the mem_clock
enum, so something is very wrong if this is not the case. Better to
die now than return 0, which will cause a division-by-zero error
later on where this function is called. The first two speeds are also
unsupported and have the same problem with returning 0, so die on those
as well.
Change-Id: Ib628c0eed3d6571bdde1df27ae213ca0691ec256
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1391088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33409
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the decoded SPD DRAM frequency is slower than the controller minimum,
then there will be an unsigned integer underflow in the following loop,
which will lead to a very large out of bounds array access. Ensure this
does not happen.
Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Judging from the state machine on page 281 of the Rockchip RK3288
Technical Reference Manual (Rev 1.0 - Jun 2015), the fall through
from the INIT_MEM -> CONF states is intentional, since that is the
only way to get to the ACCESS state. Add a comment to explain this.
Change-Id: I1d0cfea07211c54d6a906f5a7481c2c760f8ef0d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1291959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify
the Makefile.inc based on this config parameter.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix regression with commit
903b40a soc/intel: Replace uses of dev_find_slot()
Platforms where FSP hides PCI devices before enumeration
may halt with error message 'PCI: dev is NULL!'.
The workaround here is to print an error message revealing
the faulty source code function and revert to old behaviour
of dev_find_slot().
Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move the SMM lock outside the function as it is renamed.
Replace conditional !PARALLEL_MP with SMM_ASEG to better
reflect the use.
Change-Id: I93bf0d2f711f94a5bb741bdcd92c1e0fec228684
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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With PARALLEL_MP the lock has been moved elsewhere.
Change-Id: I2db78fe99aa1d46c5e7bcef99a37619301c98914
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The code should probably set SCI routing if built
with HAVE_SMI_HANDLER=n.
Change-Id: I0ada4b2a16490a15d8036a9425c4f768f7b8f218
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Currently, bluetooth FW is not loaded after a reboot. In order to do
this, we have to disable the bluetooth disable gpio (GPP_C14) in
bootblock and re-enable it in ramstage.
BUG=b:137307516
BRANCH=None
TEST=boot up Hatch device and make sure (in dmesg) that proper
bluetooth FW in loaded
Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Allow variants to customize their own smi sleep flow.
BUG=b:137033609
BRANCH=octopus
TEST=built
Change-Id: I75db544d333a640848da9072878687c802c1c1a4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34340
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow variants to override GPIO configurations of baseboard in the
bootblock stage.
BUG=b:137033609
BRANCH=octopus
TEST=built
Change-Id: I18d380cdf58f0f24e1bb1bff394ed8a91188a22c
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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These configuration files can be used to build Kodama firmware.
BUG=b:135490566
TEST=check variant: kodama via make menuconfig; make -j
Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are two hard things in computer science: cache invalidation,
naming things, and off-by-one errors. -- Anonymous
var_num records the number of initialized entries in the reg_var array.
However, this means the index of the last initialized element is one
less than the value of var_num, so we need to take that into account
when indexing into the array. This has already been fixed in several
other places (eg. sb/amd/pi/hudson/lpc.c), so let's also do so here.
Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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512 bytes is much too big for this buffer, which only needs to hold a
path that will have a length of at most 20. The large buffer size also
triggers a -Wformat-truncation warning with GCC since it is later
printed into the smaller temp_string array, so shrink it down to
something reasonable.
Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The FSP_CAR option has additional configuration options whose default
values result in boot failures. Since default values should always boot,
default to the open-source CAR NEM Enhanced implementation instead. This
also allows us to get rid of an unnecessary vendor-specific special case.
Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make the title for lesson 1 match the format used for lesson 2 and the
lessons index, for consistency purposes.
Change-Id: I133d758ddf4974096cbf9f10ae96c148fc859efc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Set the controller state to D0 during the i2c init sequence, this ensures
the controller is up and active.
BUG=b:135941367
TEST=Verify no timeouts seen during I2C controller enumeration sequence
Change-Id: I247ede44b8d1d6871e3e813b63f99a7f6398dd72
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add function to set the power state of a LPSS controller.
The API implemented can be used to enforce controllers in
active state(D0) during initialization.
BUG=b:135941367
Change-Id: I7540924885350de64caff91d920d6cc234154616
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Elan's touchpad requires min 0.3us data hold time.
To fine tune the data hold time of i2c1 to meet
specification of Elan's touchpad.
BUG=None
BRANCH=None
TEST=Verified data hold time of i2c1 is around 320ns
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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For AMD's Family17h processors, verstage needs to be run in the PSP,
before memory is initialized. This adds that binary into the PSP
directory.
See the Family17h documentation in the coreboot documentation directory
for more information.
BUG=b:137338769
TEST=Build, add test binary to mandolin board, boot
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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- Correct command line argument for microcode patches from -u to -O
- Add #if PSP_COMBO around new_combo_dir() as it's only called when
that's enabled.
- Remove unused variable in integrate_bios_firmwares()
- Correct enum type from amd_fw_type to amd_bios_type in
register_fw_addr()
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I7a361187570716df94a3fd441ae78c0f805b1dda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33921
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As Intel doesn't even document known bugs add a list of
FSP bugs here.
Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia3ec5fbdbbf2712fe314909e05aab1b135534630
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: I8a5bf39203a5de38d03d1b54453b056ea846ca38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34259
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Not implemented for TSEG.
Change-Id: I279c546a921c0504cafaddcda855bd6ea3de7f8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Don't include unneeded 'vendorcode/google/chromeos/chromeos.h', when
only 'vboot/misc.h' is used.
Change-Id: I99484c29e5a3e13f1fea277f13c2f08a8a46bd88
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
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Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch sets required FSP UPDs to skip IGD initialziation if
devicetree has disable IGD.
Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ie935f98f84772a53de92f0dd2d13a381f5dbaf89
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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SOR_LINK_SPEED_G5_4 is unsupported, but it is not invalid, so it
suffices to return here instead of printing the next warning message.
Change-Id: Ifca3c52635e9a39af42e6616821d1099c43c237c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1293137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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last_unitid is immediately overwritten in the do loop, so this assignment
is not needed. This a relic from old code that commit 13f1c2af8b made
obsolete, but was never removed.
Change-Id: I2eecddd025f7a64b0a70fc07a61ebb43aba757d6
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The JUnit output from the libpayload builds was getting deleted by the
coreinfo build. Move the libpayload to later in the coreboot-gerrit
job.
Also add messages to stdout indicating the various libpayload configs
that are built and a message indicating when all libpayload builds are
complete.
BUG=b:137380189
TEST=Upload test commit that includes a libpayload compile error and
verify buildbot fails.
Change-Id: I43b55f402216582dcf81be34171437be345572ab
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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USB device id does not get included because of the logical OR operation.
Fix encoding the USB device path.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I79317da6d9c7cd177bd7bbbba1f1ccebe076930a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34245
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mark Intel WiFi driver to depend on PCI and remove the dependency on x86
architecture.
BUG=None
BRANCH=None
TEST=Compile and Boot to ChromeOS.
Change-Id: I762007d53b43bbc78924ee8efe236d6a7ff4dc57
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33959
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add generic WiFi driver to support common device operations across
multiple types of WiFi controller.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables
and wakeup GPE information. Ensure that the SSDT table is same after the
change.
Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix
overridetree.cb to advertise the right IRQ.
Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bluebird needs to use different SAR values than Casta.
Bluebird sku id is 2.
CQ-DEPEND=CL:*1435310
BUG=b:129725065
BRANCH=octopus
TEST=build
Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Remove implementation of 24 MHz clock, available only
on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead
for all boards.
Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I39db73014c0a4456750210c002787abf9bc79fce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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It doesn't make sense to print these values for memory-mapped UARTs.
Change-Id: Ie2d9cf95f0b0fdcf601e74de799b1390c08f2335
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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CB:32870 changed FIT loading code to make an FDT mandatory (because the
platforms that can use FIT images always need an FDT). Remove one
left-over conditional that is now dead code.
Found by Coverity.
Change-Id: Ia7765d45f068ab4bdc720ea7ae87dcc62a4b7d3d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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SMM_TSEG is a qualifier between TSEG and ASEG only, while
HAVE_SMI_HANDLER currently tells if SMM will be installed.
Move rest of the file under same 'if ELOG' block.
Change-Id: I620d3ce5aa9632d862d6480922144f002cf6423b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34195
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function implementations are in local platform
scopes.
Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In our codebase, this is only coupled with intel/e7505.
The PCI registers reference here were for intel/i945.
Also aseg_smm_lock() was previously not called.
Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GRUB 2.04 was released on July 5th, 2019, so update. The only change-log
is the git history. Some coreboot related changes are listed below.
1. coreboot: Changed cbmemc to support updated console format from
coreboot.
2. ahci: Increase time-out from 10 s to 32 s
3. normal/menu: Do not treat error values as key presses
When building from the git repository, `./bootstrap.sh` needs to be run
to set up Gnulib. Ignore the exit code, as older versions might not have
this script.
Change-Id: Iab0b87164ed86f15d3415af935998b59e0d76c45
Signed-off-by: Pablo <42.pablo.ms@gmail.com>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.
This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.
Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There are only minimal differences between the architecture specific
stdint.h implementations, so let's tidy them up and merge them together
into a single file. In particular,
- Use 'unsigned long' for uintptr_t. This was already the case for x86
and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64
used 'unsigned long long'. This change allows using a single integer
type for uintptr_t across all architectures, and brings it into
consistency with the rest of the code base, which generally uses
'unsigned long' for memory addresses anyway. This change required
fixing several assumptions about integer types in the arm code.
- Use _Bool as the boolean type. This is a specialized boolean type that
was introduced in C99, and is preferrable over hacking booleans
using integers. romcc sadly does not support _Bool, so for that we
stick with the old uint8_t.
- Drop the least and fast integer types. They aren't used
anywhere in the code base and are an unnecessary maintenance burden.
Using the standard fixed width types is essentially always better anyway.
- Drop the UINT64_C() macro. It also isn't used anywhere and doesn't
provide anything that a (uint64_t) cast doesn't.
- Implement the rest of the MIN and MAX numerical limits.
- Use static assertions to check that the integer widths are correct.
Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.
Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This fixed function is never used.
Change-Id: Ia004756a0b301278f813067ab0ea580c5ea837d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34225
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I20c4436d414bc6b9a3ff5138d6fd59ead8fd4a47
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In patch e29a6ac16a9f478fc00ce7cb83f3779954e3168d (util/sconfig: Add
commonlib/helpers.h) helpers.h has been added to the include-list.
In headers.h we have a definition for __unused:
On a host system environment where glibc-headers-2.12-1.212 is
installed, a file included by <sys/stat.h> called bits/stat.h have the
following content on line 105 and onwards:
long int __unused[3];
where the mentioned part is part of the structure called struct stat.
If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for
__unused will be defined by the preprocessor to be
'__attribute__((unused))', therefore the above mentioned structure member
will be expanded by the preprocessor to be
'long int __attribute__((unused))[3];', which is not a valid C syntax
and therefore produces a compile error for sconfig tool.
To handle this case we need to make sure commonlib/helpers.h is included
_after_ <sys/stat.h>. As the needed part of stat.h (which is
struct stat) is only used in main.c it is safe to move the include from
sconfig.h directly into main.c while taking care of the order.
Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The call to dev_find_slot() may return PCI devices that
are disabled or unaccessible, as PCI enumeration does
not remove nodes from all_devices linked list.
Use PCI topology search instead.
Change-Id: I00233177e5572ca79002a7d141cda1b94b966330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34083
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These didn't align with the usual naming conventions and contained some
errors beside.
Change-Id: I45033d4cb998a85fc0bec00c54e207226f42de4e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is recommended to never reference PCI busses
using a static number. There is exception with
OPROM execution, where we want to translate the
bus number captured from the actual IO operation
into a matching device node in the devicetree.
Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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CONFIG_RELOCATABLE_RAMSTAGE is something more than ramstage specific
kconfig hence its better to remove HAVE_RAMSTAGE dependency
till stage_cache cleaner implementation lands here.
Change-Id: I3c238d727dc13014e2b77544d05099be95c22bab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I535ff1b16b1fa7c3c8c14b2be7eac32568f16077
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34194
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the AC/DC loadline values for all domains. Using the same
values as in arcada.
BUG=None
BRANCH=None
TEST=Build and Boot hatch EVT
Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPIO46 is wired to a tiny switch on the board labelled "GPU Boost".
Since coreboot could make use of it, add a comment about it on gpio.c.
Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Currently some of the LCM ID voltage gaps are below 100mV. For example, the
voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of
misrecognition from the hardware level, the voltages are adjusted so that all
the voltage gaps are larger than 100mV. The RD2 resistor values are also
updated.
BUG=b:136987483
TEST=emerge-kukui coreboot
Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set input_hertz to 26 MHz.
BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: I7f9c329ae5d610f2516e60f06b2ac96ebbeaa897
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.
By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).
BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None
Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=build & run
Change-Id: I9845c8638e4b905de5d6985dc9f1fddd8b1a8942
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25210
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct ELAN Touch pad IRQ GPIO to GPP_A21
BUG=b:135507215
BRANCH=none
TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3. Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The GPID method returns the PCR Port ID of the given GPIO community.
The CGPM method alters the given GPIO community's PM bits, given in
Arg1.
Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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These constants are needed in some ASL files, even when
__ACPI__ is defined.
Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Include the lpit.asl file in Hatch's DSDT definition.
BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.
Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us. Disable it using FSP UPDs.
BUG=b:130764684
BRANCH=none
TEST=Compiles
Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists.
Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Increases CPU max core count to 16 for coffeelake Refresh-S Platform.
TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output
of cat /proc/cpuinfo shows no of processor=16.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I579ff6ae8227844741406c503d3994408ec2b617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clang Static Analyzer version 8.0.0 detects that the result of
log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the
value of bios_size and window_size are negative. Add negative value
Check for bios_size and window_size after MIN operation.
Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.
BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Commit b19946cc62 (console: Remove support for printing extra bases)
truncated the digits string to only print integers of up to base 16.
However, that string was also used to print the leading 'x' or 'X' for
hexadecimal integers and is now too short. Fix this to prevent an out
of bounds read.
Change-Id: Iab6470cc88f445f074cf7c0b675346b37f3f2375
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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