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Correct ICC_MAX values per SKL-Y EDS spec.
Adapted from chromium commit 1c4e89e8 [Chell: Update ICC_MAX configuration]
Original-Change-Id: Ic660cc6a2d11e995a86a30ddde800d096d93e012
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/593715
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ia31ce432cf979d574d84e9205a287f87de5de057
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
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Change GPP_B21 default to low. This can prevent power leakage
of non-touch sku.
BUG=b:142849034
BRANCH=N/A
TEST=Measure the power of non-touch sku, check GPP_B21 is 0V.
Boot up with touch sku and check touch functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
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Configure enable pin GPP_D9 pull high when active
BUG=b:143046441
TEST=build bios and verify touch screen works fine
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I70f19497a2cb1314a1ab18a3da5fd47e40fb57cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I9714b197ff0d1af834aa29f96b33809396f0b203
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36196
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
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Share the same vbt_blooguard.bin to disalbe DRRS support.
BUG=b:143045247
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is blooglet.
Change-Id: Ia180f265080f801a09f10ce8a8b520c47f218775
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I446cd267dec2b6c0f7742a6834c7ee950528ad5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Idf29275575ca7965a0df98dbc8f2b27ab9c5ec4d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Evaluated using 32-bit arithmetic, then used in a context that
expects an expression of type UINT64. Cast to UINT64 instead.
Change-Id: I4f0aa26e116b47505633897c790ca8e86ea5dc4e
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241847
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Code sets `Status = TRUE` in section of code that can only be
reached if `Status == TRUE`.
Change-Id: Id9a49476d17a5ca141994b0d5dfc5e5c62a00f0e
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241801
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Use uintptr_t instead of uint32_t to fix compilation on x86_64.
Change-Id: I5584f849202c0a833c751a80bdd9a8f86c60169a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36172
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic208ae7ae38565cf97023adba3639fa12b83a21e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Move USB ports from the common devicetree to the variants' overridetree
as they differ at least for X11SSH-TF and X11SSM-F.
Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Rename the freeranges array to better match what they represent, i.e.
ranges that are used by the current running program and CAR region that
is not unallocated.
Skip adding the CAR region if cache-as-RAM is not active.
Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a driver that can properly configure the pads needed to run the
correct audio mode. I2S requires the 48M oscillator enabled
regardless of an external connection.
Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- drop FSP-1.1-only romstage.c and spd.c
TODO:
- testing
Change-Id: I9d312ac959a7dac4b018d5ca1d007b1347bcf1dd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Icc/Loadline automatic detection is supported only for FSP2.0
These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN
[*] H-Platforms, Document Number: 332986-010EN
[*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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I originally put up this document for discussion in 2015
(mailing list: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/FXX4V2OSXAQC4B2VUENSFZEWRPPOVRH2/)
(doc: https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeIc7Vo/edit)
It may be time to revisit the way we define our image layouts now that
there are new fmap schemes for new vboot uses. The approach outlined in
this document may or may not be the right one, but it's something we
have, so let's discuss.
Compared to the doc, this will
* be updated (things changed in the last 3.5 yearws)
* integrate feedback to the doc and on the mailing list back then
Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I57b37ebd3383e73a101511e303ad3beeb9d4ea31
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I18483332324ddfa45bc37a58c169901910e5a0cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Similar to MRC cache on x86 platforms, when a hotkey is pressed during
boot, the calibration data cache saved in the flash will be cleared,
consequently triggering DRAM retraining (full calibration) in the next
boot.
BRANCH=kukui
BUG=b:139099592
TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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SoC DRAM team suggested always running full calibration mode in recovery
mode because it is possible to get unstable memory even if the complex
memory test has been passed.
Since the recovery mode runs from RO and we only have training data
cache for RW, the trained calibration data can't be saved since RO and
RW may be running different firmware.
Also revised few message to make it more clear for what calibration mode
(fast, full, or partial) has been executed.
BRANCH=kukui
BUG=b:139099592
TEST=emerge-kukui coreboot
Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Add ELAN EKTH6915 USI touchsreen support.
BUG=b:139392144
TEST=check touchscreen work, and confirmed power sequence with vendor.
Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c.
Reason for revert: Breaks boot on Whiskey Lake-U boards
Both System76 and Purism have had memory initialization failures
when this patch is applied, with the following error message:
Failed to accommodate FSP reserved memory request!
An extra 4096 bytes needs to be reserved for the FSP on these
systems, and reinstating the PTT reservation does this as
expected. PTT is enabled for the System76 galp3-c in the
ME configuration, which is why the behaviour is different.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
CC: Matt DeVillier <matt.devillier@gmail.com>
CC: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add data.vbt and modify Kconfig appropriately;
allows use of FSP/GOP display init.
VBT extracted from stock ChromeOS firmware.
Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Test: build/boot Librem 13v1, 15v2 with libgfxinit
Change-Id: Ia108314b6ab9a01e898e1a8b0022aa4a0d8788be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36108
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Dead increment spotted out using clang-tools.
Change-Id: I631524b9346647048fe8ea30387553a5b4651f59
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Akemi unused devices declare:
- I2C #1 gpio_keys
- close I2C #3
- close GSPO #1
BUG=b:142800988
TEST=Reboot stress test and suspend stress test, the DUT will be
able to working properly
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Renamed mainboard.h to logo.h as it only contains
logo related items.
BUG=N/A
TEST=tested on fbg1701
Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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An important piece of information contained in the APCB is a copy of
SPD-type data to use for soldered down memory. The amdfwtool has
been updated with the ability to build five APCBs into the PSP's BIOS
Directory Table. Modify Picasso's Kconfig and Makefile.inc to take
advantage of the flexibility, and pass the correct instance ID to
amdfwtool.
Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Increase the number of potential APCB images to 5 by adding to the
amd_bios_table. New instance IDs are from 0 to 4. The backup APCB
block (type 0x68) still supports only instance ID 0.
Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Skip calling vbt_get() if FSP is not supposed to run GOP.
Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when
FSP uses the same stack provided by coreboot. This patch updates it to
129KiB since the default value of DCACHE_BSP_STACK_SIZE must be
the sum of FSP-M stack requirement (128KiB) and CB romstage
stack requirement (~1KiB).
BUG=b:140268415
TEST=Build and boot CML-Hatch.
Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix a handful of errors that slipped through in 2e0f2788
"soc/amd/picasso: Update GPIO configuration".
Change-Id: I5784ab3cd95abc28fdc80a3815d0a52d955cff26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36118
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Let the mainboard decide whether to let coreboot load the verb table.
Change-Id: I8f05ac02f690a43ada470916f5292b83aeaa8a4f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35274
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Picasso's Audio Coprocessor
Change-Id: I3f49a61125f0a25db9f43bf2b27c9c68f21d1594
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36116
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make the driver work with stepping=0.
Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35273
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add files for Picasso's FSP UPD definitions. These are automatically
generated from the FSP build.
Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34575
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Prepare for products that can use any DRAM for TSEG.
Include an ID for data pointed to by an ACPI BERT table. This region's
only requirement is it is marked reserved.
Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36115
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clarify names as I2C2, etc. Use iomap.h defines for base addresses.
Update IRQs.
Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33991
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a function to uart.c to ensure the right IOMux settings are
programmed for the console UART. Update Kconfig to reflect the
new addresses.
Give the user the ability to downclock the UARTs' refclock to
1.8342MHz.
Add the abiltiy to use an APU UART at a legacy I/O address.
Update the AOAC register configuration for the two additional
UARTs.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Picasso's Device ID and default filename.
Only a single Device ID is documented for Picasso so remove the oprom
remapper function.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34422
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Picasso's SATA controller operates only in AHCI mode. Remove the
Kconfig symbols previously used to select between other possibilities.
Change-Id: Iaeb8b4a2540e976d2e7361faf8c6d261e60398fd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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SATA is no longer defined in AOAC so remove its definitions.
Change-Id: Ief0ab6b5f69f2d17c11d8e2ee40941ac56c077f6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary. The most notable changes are:
* Update the index values for the C00/C01 interrupt routing
* FORCE_STPCLK_RETRY is not present
* PCIB is not defined
* FCH MISC Registers 0xfed80e00 numbering has changed
* C-state base moves from PM register to MSR
* Add option to determine the intended MUX settion for LPC vs. eMMC
* Remove the LEGACY_FREE option
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I69dfc4a875006639aa330385680d150331840e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The standard PCI register space for D14F0 is accessible at 0xfed80000.
Add functions for use as helpers.
Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The LPC-ISA bridge supports two ranges for SuperIO control registers.
Add a generic function to allow a mainboard to enable the appropriate
range. Provide #define values that are more descriptive than the
register's field names.
Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change to the appropriate device IDs. Remove the ehci resource
call. Remove overcurrent settings, as this will be passed to
AGESA in later change.
Remove unused USB2 ACPI name assignment.
Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Kconfig options and Makefile command line options to generate
the amdfw.rom image. A new intermediate image is introduced, which
is the initial BIOS image the PSP places into DRAM prior to
releasing the x86 reset. The amd_biospsp.img is a compressed
version of the romstage.elf program pieces.
Additional details of the PSP items are not public information. See
NDA document PID #55758.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ic8a28493c386c0097dbf3478e6d046fdfbf28724
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Fix compiler warning by adding an additional check for the fastpath
memset.
Change-Id: I9a80438995bafe7e436f3fe2180b8c9574eeff23
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is similar to X200s, with U-series CPU, slightly different gpio
setup, no docking support, and no superio chip.
Tested:
- CPU Core 2 Duo U9400
- Slotted DIMM 4GiB*2 from samsung
- Camera
- pci-e slots
- sata and usb2
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
Linux payload (Heads) and Seabios.
TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in
CB:4294 ) for h8-using devices without a dock.
Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36128
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This commit creates a dood variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.
BUG=b:141960652
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Add cbfsoption --ibb to mark files as IBB
* Will be used by "Legacy FIT TXT" boot
Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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* Mark files in CBFS as IBB (Initial BootBlock)
* Will be used to identify the IBB by any TEE
Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance
with doc#332691-003EN and doc#334819-001.
Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FBG-1701 revision 1.3 will use Kingston onboard memory.
Add Kingston SPD file.
When Samsung memory configuration is disabled use
cpld_read_pcb_version() for using correct SPD data.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701 revision 1.3
Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792
Reviewed-by: Wim Vervoorn
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change d3a1a417 "src/superio: Remove unused superio chips" removed
all unused devices except for ones used on mainboards still under
review. The SMSC 1036 was inadvertenly also removed as well. This
device is used in debug cards that may be connected to AMD CRBs.
This patch restores the smsc1036 directory as-is and then corrects
the following lint messages.
* WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
* ERROR: else should follow close brace '}'
* WARNING: braces {} are not necessary for single statement blocks
Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move all code involving the cpld to a single file.
Rename mainboard_read_pcb_version() to cpld_read_pcb_version().
BUG=N/A
TEST=tested on fbg1701 board
Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The change applies the DPTF parameters.
BUG=b:142849037
TEST=build and verified by thermal team
Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The DRAM calibration blob can be compressed using pre-RAM algorithm
(currently LZ4), which will save ~12ms in boot time.
On Kodama, boot time difference:
Before: 1,082,711
After: 1,070,309
BUG=b:139099592,b:117953502
TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed)
BRANCH=kukui
Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Chrome OS firmware images have moved bitmap resources from GBB into CBFS
for a long time, so the GBB should only hold firmware keys and HWID,
that is usually less than 10k.
ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but
many recent x86 simply copy from old settings and may run out of space
when we want to add more resources, for example EC RO software sync.
Note, changing the GBB section (inside RO) implies RO update,
so this change *must not* be cherry-picked back to old firmware
branches if some devices were already shipped.
BRANCH=none
BUG=None
TEST=make # board=darllion,hatch,kahlee,octopus,sarien
Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The two GPIO functions variant_gpio_table() and
variant_early_gpio_table() provide the pointer to the variants GPIO
table for late and early GPIO init. As these functions are variant
dependent the keyword __weak must not be used as otherwise the linker
might choose the tables from the baseboard.
This patch removes the __weak definition making these functions
overriding the general ones in baseboard/gpio.c.
Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36094
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To make data flow more explicit, global variable 'impedance' is replaced
with a local variable, which is passed as a function argument.
BUG=none
BRANCH=kukui
TEST=Krane boots correctly
Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with
multiple frequencies to support DVFS switch.
BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch supports voltage adjustment for each DRAM frequency, which is
neccesary to support DVFS switch.
BUG=b:80501386,b:142358843
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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DRAM DVFS needs to be calibrated with different vddq voltages to get
correct parameters.
A new API is added to allow changing vddq voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vddq voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DRAM DVFS needs to be calibrated with different vdram1 voltages to get
correct parameters.
A new API is added to allow changing vdram1 voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vdram1 voltage with multimeter
Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33186
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most coreboot debug messages are sent to UART and cbmem console, and we
also want to collect DRAM calibration module output, especially for
cbmem console (so we can see the logs after kernel is up).
Instead of sharing whole cbmem/cbtable/cbmemconsole implementations, we
want to simplify that by a simple function pointer so output can be
preserved by do_putchar, which internally sends data to all registered
consoles (usually cbmem console and UART).
BUG=b:139099592
TEST=make; boots properly for full-k, with and without serial console.
BRANCH=kukui
Change-Id: I1cf16711caf3831e99e17b522b86694524425116
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36056
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously if .xcompile was missing, abuild would silently ignore the
error. With https://review.coreboot.org/c/coreboot/+/34241 we now check
the return code so abuild started failing.
We should generate the .xcompile if it doesn't exist. The Makefile will
handle that so we include it as the first Makefile.
We then need to override the default target so we don't use the one from
the Makefile.
BUG=b:112267918
TEST=ran abuild and made sure it generated a .xcompile in the root.
Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add an entry for mb/supermicro/x11-lga1151-series and add myself to the
list of maintainers.
Change-Id: I634d251b4323c4f05edd553a9fa82e0f8c53773b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the
romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol.
Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between
RW_A and recovery, which works quite well as a developer mode to test
RW_A with the COREBOOT slot as a fallback.
Change-Id: I9d524988e991457032f63a947606d1b3581de5e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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During the raminit the CPU gets reset but the platform does not. To
deal with TPM init failure (a TPM can only be started up once) ignore
the invalid POSTINIT return code.
Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36055
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are use cases where TPM has already been set up in a previous
stage, e.g. TXT or when a CPU reset without a platform reset happens.
If this is the case the TPM startup will return a
INVALID_POSTINIT (return code 0x26). This adds a Kconfig to allow
platforms to disregard that return code.
Change-Id: I238b30866f78608c414de877b05a73cf8fdb9bbd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The checksum is stored in the header of calibration data and saved to
SPI flash. After reading the data from flash, checksum is used to verify
the integrity of the calibration parameters.
BUG=b:139099592
BRANCH=kukui
TEST=Calibration data successfully loaded from flash
Change-Id: Ie4a0688ed6e560d4c0c6b316f44e52fd10d71a9d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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In broadcast mode we only need to set registers for channel 0
instead of all channels.
BUG=none
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Some typos are fixed to make DVFS switch work.
BUG=b:142358843
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and
other bit field helpers.
Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch contains some minor changes including:
- Use lowercase hex literals
- Combine short lines
- Remove unnecessary curly braces
- Simplify struct initialization
- Leverage macro _SELPH_DQS_BITS
- Ensure whitespaces around binary operators
- Remove extra whitespaces after commas
- Change log level and remove unnecessary debug logs
BUG=none
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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If DRAM calibration fails or mem test fails using the cached calibration
results stored in flash, rerun DRAM full calibration. If partial
calibration fails or the mem test following it fails, hang forever.
Partial calibration acts as a fallback approach in case of full
calibration failure. Therefore, if it fails, there would be no other
ways to initialize DRAM. Instead of falling into reboot loop and
draining out of battery, it is better to just hang so that the end user
may notice that and send to RMA.
BUG=b:80501386,b:139099592
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35481
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is already done in nb/intel/nehalem/romstage.c.
Change-Id: I2dc34af874ac96af31ca9ebe6a43b2805da32d18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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During the raminit the CPU gets reset, so reprogram those bits in
PM1_CNT such that the CPU remains aware that this is a S3 resume path
after the reset.
Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This decreases the output verbosity of RAM_DEBUG to be useful.
Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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