| Age | Commit message (Collapse) | Author |
|---|
|
We should always have some timeout when we wait for the hardware. This adds
missing timeouts to the EHCI driver.
Change-Id: I13ba532a6daf47510b16b8fdbe572a21f1d8b09c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1077
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
We should always have some timeout when we wait for the hardware. This adds
missing timeouts and a more standard compliant port reset to the OHCI driver.
Change-Id: I2cfcb1039fd12f291e88dcb8b74d41cb5bb2315e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1076
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This removes a synthetic delay of 5ms from every OHCI USB command. A delay
here seems to be of no use and first tests have shown no glitches.
Change-Id: Ie72b2d49e6734345708f04f3f7b86bacc7926108
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1075
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This adds support for usb interrupt transfers in the EHCI driver. Split
transactions are supported, so this enables support for HID keyboards
devices over hubs in high-speed mode.
Change-Id: I9eb08f12b12c67ece10814952cb8651278b02f9d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1083
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The call to destroy_intr_queue was missing in usb_hid_destroy.
Change-Id: I51ccc6a79bc005819317263be24a56c51acd5f55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1082
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
With split transactions, the EHCI host controller can handle full- and
low-speed devices on hubs in high-speed mode. This adds support for split
transactions for control and bulk transfers.
Change-Id: I30fa1ce25757f33b1e6ed34207949c9255f05d49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1081
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This adds proper device attachment and detachment detection and port enable-
ment to the USB hub driver. Support for split transactions is still missing,
so this works only with USB2.0 devices on hubs in USB2.0 mode and USB1.1
devices on hubs in USB1.1 mode.
Change-Id: I80bf03f3117116a60382b87a4f84366370649915
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1080
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
* -c "" need never be tested if getopt params are handled; fail abuild script when getopt parsing fails
* use expr to resolve numeric test fails with -c max
* cpus variable may be being passed in the environment. Don't overwrite MAKEFLAGS if it is not.
Change-Id: I96236ef719a1a9f942b8e15bfcf015d60068e58a
Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
Reviewed-on: http://review.coreboot.org/1068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
This removes a synthetic delay of 10ms from every mass storage command.
A delay here seems to be of no use and first tests have only shown a
huge speed increase.
Change-Id: Ida7423229373ec521d4326c5467a3f518b76149c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1071
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Without GFXUMA beeing set, MTRR initialization runs out of variable MTRRs.
Change-Id: I5d1aa0d5fa2d72f17a0d88cae3fad880b489828c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
This disables some debugging code in the OHCI USB driver which causes
reboots under rare circumstances.
Change-Id: Ic274c162846137ee00638ffbc59ccf1d8130586f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1074
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Due to operator precedence incomming USB commands were missing some
flags.
Change-Id: I87ef51590c9db7a6cbc7304e1ccac29895f8a51e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/1084
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
UHCI commands should have a timeout of 30ms, not 30s!
Change-Id: Iebcf338317164eb1e683e1de850ffab5022ca3a1
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/1085
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Enable power on EHCI root hub ports only if the controller supports it.
Wait 20ms for the power to become stable.
Change-Id: I8897756ed2bfcb88408fe5e9f9e3f8af5dd900ac
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1078
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
This function will be used by the USB hub driver.
Change-Id: I4d1d2e94f4442cbb636ae989e8ffd543181c4357
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
The removal of bitfields came with some glitches in the UHCI driver. This
fixes it.
Change-Id: Iba8ea3b56b03c526eca7b6388c019568e00be6f5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1069
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
It is just me or does anybody have the same build error without
this patch?
------
src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC':
src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv'
specified in initializer
src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around
initializer
src/arch/x86/boot/acpigen.c:347:3:warning: (near initialization
for 'addr.<anonymous>')
-------
Anyway, I believe at least this will cause warnings.
"resv" is a member of a union, not of acpi_addr_t. So it should be
wrapped by a brace in the initializer.
Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
clang complained about a missing include and wrong fprintf use.
Change-Id: Idc023b653e694147c624d5f8f9ed3b797c462e9f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1067
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Without that fix the debugging is harder because the person debugging
coreboot will see the following twice(note the repeated MTRR number):
Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB
[...]
Setting variable MTRR 1, base: 4096MB, range: 512MB, type WB
Setting variable MTRR 1, base: 4608MB, range: 256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
instead of the following twice:
Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB
[...]
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea:
May 25 23:57:17 <kmalkki> I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs()
Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1058
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change adds utility functions which allow to read any GPIO pin,
as well as a vector of GPIO pin values.
As presented, these functions will be available to Sandy Bridge and
Ivy Bridge systems only.
There is no error checking: trying to read GPIO pin number which
exceeds actual number of pins will return zero, trying to read GPIO
which is not actually configured as such will return unpredictable
value.
When reading a GPIO pin vector, the pin numbers are passed in an
array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a
three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass
pointer to array of {4, 2, 15, -1}.
Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1049
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
clang does its own linking, incompatible to our
binutils-centric linker magic.
Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs
and the code can easily be changed to not rely on any Kconfig magic.
Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Right now coreboot compilation fails when SPI flash debugging is
enabled. Fix it by using the right set of memory functions.
Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Experiments have shown that writing plain value of 6 at byte io
address of 0xcf9 causes the systems to reset and reboot reliably.
Change-Id: Ie900e4b4014cded868647372b027918b7ff72578
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Originally, on ChromeBooks, coreboot would provide a modified
u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot
can now create all the information it needs from the coreboot
table and add it to its device tree itself. This means we can
drop this (anyways unused) code.
Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Originally, ChromeBooks would get the offset of the MRC cache
from an entry in the u-boot device tree. Not everyone wants to
use u-boot on Sandybridge systems, however.
Since the new code (based on Kconfig) is now fully working, we
can drop the u-boot device tree remnants.
Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1051
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
The MRC region is described by Kconfig variables, no further math
or parsing is required at this point.
Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Without this option bluetooth configuration value in nvram is not
consulted properly.
It also enables built-in volume control (read-only).
Tested on: ThinkPad X60s, 1702.
Change-Id: I2fc6bb527c6e086a083e63922d1253eda7d4a36d
Signed-off-by: Motiejus Jakštys <desired.mta@gmail.com>
Reviewed-on: http://review.coreboot.org/985
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
|
|
The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t).
Implement this in our printk implementation so we get useful output.
Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1043
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
A while back coreboot was changed to read the subsystem IDs from
devicetree.cb to allow each onboard PCI device to have its own
subsystem id. When we originally branched, this was not the case,
and the sandybridge/ivybridge mainboards have not been updated yet.
Also, drop the subsystem ID from Emerald Lake 2, since it's not a
Google device.
Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1042
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled.
Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1045
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
- use %zu instead of %zd for size_t (%zd is for ssize_t)
- use %x instead of %lx for u32
- break some long lines to avoid commit hook trouble
Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1041
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Stupid typo: APCI instead of ACPI in Persimmon.
Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1054
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
|
|
In printf/printk, using %lld or %ld for uint64_t will warn on either
64bit or 32bit machines. However, C99 defines PRIx64 / PRId64 to
provide the right modifiers for printing uint64_t variables. Use them
instead.
Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1053
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
When compiling coreboot with the latest ChromeOS toolchain, GCC
complains that some printk calls use %zu in connection with size_t
types since it resolves the typedefs to long unsigned int.
The problem is solved by using the GCC built-in __SIZE_TYPE__ if it
exists and define __SIZE_TYPE__ to long unsigned int otherwise.
Change-Id: I449c3d385b5633a05e57204704e981de6e017b86
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1040
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
To avoid having two copies for every firmware descriptor (one for
EM100 use and one for real SPI flash use), add an EM100 mode to
ifdtool that allows to "dumb down" a fast image to the settings
required for the EM100 to work.
Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1039
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The ChromeOS build system provides a set of CXXFLAGS, however those do
not contain -DCOMPACT. This breaks the compilation of cbfstool in
coreboot-utils.
This fix overrides CXXFLAGS so that coreboot-utils compiles again.
Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1038
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Being a diligent soul, I changed the "enter a numeric value for the
mode you want" option to a choice of common modes. New modes can be
added quite easily.
Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/1036
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
It still failed because make touches files it isn't
supposed to touch.
Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1037
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.
Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
In the heap function, only check for S3 check when it is built in
with CONFIG_HAVE_ACPI_RESUME.
Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1034
Tested-by: build bot (Jenkins)
Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The fadt legacy free logic was backwards.
Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1030
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
|
|
The bootblock.ld linkerscript is used by romstage. Name it
accordingly to avoid confusion.
Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1031
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
|
|
Cygwin is case insensitive, so bootblock.s and bootblock.S in the
same directory cause a build failure. This changes bootblock.S
to bootblock_inc.S, as it is generated from bootblock_inc.
crt0.S and crt0.S also had this problem. This changes crt0.S to
crt0.romstage.S.
Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1032
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
|
|
Use the coreboot IASL for building SeaBIOS.
Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1033
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
|
|
lint tests for labels to start at BOL, no spaces before them.
Change-Id: Icf6ce533f26998a81b4be46d17e2d0b6b868904d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Happened way too often that crossgcc failed
because m4 or bison wasn't installed already.
Change-Id: Ibcca2183edd5db20608015e3898f8fff9a6d11e8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1026
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Update GNU project versions, download GNU project tarballs
using ftpmirror.gnu.org (http, picking close servers).
Update ACPICA tarballs, ignore https certificates for all
downloads. Not very useful, but breaks ACPICA download.
Change-Id: I4aa8b08836346d031793a006b20b741d86e48988
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1025
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Raymond Danks <ray.danks@se-eng.com>
|
|
Handling user options was spread out across the code.
Collect as much as possible in the getopt loop.
Change-Id: I4979a14988da000c008e155023b960535b529b41
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1028
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
abuild used to allow boards to override certain environment
variables using a file called abuild.info.
This isn't used, this isn't needed. Drop it.
Change-Id: Ic93748f602bf0c354ff1f3be25a050e1cb469256
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1027
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The FADT iapc_boot_arch indicates the available information
for accessing legacy devices. By default, the setting supports
legacy. LEGACY_FREE and/or the iapc_boot_arch field may be
customized.
Change-Id: I5679741e1f8db923d3c00b57f6a5d813550f3a5e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
|
|
The South Station recieved updates that fix a number of fadt problems.
South Station now uses the southbridge fadt.
Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
|
|
Requirements:
- must be in ramstage (locking flash while executing code from there
might not work)
- must be after cbmem is reinitialized (so the mrc cache copy of the
current run can be found)
Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
- Separate Sandybridge from ChromeOS a bit
The Sandybridge code depends on chromeos features a whole lot.
As a first step, provide a code path to look up the MRC cache
without depending on u-boot.
- Move mrc cache handling to separate file
This enables us to handle the MRC cache from ramstage,
where we can write the flash safely (eg. to update the
cache).
Also teach it to lookup the current MRC cache from CBMEM,
as the original data block isn't available anymore.
After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.
Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
This driver is taken from u-boot and adapted to match
coreboot. It still contains some hacks and is ICH specific
at places.
Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/997
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Determine if xargs -P works. If yes, use that to build multiple
boards in parallel, instead of relying on make -j X, when doing
a full abuild run (instead of single boards).
make -j X isn't able to make use of several cores at various
serialization points in our build process, so this change results
in a >25% speed up for a full abuild run in my tests.
Change-Id: Id484a4211c84a3a24115278e0fbe92345f346596
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/409
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
For legacy free AMD systems, the #define LEGACY_FREE cannot
currently be overridden. This patch allows the platform_cfg.h
to override that. (I know we want to get away from that, but
for now...)
Also allow BIOS_SIZE to be overridden on SB700 cimx based
platforms.
Change-Id: I570115248bcbc686062bfb66acb56208240b847a
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1018
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
MA785GM-US2H was left out of Kconfig. This
allows the option to select the board.
Change-Id: I9efea96c21dcd0754ab51824b410435b0b5300c2
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1022
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
We have a http accessible SeaBIOS mirror at review.coreboot.org.
Use it.
Change-Id: Icce8e4f9ca1fa69966c82423b2b27057f15b30d2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1020
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
The fadt.c is the same across all the platforms using the sb800
cimx southbridge wrapper.
Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1019
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
These are the PMIO & PMIO2 read & write routines from
src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx
tree. Currently most platforms using CIMX are calling WritePMIO()
directly from the src/vendorcode/amd/cimx/sbX00 directories
instead of using a wrapper function.
These functions only do byte reads & writes.
Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/981
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
If serial uart (8250/16x50) takes abnormally long to respond, give
up on logging to serial console and instead let the system boot.
Also reference bit in LSR register with correct name.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to
uart8250mem.c:
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Iaca4f57389c887110e6406d45053935891c96838
Reviewed-on: http://review.coreboot.org/826
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This is the beginning of a tool that transforms the i9x5 code to user
mode code. Consider this a very early stage although it does produce
two programs. Requires spatch 1.0 or greater.
To try it out, assuming you have an up-to-date spatch,
sh transform
make
make broken
Please don't fall to the temptation to auto-magicize this process.
It's primitive for a reason. That said, suggestions welcome of course.
Change-Id: I0188e36637b198b06c17f6d3c714d990e88bd57d
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/1003
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
When bringing in nvramtool as build_opt_tbl replacement,
various platforms where left in the cold that don't
provide direct IO support from userland (or at least not
in a way we support).
Build nvramtool without CMOS support when done as part of
a coreboot build. We don't need to touch CMOS in this case.
Change-Id: Icc88d1d32f10384867a5d44b065f9aa119bb0d50
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/983
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
|
|
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)
Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +
Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This change is taken from Linux. It allows to check for Kconfig
definitions in the preprocessor and source code using the same
idiom.
Long term plan is to remove our Kconfig hack to #define values to 0,
and this helps.
This includes a tiny modification to the macros to fix romcc support.
Change-Id: I0fddbea8c8ca215cf226acf39cb329b0ba0445a5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1005
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
|
|
- Prefix all CBFS output messages with CBFS:
- Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS
enabled, the code will no longer print all the files it walks for
every file lookup.
- Add DEBUG() macro next to LOG() and ERROR() to specify which messages
should only be visible with DEBUG_CBFS printed.
- Actually print a message when the file we're looking for was found. :)
old:
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check pci8086,0106.rom
Check fallback/romstage
Check fallback/coreboot_ram
Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24
Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000
Stage: done loading.
new:
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000
CBFS: stage loaded.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/993
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: I40a4201b468131ba67e48ab68d62ca5413f2e2e8
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Otherwise set_subsystem isn't called for these (as they're not
marked on_mainboard)
Change-Id: I08e781735c59e4aa61009d2afa165d782f5a849e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/998
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The stable lint test "build-dir-handling" ran the build system
in a way that made it download the blobs repository. Since this
is part of the pre-commit hook, this might have kicked in with
users desiring not to have them.
Change-Id: I44a00137352c5966ff7fe2a030673276f6803908
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
In a recent commit the SATA code of Panther Point / Cougar Point was
changed to enable AHCI mode depending on the device tree settings rather
than a hard code hidden in romstage.c. However, Emerald Lake 2 was not
fixed up accordingly.
Change-Id: I6c93f386509361e1ab5565b0e4d0e84f0ba282a2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/995
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: I1ec7a7e54513671331ac12f08d5f59161b72b0fd
Example:
PSS: 1900MHz power 35000 control 0x1300 status 0x1300
PSS: 1600MHz power 28468 control 0x1000 status 0x1000
PSS: 1400MHz power 24291 control 0xe00 status 0xe00
PSS: 1200MHz power 20340 control 0xc00 status 0xc00
PSS: 1000MHz power 16569 control 0xa00 status 0xa00
PSS: 800MHz power 12937 control 0x800 status 0x800
PSS: 1900MHz power 35000 control 0x1300 status 0x1300
PSS: 1600MHz power 28468 control 0x1000 status 0x1000
PSS: 1400MHz power 24291 control 0xe00 status 0xe00
PSS: 1200MHz power 20340 control 0xc00 status 0xc00
PSS: 1000MHz power 16569 control 0xa00 status 0xa00
PSS: 800MHz power 12937 control 0x800 status 0x800
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/994
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one
particular board (AMD Persimmon). Make the creation of that section
depending on Agesa so it does consume space on non-Agesa systems.
Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/992
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/991
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Sandybridge memory initialization produces some amount of training data
that has to be kept around in CBMEM. Add a descriptive name to the CBMEM
pretty printer to prevent it from just printing the hex value.
Change-Id: I587c0bc3dfcf389ba298d445d2594eef73bc69a8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/990
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Another bug in the Intel microcode update code that existed since we switched
to LinuxBIOSv2 in 2004:
The inline assembly code that reads the CPU revision from an MSR after running
cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber
list. C code running after this function could silently access completely wrong
data, which resulted in the wrong date being printed on microcode updates (and
potentially other issues happening until the C code writes to EBX again)
Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/996
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
No part of ChromeOS seems to use the debug header description, so drop
it to make sure it does not get copied around wrongly.
Change-Id: Icb0baedbf6112f11289b2ddd9618a955a424ddf7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/989
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/986
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
If microcode.c is built by romcc, this indicates that we are running
microcode updates in the bootblock (e.g. before enabling cache as ram).
In this case we did not enable any consoles yet, so we don't output
anything.
This patch removes inclusion of the unnecessary console/console.h for
that case, which was breaking with certain configurations.
Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/988
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
This fixes my build when specifying an absolute path to the binary.
Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/987
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
It is important to have the system configuration reported as early as
possible to have a better idea what exact chipset the platform is
running with.
This change adds code to have an early coreboot module report the CPU
and PCH information. CPU info includes the 32 bit feature information
word, the symbolic processor brand string, and information about some
features support, as obtained through CPUID instructions.
The PCH information includes the symbolic device name and PCI device
version.
Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
The current early PM setup that attempts to configure dynamic clock
gating relies on PCIe functions to be enabled that may not be.
Instead of reading port 0 or 4 directly to determine the link width
use the register that refelects the soft strapping options as this
will always be available.
Also add a clear register assignment and break for port 0 in the
switch statement instead of falling through to port 4 as that could
end up setting the slot power limit based on port 4 values instead
of based on port 0.
register 0xE1=0x3f and all other root ports should have 0xE1=0x03.
When port 0 and 4 are disabled they will have 0xE1=0x3C before
being disabled by the pch enable handler.
LUMPY default:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 3 0xe1
0x03
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 1 0xe1
0x03
Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/980
Tested-by: build bot (Jenkins)
|
|
Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices
implement function 0. The Linux Kernel therefore will not enumerate
a PCI device if it does not present a valid config space at function 0.
If a board does not have anything connected to root port 0 and it is
desired to disable the unused ports in order to save power then this
will cause the other downstream PCIe devices to go missing as they
will not be enumerated.
Intel chipsets provide a way to map root port numbers to different PCI
function numbers, thereby avoiding this issue and allowing root port 0
to be turned off.
This change adds a new chip config option 'pcie_port_coalesce' that
will collapse the enabled root ports into a linear map starting at
zero. This option defaults to disabled as it can have a confusing
effect on the system as the declared static devicetree may not match
what is seen at runtime. This option is also forced on if the static
devicetree disables port 0.
When each root port is processed in the early enable stage it looks
for a lower numbered root port that has been disabled and then swaps
the two assigned function numbers.
However the mapping register is write-once so it has to keep track of
the proposed mapping changes until all ports have been processed
before writing out the final map value. At this point it also updates
the function numbers in the static device tree so they are consistent
with the new layout.
There are a few other closely related fixes in this change:
1) There is a power savings opportunity if an entire bank of ports
(0-3 or 4-7) are disabled. This was checking the chipset revision to
look for CougarPoint B1+ stepping and that was not passing on
PantherPoint where this should always be applied. To fix this I added
a function to determine the chipset type based on comparing the upper
byte of the device ID.
2) Apply the same chipset type check fix to the IOBP programming.
3) There is another power savings opportunity to enable dynamic clock
gating on shared PCIe resources which only applies to ports 0 and 4.
However if 0 or 4 is disabled then the later check to enable this
would fail as that device is already hidden.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/979
Tested-by: build bot (Jenkins)
|
|
The chipset enforces static-defined interrupt swizzling on PCIe root
ports so if a port is remapped to a different function it needs to
still report the proper interrupt map to the OS instead of assuming
that function number is equivalent to root port number.
This change also includes an update to the PCH function disable
register which was incorrect for CPT/PPT and would cause unpredictable
behavior if used.
The kernel command line was changed to add 'nomsi' in order to force
PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
that the mapping is correct.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/978
Tested-by: build bot (Jenkins)
|
|
CONFIG_MAX_PHYSICAL_CPUS is defined by quite a number of
mainboards whithout any code actually using the variable.
Hence, drop MAX_PHYSICAL_CPUS from Kconfig for those boards.
In the long run we should drop CONFIG_MAX_PHYSICAL_CPUS use
completely and make the code dynamic or depend on CONFIG_MAX_CPUS
instead.
Change-Id: I37dcc74d245ddba5186b96bd82220dacb6f4d323
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/984
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
The sata controller comes up in legacy/normal mode and
is currently put into AHCI mode in romstage.
If that is removed and the controller is left alone until the
ramstage driver (like we do on Stumpy/Lumpy) then the resource
allocator will have configured the device for IDE mode with an
IO address in BAR5. Then when the ramstage driver puts the
controller into AHCI mode it will not have the correct resources
to do the rest of the AHCI setup.
So the controller mode needs to be changed in the enable stage
rather than in the init phase. This same register contains
the port map and it is a R/WO (write once) field so the configured
port map must be written at the same time. For non-AHCI mode
the devicetree map was ignored before but it is used now.
Since the port map register is now written at enable step it
does not need to be written again during init.
With this change the sata port map can be reduced to just port 0
and then U-boot does not have to probe all available ports.
Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/977
Tested-by: build bot (Jenkins)
|
|
- New table for GT1
- Updates to GT2 17W table
- New table for GT2 35W SKU
- New table for GT2 Other
This also includes a workaround to poll on a different register
when deasserting force wake. On some SKUs the kernel is hanging
when bringing up graphics unless this register is also polled.
Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/974
Tested-by: build bot (Jenkins)
|
|
- Add config options to set backlight registers
- Update powermeter weight tables for IvyBridge GT1 and
add a new table for GT2 SKU
- Fix a few registers used during GPU PM init sequence
Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/973
Tested-by: build bot (Jenkins)
|
|
Port u-boot patch for low-level driver:
- Fix bug in traversal of vendor name list.
- Sending "command ready" needs additional logic to handle
TPMs that need that bit set twice: once to empty the read
FIFOs and once to actualy set command ready.
Change-Id: I57c280266b2e966c5b90e4f9e968426a33b93cf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/972
Tested-by: build bot (Jenkins)
|
|
The OS does not re-execute the APMC 'enable ACPI' SMI
on resume so this has the potential to leave things
in an unknown state.
Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/971
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
This is done inside the SystemAgent binary on Ivybridge.
Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The ASPM setting for the Direct Media Interface should no longer be done on
Ivybridge/PantherPoint based systems.
Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://review.coreboot.org/969
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
This adds the PCI device id of the LPC controller identifying the
QPRJ/QS stepping of the Panther Point southbridge.
Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Many PCI devices share the very same driver despite having different
PCI device IDs, which causes a lot of copy and paste of driver
definitions.
This change introduces a way to specify the array of acceptable
device IDs in a single driver entry. As an example the Intel
{Sandy|Ivy} Bridge SATA driver is being modified to use a single
driver structure for all different SATA controller flavors, a few
more Ivy Bridge IDs are being added as well.
BUG=none
TEST=manual
. modified coreboot brought up an Ivy Bridge platform all the
way to Linux login screen.
Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I4a64a56dda22050a31232807096e15565a665377
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/967
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The Emerald Lake 2 CRB can potentially have more
than 8 CPU cores, so update the number of max cores
accordingly.
Change-Id: Ia42ed8a84916f66dfbfdf2a72cbbed5cea61899b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/966
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't
any actual developer mode, recovery mode, or write protect switches, let alone
GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs
which are for other things but which aren't used by hardware or, for instance,
the EC to do something Coreboot doesn't control.
The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the
schematic. The name is at least very reminiscent of the right thing even if
it's supposed to be used for something else. There's a jumper on the board
labelled J8G1 which can force the line to ground, and if not, there's a switch
on the front of the case which toggles its value. "RECOVER" is for recovery
mode and "KEEP" is for normal mode.
The developer mode switch is connected to GPIO 57 and is called SV_DET on the
schematic. It's connected to a jumper labelled J8E2 on the board and, as far as
I can tell, can't be controlled in any other way. When the jumper is in place
and the pins are shorted, developer mode is selected. When the jumper is
removed, normal mode is selected.
The write protect is connected to GPIO 48 which is called BIOS_RESP on the
schematic. It's connected to a jumper labelled J8E3 which, like j8E2, seems to
be the only way to control the line it's on. When the jumper is in place,
write protect is "disabled", and when it's in place it's "enabled" even though
there's no functional difference.
The input for the recovery mode switch was chosen because of the name it
already had on the CRB, BIOS recovery, and because there's a switch to control
it on the front of the case which makes it easy to get at. The jumpers for
developer mode and recovery mode were chosen because there weren't very many
options available, and of those these were next to each other which should
make them easier to find and work with. It might be a good idea to wire toggle
switches up to the pins of those jumpers so they'll be easy to identify, can
be labelled, and would be easier to work with than little jumpers in the
middle of the motherboard.
Change-Id: Ib2c3dc05077dacfbede596dae143ed81a99dbebd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
