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2020-04-16intel/common/block/lpc: Add new device IDs for Lewisburg PCHBryantOu
Add C621A, C627A and C629A SKU IDs. C621A is used in the Whitley Product. We need to add device ID for setting LPC resources. Refer to Intel C620 series PCH EDS (547817). Change-Id: I19a4024808d5aa72a9e7bd434613b5e7c9284db8 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40395 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16mb/google/hatch/var/kindred: Override VBT selection for kledDavid Wu
Override VBT to fix CRC error issue with psr2 panel for kled. Cq-Depend: chrome-internal:2877637 BUG=b:145963505 BRANCH=hatch TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-04-16MAINTAINERS: Update GA-H61M-S2PVAngel Pons
Commit 991ee05 ("mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-series") renamed the mainboard folder from `ga-h61m-s2pv` to `ga-h61m-series`, but the MAINTAINERS file was not updated accordingly. Correct that. Change-Id: I8119e29912e04ab57bebb96f37a4147afbb4d56e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-16MAINTAINERS: Drop invalid pathsAngel Pons
Remove references to directories that no longer exist. Change-Id: Ief45bf4c00c6cbf9b5acef72a76c05a86a7ebedc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-16autoport: use GMA_STATIC_DISPLAYSIru Cai
Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16autoport: Support bigger ACPI tablesIru Cai
DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB for an ACPI table and support lines in acpidump.log with address higher than 0x10000. Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16SeaBIOS: fix threaded hardware initialization during oprom executionMichał Żygowski
Since SeaBIOS rel-1.7.5 CONFIG_THREAD_OPTIONROMS is not present in its config. The threaded hardware initialization during optionrom execution is now controlled with a CBFS file. Add appropriate integer to CBFS when threaded hardware initialization is selected in coreboot's Kconfig. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9b5a532b609c6addf31ccdb6be03ff2e937ad326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16ec/google/chromeec: add BOARD_VERSION CBI supportAaron Durbin
Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base. Add the binding for it so it can be used. BUG=b:153640981 Change-Id: Ie2f289631f908014432596448e56b5048a196a10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-16mb/google/puff: Add variant specific DPTF parametersTim Chen
Modify DPTF parameters for OEM EVT build from thermal team. BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-15mb/google/hatch: Add Kaisa variantAndrew McRae
A verbatim copy of variants/puff V.2: rebased on duffy. BUG=b:152951180 BRANCH=none TEST=none Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mb/google/hatch: Add Duffy variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15mb/kontron/ktqm77: Extend SATA CMOS option with "legacy" modeNico Huber
TEST=Booted Linux 2.6.12 w/o native Intel IDE driver and confirmed working SATA drive. Change-Id: I85f72a172bcbc4c8b4bfb7a2baed7c6739b2d9f8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15sb/intel/bd82x6x/sata: Clean up IDE modesNico Huber
Don't set legacy timing values that don't affect the hardware but enable the OOB retry mode as already done on the AHCI path. Change-Id: I0b078d7790ca801a89066ef6a161d900be5eb778 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15trogdor: add support for Bubs variantT Michael Turney
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15Do not select USE_BLOBSNico Huber
The `USE_BLOBS` config only exists for idealistic reasons. If we would allow us to use blobs by default, we wouldn't need that option and could just always do it. It's generally debatable for the project as a whole, but not per board/subject. Change-Id: I8591862699aef02e5a4ede32655fc82c44c97555 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-15MAINTAINERS: Fix a commentAngel Pons
A space was missing before the asterisks. Change-Id: I1cb62a9efc8e15c09cdebb49956f0edeb032beb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-15soc/intel/apl/report_platform.c: Fix typoAngel Pons
"Aplollolake" => "Apollolake" Change-Id: I1881d40b5f71d07d5d217b4380241cc14467fb1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40407 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15mb/intel/jasperlake_rvp: Update JSLRVP USB configurationRonak Kanabar
Remove extra USB port entry because it came in from copy patch from the previous board and configure USB over-current pins as per JSLRVP. Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15cpu/x86/acpi: Add assignments to ACPI_Sn enumsMarshall Dawson
Explicitly assign numerical values to the enumerated sleep state values. BUG=b:153854742 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I1de2e7f65a2dc3f8a9a1c5fd83d164871a4a2b96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15sb/intel/bd82x6x/sata: Add legacy mode supportNico Huber
Legacy mode is supposed to help with IDE controller drivers that don't know Intel's "native" IDE interface. We extend the `sata_mode` NVRAM variable to provide the following choices: * 0 "AHCI" - AHCI interface * 1 "Compatible" - Intel's "native" interface * 2 "Legacy" - Legacy interface Change-Id: I0e7a4befa02772f620602fa2a92c3583895d4d1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKUMichał Żygowski
CLKRUN_EN bit available for mobile is reserved on desktop SKUs. PSEUDO_CLKRUN_EN bit available for desktop is reserved for mobile SKUs. Configure these bits accordign to SKU. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5295eb2bec27c77f800cc2ade9093e97ede47789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-04-15soc/amd/picasso: Add common PSP supportMarshall Dawson
Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15soc/amd/common/psp: add Kconfig description to interface versionFelix Held
BUG=b:153677737 Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.cFelix Held
This function is only needed and valid for the 1st generation PSP interface used on stoneyridge. BUG=b:153677737 Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15mb/google/puff: Fix up WLAN_OFF gpio configurationEdward O'Callaghan
BUG=b:152927525 BRANCH=none TEST=builds Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mb/lenovo/x60: Add vboot supportArthur Heymans
It's relatively slow to boot. It takes 1.5s to get to the payload. In timestamps there are entries related to TPM, which are somewhat weird given that the TPM is not enabled on this device (buggy). TESTED: boot X60, with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y you can force the recovery bootpath. Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15mainboard/puff: Tune ALC5682I rise_fall times on i2cEdward O'Callaghan
Tunes the headphone amp i2c with measured signal shape. BUG=b:147192377 BRANCH=none TEST=builds and measured i2c frequency below 400khz Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14trogdor: Add third RAM_CODE pinJulius Werner
We decided to add a third RAM_CODE pin to the Trogdor family for devices after rev1. This patch adds support to read it. Since the newly used pin was previously unconnected (not pulled down) on rev1, this will change the RAM_CODE result for previous versions (and actually make it undetermined until we enable tri-state). But since we're not actually using RAM_CODE for anything yet, and since those are development revisions that will eventually be discontinued, this should be fine. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-14mb/google/nightfury: Update tdp_pl1_override valueSeunghwan Kim
Update tdp_pl1_override value to 15W for CML-U based nightfury platform. BUG=None BRANCH=firmware-hatch-12672.B TEST=Built Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-14soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope typeJohn Zhao
TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT. Fix the scope type to be PCI_SUB. BUG=b:141609884 TEST=Booted to kernel and verified no TBT PCIE root ports scope type mismatch error in kernel log. Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14mb/google/deltaur: Enable Melfas touch screen for DeltanEric Lai
Reference Drallion to add device tree for Melfas touch screen. BUG=b:152924290 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14mb/google/octopus/variants/lick: Disable xHCI compliance modeJulia Tsai
Since the first LFPS timeout causes xHCI to enter compliance mode, the SS hub cannot be enumerated. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:153782196 TEST=Verified usb operation successfully. Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/dedede: Enable ELAN touchscreen for WaddledooDtrain Hsu
Add ELAN EKTH6918 USI touchscreen support. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-14mb/google/dedede: Enable SIS touchscreen for WaddledooDtrain Hsu
Add SiS9813 USI touchscreen support. BUG=b:152936541 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/intel/{jasperlake_rvp, tglrvp}: Remove unused filesSubrata Banik
This patch removes unused "spd_util.c" files from mainboard directory. Change-Id: Ibd011be578fa256afb61796d5ceeea073e852fe9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-14soc/intel/tigerlake: Implement CHIPSET_LOCKDOWNWonkyu Kim
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I63cec8a718285f424914e426d0399ed821588dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/hatch: Use tabs for alignmentPaul Menzel
Change-Id: I38d429245810f64a03253b5076391af843f8d0de Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mb/google/poppy/variants/nami: Use tabs for alignmentPaul Menzel
Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39 Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mb/ocp/tiogapass: Add missing spaces around operatorsPaul Menzel
Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-14Documentation/vboot: Drop deprecated options from exampleArthur Heymans
4K keys are now default. Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14src/Kconfig: enable USE_BLOBS by defaultFelix Held
To provide sane defaults for most of the user base, this patch switches on the USE_BLOBS option by default. Since it only changes the default, this behaviour can still be easily disabled. With this abuild doesn't have to select USE_BLOBS any more, so what abuild tests becomes the coreboot default again. Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mainboard: add Supermicro X9SCL/X9SCMJonathan A. Kollasch
Boots to Linux. Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7 To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants) Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14nb/intel/sandybridge/raminit: Add ECC supportPatrick Rudolph
Add ECC support for native raminit on SandyBridge/IvyBridge. Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14nb/intel/sandybridge/raminit: Add ECC detection supportPatrick Rudolph
Add support for detection ECC capability and forced ECC mode. Print the ECC mode in verbose debugging mode. Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14nb/intel/i945: Add vboot supportArthur Heymans
Change-Id: I749be0044be04b044ff82e96aff8093f4b0d295e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14soc/intel/apollolake: Disable XHCI LFPS power managementMarx Wang
Provide the option to disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=None TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14src/mainboard: Use 'const' to set pnp_devfn_t staticallyElyes HAOUAS
Change-Id: I50ac6914fadc02491df2eccb437eada89fd12b82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14soc/intel/jasperlake: Allow mainboard to override DRAM part numberMarco Chen
In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: I7ba635f5504ba288308d7d7a4935f405f289aa8d Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-14mb/lenovo: Add additional FMAPs on 8MiB devicesMarcello Sylvester Bauer
* Add FMAP for measured boot only, with a single RO partition. * Add FMAP for measured boot only, with a single RO partition but where the ME has been shrunken. Tested on X220 using VBOOT+measured boot: * Used patched IFD and ME, boots into OS Change-Id: I04c1add13198444638c669deec1e05159b1a09c9 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-04-144.12 release notes: Add some explanation behind deprecationsArthur Heymans
Some features are made mandatory, meaning that some platforms have been dropped from master. This also explains that further development on these popular platforms can happen on the 4.11 branch. TODO is this really the right place or is it too technical for release notes? Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-04-14soc/intel/icelake: Add function to dump ME firmware status informationKrishna Prasad Bhat
Add a function to dump ME Host Firmware Status registers. BUG=None BRANCH=None TEST=Build and boot iclrvp. Change-Id: I9430189665c94decb2e64680d28a7390ee6e912c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14soc/intel/tigerlake: Add function to dump ME firmware status informationKrishna Prasad Bhat
Add a function to dump ME Host Firmware Status registers. In tigerlake, Manufacturing mode is “No” if below conditions are satisfied, indicating end of manufacturing. Otherwise, manufacturing mode is "Yes". 1. Intel fuses are programmed (Indicated by HFSTS6[30] bit set) 2. The SPI flash descriptor region is locked. (Indicated by HFSTS1[4] cleared) BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE libKrishna Prasad Bhat
Make use of print_me_fw_version() which is defined in the CSE lib to print ME firmware version information for icl,tgl. BUG=None BRANCH=None TEST=Build and boot iclrvp, tglrvp boards. Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-14mb/intel/tglrvp : Enable RP LTRWonkyu Kim
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/volteer: Enable RP LTR settingWonkyu Kim
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14soc/intel/tigerlake: Configure RP settingWonkyu Kim
Add LTR and AER configuration to the root ports config. BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/volteer: fix incorrect fields in SPDsNick Vaccaro
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16) This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD). BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel. Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-04-14mb/google/volteer: fix CROS_GPIO_WP_AH exportNick Vaccaro
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community zero instead of community 1. BUG=b:152876091 TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to and log into Volteer kernel, execute "wp enable" in H1 console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in H1 console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14mainboard/lenovo: Use the original hardware ids for keyboard/pointingdalao
Currently coreboot is using the compatible ID PNP0303 for all keyboards and PNP0F13 for all pointing devices, which causes some problems. On Windows, the touchpad driver can't be automatically matched and installed through Windows Update. On Linux, there are some strange issues. So it's better to use the original hardware IDs for each model. The hardware IDs for the following models can be found By searching for dmesg logs on vendor BIOS: T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html Keyboard: PNP0303 Pointing: IBM0057 R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg Keyboard: PNP0303 Pointing: IBM0057 X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out Keyboard: PNP0303 Pointing: IBM3780 X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2 Keyboard: LEN0010 Pointing: IBM3780 T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log Keyboard: LEN0010 Pointing: IBM3780 T510: https://bbs.archlinux.org/viewtopic.php?id=120287 Keyboard: PNP0303 Pointing: LEN0015 T410: https://forum.ubuntuusers.de/topic/kein-sound-109/ Keyboard: PNP0303 Pointing: LEN0015 T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T420s: https://bbs.archlinux.org/viewtopic.php?id=191510 Keyboard: PNP0303 Pointing: LEN0015 T520: https://bbs.archlinux.org/viewtopic.php?id=195636 Keyboard: PNP0303 Pointing: LEN0015 W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log Keyboard: PNP0303 Pointing: LEN0015 T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU Keyboard: LEN0071 Pointing: LEN0015 W530: https://bugs.freedesktop.org/attachment.cgi?id=115557 Keyboard: LEN0071 Pointing: LEN0015 L520: https://pastebin.com/U6MaBAY3 Keyboard: PNP0303 Pointing: LEN0017 X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1 Keyboard: PNP0303 Pointing: LEN0018 X220: https://bbs.archlinux.org/viewtopic.php?id=237669 Keyboard: PNP0303 Pointing: LEN0020 X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460 Keyboard: PNP0303 Pointing: LEN0020 X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg Keyboard: MSF0001 Pointing: LEN0026 X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851 Keyboard: LEN0071 Pointing: LEN0030 s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt Keyboard: PTL0001 Pointing: LEN0031 T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg Keyboard: LEN0071 Pointing: LEN0034 X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg Keyboard: LEN0071 Pointing: LEN0035 T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Keyboard: LEN0071 Pointing: LEN0036 T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Keyboard: LEN0071 Pointing: LEN0036 T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976 Keyboard: LEN0071 Pointing: LEN200e Others: https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c Test result: This can make Windows automatically install the Lenovo touchpad driver. It also fixes the T440p touchpad issue. Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932 Signed-off-by: dalao <dalao@tutanota.com> Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/facebook/monolith: Add fmd files for 6MB BIOS areaWim Vervoorn
The current flash layout requires changes to the descriptor area to create the 9MB BIOS region. Add fmd files that allow switching to coreboot by only replacing the BIOS region. BUG=N/A TEST=tested on facebook monolith Change-Id: I2b003018e245693934202505d7e3891c2f545e6c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-14mb/lenovo: Add additional FMAPs for stripped MEPatrick Rudolph
Make it easier to use measured boot with stripped ME by providing the corresponding FMAPs. Change-Id: I1763583a42bbc91e6acc06b262deab10d34447a3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-04-14mb/lenovo/*: Add vboot RO FMAPs on 12MiB devicesMarcello Sylvester Bauer
Tested on W530 Change-Id: I9be0c5e06fcb8287d32171cb72dabb5fcf047e7a Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39450 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14Update vboot submodule pointerDuncan Laurie
Update the pointer for vboot_reference so it can be used to compile depthcharge payload on the master branch. Change-Id: I5fc6e05896d7221a1e48ca86c6b15081488302b5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14lp/drivers/usb: Work around QEMU XHCI register issueDuncan Laurie
The QEMU XHCI controller does not support byte/word reads from the capability register and it expects dword reads only. In order to make this work move the access of the capability register fields to use macros instead of a packed struct bitfield. This issue was filed upstream: https://bugs.launchpad.net/qemu/+bug/1693050 The original fix attempt in 2012 was not effective: https://github.com/qemu/qemu/commit/6ee021d41078844df60a3a466e3829a3e82776f3 With this change the controller is detected properly by the libpayload USB drivers. Change-Id: I048ed14921a4c9c0620c10b315b42476b6e5c512 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13google/chromeec: Add USB MUX InterruptBrandon Breitenstein
Kernel relies on the USB MUX interrupt to configure USB devices that are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt so the Kernel can properly receive and configure USB devices BUG=b:152902608 TEST=buld_packages for volteer and verified that Proto 1 and Proto 2 are now seeing extcon events Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Prashant Malani <pmalani@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13acpi: Bump MADT to revision 3Patrick Rudolph
Add structs and methods for revision 3. Change-Id: Ida75f530551ad2b8b20ce7fdeffb3befc51296bc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13mb/google/deltaur: Add support to enable GbE on variantVarun Joshi
- Configure devicetree for enabling GbE on variant and remove from baseboard. - Configure Kconfig to enable GbE region. - Configure fmd to incorporate GbE. BUG=b:151102809 Cq-Depend: chrome-internal:2843183 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I1c36b132546049e3e775585c41164072f4ece73e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-04-13mb/google/deltaur: Return SKU ID infoAnil Kumar
For Deltaur and Deltan variants return proper SKU ID based on EC firmware type and sensor detect GPIO value BUG=b:152544516 TEST=make build successful for deltan Change-Id: I20a497739e5062400b093648c3a634203dec6105 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-13mb/google/deltaur: Update onboard memory configVarun Joshi
Update dq, dqs map based on deltan schematics. Configure memory to read SPD. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-13include/input-event-codes.h: Add Linux input key codes header fileRajat Jain
Add header file from keycodes from Linux sources. This is needed so that coreboot can provide scancode to keycode mappings in the ACPI that the linux kernel expects (https://lkml.org/lkml/2020/3/24/588) Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I40051cb63a6c154728887ac9b0521bc671b2a518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40029 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licensesRajat Jain
The Linux kernel UAPI header files are licensed under /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ Allows files with this license to be included in coreboot. For more details about this particular license: https://www.kernel.org/doc/html/v4.17/process/license-rules.html https://spdx.org/licenses/Linux-syscall-note.html Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13mb/google/volteer: enable Early Command TrainingSrinidhi N Kaushik
Update memory configuration on Tiger Lake platform to enable Early Command Training. This feature was not supported before FSP v2527. BUG=b:150357377 BRANCH=None TEST= Build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13ec/google/chromeec: add smbios_mainboard_manufacturer()Aaron Durbin
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an implementation of smbios_mainboard_manufacturer() so the code doesn't need to be duplicated in the mainboards. BUG=b:153767369 Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13cpu/x86/smm.h: Add SW SMI for PSP SMM InfoMarshall Dawson
Add a definition for a software SMI to allow AMD systems supporting the MboxBiosCmdSmmInfo command to properly initialize the PSP. BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I1d78aabb75cb76178a3606777d6a11f1e8806d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40294 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13soc/amd/common/psp: Split mailbox support into v1 and v2Marshall Dawson
Family 17h redefines the PSP command and status, and therefore the steps required to send commands via the mailbox. Convert the existing version into a v1 and add a v2. New Kconfig options allow the soc to choose v1 vs. v2. The v2 PSP begins responding to the mailbox command when the full bit range is written. Define the new mailbox as a union of a u32 and a structure. Additional PSP details may be found in the NDA publication (#55758) AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors Change the existing two soc functions that return pointers to void pointers. BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d358fdae07da471640856f57568059e9487f6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13soc/amd/picasso/soc_util: add TODO to Dali detectionFelix Held
Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13mb/intel/jasperlake_rvp: Enable S0ix for JSLRVPRonak Kanabar
Enable S0ix from devicetree for JSLRVP TEST= Build, boot JSLRVP and Verified S0ix is working by running "echo freeze > /sys/power/state" from kernel console. Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-04-13mb/intel/jasperlake_rvp: Enable audioMaulik V Vaghela
Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips connected on I2C0: DA7219 and MAX98373 1. Enable Kconfig to enable I2C drivers for both chips. 2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry for I2C0. 3. Enable audio related GPIO configurations. BUG=None BRANCH=None TEST=Checked that dmic and speaker are functional on Jasper Lake RVP Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13soc/intel/tigerlake: Remove scs.aslAamir Bohra
Remove EMMC and SD card ACPI devices copied from Ice Lake. Tiger Lake does not support these controllers. BUG=b:151208782 TEST= Build volteer board Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11soc/intel/tigerlake: Disable MrcSafeConfigSrinidhi N Kaushik
This change disables MrcSafeConfig option during MRC training. MrcSafeConfig was enabled as part of the early testing. Now with FSP 2527, there is no need to set this config anymore. BUG=b:150357377 BRANCH=master TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 2527. Which includes below additional UPDs: FSPM: - PchTraceHubMode - CpuTraceHubMode - CpuPcieRpEnableMask FSPS: - D3HotEnable - D3ColdEnable - RtcMemoryLock - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchUnlockGpioPads - CpuMpPpi - ThcPort0Assignment - ThcPort1Assignment BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11ec/google/chromeec: expose failure and unprovisioned SKU id valuesAaron Durbin
Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so callers can utilize the default and failing value without open coding it. BUG=b:153642124 Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11mb/google/kukui: correct board nameScott Chao
Modify board name from "Kadadu" to "Kakadu" BUG=b:153590144 TEST=CPU log show "Starting depthcharge on Kakadu..." BRANCH=kukui Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11nb/i945: Improve code formattingElyes HAOUAS
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10src/mb: Remove unneeded spaces before/after tabsElyes HAOUAS
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10mb/lenovo/t420s/devicetree.cb: Fix PCIe port definitionsJake Mannens
The NEC uPD720200A USB 3.0 controller on the T420s is actually connected to PCIe root port #5 on the PCH, not #7. Enable RP#5, disable RP#7 and update comments accordingly. Test=USB 3.0 controller shows in `lspci` Change-Id: I21ac72fd5632e552bdcdbd573cf92b433ed545ff Signed-off-by: Jake Mannens <jakem_5@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10soc/intel/jasperlake: Publish EMMC and SD card ACPI devicesAamir Bohra
BUG=b:150872580 TEST=Build waddledoo board. Verify EMMC and SD card ACPI devices are present in dsdt.asl. Change-Id: I70d47455c48990afe9e79c013c5272d70f4f71e7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-10mb/google/dedede: Add Synaptics Touchpad configuration for waddledeeKarthikeyan Ramasubramanian
TEST=Build and boot the mainboard. Ensure that the touchpad is operational. Change-Id: I937462cd3992a884194bbd1759a0802a147e925a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-10soc/intel/jasperlake: Publish single GPIO ACPI deviceAamir Bohra
Current pin-ctrl kernel v5.4 driver expects the firmware to publish single GPIO ACPI device. Until kernel pin-ctrl driver implementation is updated to consume community based GPIO ACPI device, update the current ACPI code to comply with pin-ctrl driver requirement. BUG=b:150154277 TEST=Verify intel pin-ctrl driver can successfully load in OS Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Ifcc92adaee550182ab405541ea85019f31bb8658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-10mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpioKarthikeyan Ramasubramanian
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up of 20K. Retain it during the GPIO pad configuration. BUG=b:150985246 TEST=Boot the mainboard. Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10drivers/ipmi: Implement the function for logging system events into BMCMorgan Jang
Implemented for functions that need to log system events into BMC, the information of system events can be specific. TEST=Use ipmitool and execute "ipmitool sel list" command to check if SEL is added into BMC. Change-Id: I38f3acb958d12c196d33d34fd5cfa0b784f403b7 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10spi: add Winbond W25Q64JW spi rom supportScott Chao
BUG=b:153515968 TEST=Able to boot to kernel Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Change-Id: I699f6d7ba3af01436f10c9a59af4a22fc45aa300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40270 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10src/ec: Add missing "set_resources = noop_set_resources"Elyes HAOUAS
Change-Id: I4acfb9d9911e251a494b6d35d76226c06e7858d6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10util/nvramtool: Remove 2nd initializationElyes HAOUAS
'result' is already defined as 'unsigned long long result = 0;' so no need to re-write 'result = 0;'. Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10soc/intel/tigerlake: Add support to initialize DDR4 MemoryVarun Joshi
Support to configure DDR4 memory variant. -Add support to read SPD data based on different memory topology. -Initialize FSP UPD's for DQ and DQS mapping. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10mb/*/*/hda_verb.c: Improve code formattingElyes HAOUAS
Change-Id: I294ea867678ad77e454873ecf4948bf2d12c9f80 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10assert.h: Simplify dead_code()Nico Huber
It turns out the linker's error message already includes the line number of the dead_code() invocation. If we don't include the line number in the identifier for our undefined reference, we don't need individual identifiers at all and can work with a single, global declaration. Change-Id: Ib63868ce3114c3f839867a3bfb1b03bdb6facf16 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 20:57:19 +0000