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This change updates the camera power enable GPIOs as per the latest
schematics. With this update, since one of the enable GPIOs is using a
UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that
FSP-S does not re-configure the UART0 GPIOs.
BUG=b:68964831
Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Configure GPP_H12 as an input for PCH_WP_OD.
BUG=b:72202352
BRANCH=none
TEST=none
Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The following two patches were independent, but they were
merged together. However, the first one changed the API
that the second was originally was written against. Fix build.
b94a2750 (i2c/designware: reduce API complication for bus config)
13101a7b (soc/amd/stoneyridge: Add I2C devicetree support)
BUG=b:72121803
Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Make is so that a different timer source can be provided instead
of TSC on x86 platforms.
BUG=b:72378235,b:72170796
Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some x86 platforms don't have a TSC that is invariant w.r.t.
rate to get accurate timestamps. As such a different timestamp
is required. Therefore, allow one to specify non-TSC timestamp
source and not compile in the default x86 TSC code.
BUG=b:72378235,b:72170796
Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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If GENERIC_UDELAY is selected don't try to use UDELAY_IO as there
will be a udelay() conflict at link time.
BUG=b:72378235,b:72170796
Change-Id: I9e01c9daddd0629ecc38a809889b39a505c0e203
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In order to fully utilize GENERIC_UDELAY in smm and postcar
the udelay() implementation needs to be included. Do that.
BUG=b:72378235,b:72170796
Change-Id: Ia20c1ed41ee439bb079e00fb7bd9c1855e31e349
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement
that callback for obtaining the bus config. However, we're currently
forcing another parameter of struct device so one can do the lookup.
This works for Intel-based systems since the struct device was needed
to program the BAR, etc. However, from an API standpoint, it just
complicates matters by needing to obtain the struct device. The SoC
already has knowlege of its own devices so it can get the config
itself by bus number. Therefore, remove that contraint from the API.
BUG=b:70232394
Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23420
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit adds support for an Elan touchscreen device connected over
I2C via devicetree.
BUG=b:72121803
TEST=Confirm the device is probed for.
Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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I2C bus configuration is generally set up in devicetree.cb. This change
establishes listings for the buses so that they can be used (though
followup changes should update the buses to have correct timings).
BUG=b:72121803
Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This is required to add support for I2C devices on Kahlee to ACPI tables
via devicetree.cb. Without this, operations are not emitted for I2C
devices and the proper ACPI table entries are not generated.
BUG=b:72121803
Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.
BUG=b:72121803
Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This commit adds device name to ACPI name bindings for various entries
in the devicetree.
BUG=b:72121803
Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296
comes from the lower four numbers from running:
$ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST'))
BUG=b:72436450
Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add support for a mmio resource in the devicetree to allow
memory-mapped IO addresses to be assigned to given values.
AMD platforms perform a significant amount of configuration through
these MMIO addresses, including I2C bus configuration.
BUG=b:72121803
Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Rename the device ID macros as per the skylake PCH H external design
specification.
Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23381
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change disables SATA controller in order to make SATA IP enter
low power status.
BUG=b:72332817
TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status
and verify SATA IP enters low power state
Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC
and enable eSPI instead.
TEST=Boot to OS
Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This moves the call to pch_enable_lpc() from romstage to bootblock.
In other words, it happens earlier in the boot process. Turns out, we
need this to talk to the EC to determine if we're in recovery mode or
not.
BUG=b:69011806
TEST=boots to linux
Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This adds coreboot device tree entries on zoombini & meowth for the
cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This
is based on what we do for fizz.
BUG=b:71722449
TEST=booted to linux on meowth: tpm_version command now sees the cr50.
localhost ~ # tpm_version
TPM 2.0 Version Info:
Chip Version: 2.0.0.0
Spec Family: 322e3000
Spec Family String: 2.0
Spec Level: 0
Spec Revision: 116
Manufacturer Info: 43524f53
Manufacturer String: CROS
Vendor ID: xCG fTPM
TPM Model: 00000001
Firmware Version: 0ad551830bcf7a82
localhost ~ # uname -a
Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux
localhost ~ #
and we see interrupts when talking to the cr50:
localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru
pts
84: 4687 IO-APIC 84-edge cr50_spi
TPM 2.0 Version Info:
Chip Version: 2.0.0.0
Spec Family: 322e3000
Spec Family String: 2.0
Spec Level: 0
Spec Revision: 116
Manufacturer Info: 43524f53
Manufacturer String: CROS
Vendor ID: xCG fTPM
TPM Model: 00000001
Firmware Version: 0ad551830bcf7a82
84: 4799 IO-APIC 84-edge cr50_spi
localhost ~ #
Change-Id: I9d503334502503ef49515e4a8736d967bc454a98
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=b:71839089
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. powerd_dbus_suspend
3. touch touchpad to wakeup system
4. localhost ~ # cat /var/log/eventlog.txt
| 2018-01-21 17:01:59 | S0ix Enter
| 2018-01-21 17:02:04 | S0ix Exit
| 2018-01-21 17:02:04 | Wake Source | GPIO | 80
Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/23363
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP 2.0 Memory_Info_HOB for KBL is not sending
"MemoryType" value as what is required for SMBIOS Table
according to SMBIOS Spec. Thus, converting the value
retrieved from FSP HOB to the correct value.
This change will not be required for upcoming SOCs since
FSP have fixed this issue in its next platforms and thus it
will take care and send the correct value in "MemoryType"
field based on SMBIOS spec. Thus this conversion from coreboot
will not be required in the next platfoms. "MemoryType" value
can be directly passed to dimm_info_fill() function.
BUG=none
BRANCH=none
TEST=Tested in Soraka, and getting the value as 0x1D for
LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17
will also show correct information. Currently, it was showing
"Unknown".
Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23384
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In payloads/nvramcui/payload.sh line 5:
DIR=`dirname $0`
^-- SC2006: Use $(..) instead of deprecated `..`
^-- SC2086: Double quote to prevent globbing and word \
splitting.
In payloads/nvramcui/payload.sh line 6:
lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1
^-- SC2086: Double quote to prevent globbing and word \
splitting.
^-- SC2086: Double quote to prevent \
globbing and word splitting.
^-- SC2069: The order of \
of the 2>&1 and the \
redirect matters. The \
2>&1 has to be last.
Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The CAR APIs already exist to deal with proper type useage.
Don't open code things that already exist.
BUG=b:65485690
Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Clean up the extra DRIVERS_I2C_GENERIC
BUG=None
TEST=None
Change-Id: Ida32b6f99c40c022aa8548f7353abf1d60ba4ddf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- The em100 project needs msitools.
- Flashrom uses rsync.
Change-Id: Ie01064adede25471a860bc22c0a59b31202b56c2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.
BUG=b:72170796
Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The function read() returns the number of bytes actually read. Program is
assuming it actually read the required number of bytes without checking.
This is wrong.
This fixes CIDs 1353019 and 1353021
BUG=b:72062481
TEST=Build no errors
Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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For the internal eMMC to be used by non-chrome for installation,
the CARD device and _RMV methods are required. Without these,
other OSes does not show the eMMC as a valid installation target.
TEST= boot CNL-RVP with Tiano payload and install Windows 10
to the internal eMMC drive.
Change-Id: Icfdccd88bc113d97c2fabf4c63d8d772737a6057
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Solution: To do an additional config read to the SD controller
after the controller has been power gated (put to D3)
Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Solution: To do an additional config read to the eMMC controller
after the controller has been power gated (put to D3)
Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In ramstage the device_operations are needed for the i2c designware
host controller. Move the intel/common/block/i2c implementation
into the generic driver so other platforms can take advantage of it.
BUG=b:72121803
Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Rename the following functions to ensure it's clear that the designware
i2c host controller driver is the one that these functions are
associated with:
i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg()
i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base()
i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus()
i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn()
BUG=b:72121803
Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23371
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If one wants to implement both i2c_bus.h and i2c_simple.h APIs
the compilation unit needs to be guarded or coordinated carefully
with different compilation units. Instead, name the i2c_bus
functions with _dev such that it indicates that they operate on
struct device. One other change to allow i2c_bus.h to be built in
non-ramstage environments is to ensure DEVTREE_CONST is used for
the dev field in struct bus.
BUG=b:72121803
Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: If5a72786d1119908073488c1d6d8787ac0f4f95c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds AC and DC loadline settings since vr_config_enable is
set. Without correct AD/DC loadline settings, VRs reported incorrect
VID values which caused CPU freqency clipping. The clipping reason
could be retrieved from MSR 0x64F. From VRTT report, the AC/DC
loadline resistances are within spec, we can use default value defined
in Table 6-1, doc #543977.
BUG=b:70646304
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline
settings from DCI to ensure the values were programmed correctly.
Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23349
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice.
By doing this, SoC can see the DMIC DATA and use for WoV processing.
Thus configuring GPIO_173 as IGNORE IOSSTATE.
TEST=put DUT in S0ix, verify DUT wakes up
Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23246
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Updating from commit id f3bb31fee:
2017-09-08 (vboot: Support EC early firmware selection)
to commit 61cfcc3b:
2018-01-17 (meowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2)
This brings in 57 new commits.
Change-Id: Iadacc6017abbcc659e461d2fc27990ef8124871b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Updating from commit id f6780a36:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)
to commit id e0b38418:
2018-01-16 04:08:26 -0800 - (image_signing: Add sha1sum of keys in keyset to VERSION.signer.)
This brings in 25 new commits.
Change-Id: If60f19decd91eaafec1d555c1e7d3ca0249d8068
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Updating from commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
to commit id 9fd4a36c:
2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
This brings in 596 new commits.
Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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File open function <open()> will return -1 if there's any error. Check that
the return is greater or equal to 0 before using fstat(). Print error message
and exit if there's an error.
This fixes CIDs 1353018, 1353020, 1353027 and 1353028
BUG=b:72062481
TEST=Build no errors
Change-Id: I77d6973d1ad1eadb93922866e618038045be5937
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Tune I2C params for I2C bus 5 to ensure that the frequency does not
exceed 400KHz.
BUG=b:65058277
BRANCH=None
TEST=Measured bus frequency for audio <= 400MHz
Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create
the appropriate selection based on selected board, and if grunt then
define the I2C address.
BUG=b:69416132
BRANCH=none
TEST=make all
Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22960
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable S0ix wake mask programming from coreboot using unified host event
programming interface. Lazy s0ix wake mask helps to configure s0ix wake
mask during boot and EC sets the wake mask during S0ix entry.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix
Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21610
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Function platform_FchParams_reset() is now an empty function, remove it,
its header declaration and its use.
BUG=b:64140392
TEST=Build kahlee.
Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data
from agesa_board_gpios[], wrap format and delete agesa_board_gpios[].
Finally, make platform_FchParams_reset() an empty function.
BUG=b:64140392
TEST=Build gardenia.
Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[]
with data from agesa_board_gpios[], wrap format and delete
agesa_board_gpios[] and get_gpio_table(). Then remove the
get_gpio_table() call from BiosCallOuts.c. Finally, remove
get_gpio_table() from
google/kahlee/variants/baseboard/include/baseboard/variants.h.
BUG=b:64140392
TEST=Build grunt. Build and boot kahlee, recording serial output. Search
for "stage bootblock" and "stage ramstage", indicating GPIO being
programmed.
Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new function sb_program_gpio to be called after AGESA init_reset
and some point within ramstage. For AGESA init_reset, change
amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init
(add the function after the call to AGESA function).
BUG=b:64140392
TEST=Build kahlee, grunt, gardenia.
Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22987
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings)
provides correct iccmax settings for kbl-u based on the SKU. Thus,
there is no need to override these values in devicetree. This change
gets rid of iccmax settings in the nami devicetree.
Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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PC10 is a necessary condition for S0ix entry. With the current C-state limits,
CPU fails to enter PC10 during S0ix. C-state Latency control limits
have to be tuned to new values for PC10 entry.
Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/23220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Linters try to determine whether they are running in a git worktree so
that `git grep` can be used instead of `grep`. These checks are done in
different not truly correct ways and thus the linters don't use `git
grep` when running from a worktree subdirectory, e.g. in a git subtree
environment.
Unify checks using `git rev-parse --is-inside-work-tree`.
Change-Id: I3f54afc99ad0f0e3052cffdd32bdd9649cf3d720
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The HeapAllocateBuffer and HeapDeallocateBuffer functions are not used.
Change-Id: I491a796d87afd0e37051f9caabfff3f70d4d803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/22069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib8d4d3ee490188ce171188d859549da586683e26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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`genbuild_h.sh` checks whether it is running from a coreboot's own git
worktree to decide whether to use git as the time source. This check
fails when `${top}/.git` is a gitfile, e.g. when coreboot is a
submodule.
Add a proper `git rev-parse` call to check the condition, remove `$top`
which is not used anymore.
Change-Id: I8bb13d607a01f4f28fa8b165769e0a1f702da362
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The `gitconfig.sh` script contains a call to `printf` with a lengthy
argument where no format string is used at all. Replace it with a
heredoc for better readability.
Change-Id: I42dbaa570ab9661991fa5d9b4577c9aed05c2981
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ie710f8c6c06332830c3edb9e5490d1e4877ee33b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I556a122753e8a35c4ed32df460a5e12fa85de7f7
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Some non-static declaration remains. If they were made
static, the compiler would output some warnings:
bincfg.y:30:1: warning: useless storage class specifier in empty declaration
};
^
bincfg.y:47:1: warning: useless storage class specifier in empty declaration
};
^
bincfg.y:22:12: warning: ‘yylex’ used but never defined
static int yylex (void);
^~~~~
bincfg.y:456:13: warning: ‘set_input_string’ used but never defined
static void set_input_string(char* in);
^~~~~~~~~~~~~~~~
Change-Id: I753e99c4a8290f9edd9abcda9af8e33b6ccfe406
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23243
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Macro renamed to be in accordance with the name used in the datasheet.
Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The readme.md file was missing the instruction to also compile superiotool,
because autoport errors out without a working version of it.
Change-Id: Ic426b7312f68d59e2e0503d61da694adc9d4fb3f
Signed-off-by: Christoph Pomaska <cp_public@gmx.de>
Reviewed-on: https://review.coreboot.org/23282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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As the code was moved from the Makefile.inc to a separate file in
commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script),`$(MAKE)`
was replaced by `remake`, introducing dependency on this tool which is
basically a `make` with debugging capabilities. Many developers don't
have `remake` installed, leading to pre-commit hooks being not executed
properly. Apparently this was an unintentional change.
Furthermore, special treatment of `make` tool via the `%MAKE%`
substitution performed during hooks' deployment is still desired. Use
case is calling `remake gitconfig` to set `remake` as the `make` tool in
the hooks. To accomplish this, add a parameter that is passed from the
Makefile.inc to gitconfig.sh.
Change-Id: Ia78e06567b904b342dc9b7778569201fe02e6897
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Some script files under the `util` directory have no final newline or
multiple final newlines. This is fixed so that an adapted
`util/lint/lint-extended-015-final-newlines` does not bark at them
anymore.
Change-Id: Icec08f1fc7ea837906653475b7f821aa1a143169
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add NHLT and dt support for max98373 amp
BUG=None
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373
Change-Id: I0b402f89f1ece9e62a394f713c4b0feff29bd1e5
Signed-off-by: N, Harshapriya <harshapriya.n@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/22674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a device driver to generate the device and required properties
into the SSDT for max98373.
TEST=verified SSDT contained relevant params
BUG=None
Change-Id: Id45f74e52855f4b19276e1d3d673d5448207ef4b
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: N, Harshapriya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/22673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add NHLT and dt support for Audio with Max98357 and DA7219
TEST=verified NHLT tables and SSDT entries
BUG=None
Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/22144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add audio NHLT support for cannonlake, reference code is implementation
in apollolake.
CQ-DEPEND=CL:*533799
BUG=None
TEST=None
Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/22134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds a member device_index to r8168 chip information which
allows driver to identify which NIC card requests MAC address.
In this implementation, only 10 NIC cards are supported, the device
index is in the range of 0 to 10. Regarding to MAC address mapping,
when there is only one NIC on DUT, it is treated as a special case
mapping to "ethernet_mac" in VPD for backward compatibility. When
there are multiple NICs on DUT, they are mapping to "ethernet_macN"
where N is [0-9].
Device tree configuration:
For single NIC: .device_index = "0", maps to "ethernet_mac"
For multiple NICs: .device_index = "[1-10]", maps to
"ethernet_mac[device_index - 1]"
BUG=b:69950854
BRANCH=None
TEST=Added device_index = [0-10] under /drivers/net in device tree &&
Programmed the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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this enables the MRC recovery cache for zoombini & variants.
the Kconfig options are:
HAS_RECOVERY_MRC_CACHE
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
one note of caution: early board builds will likely fail to boot with:
tlcl_extend: response is 0
tlcl_extend: response is 0
tlcl_lock_nv_write: response is 0
tlcl_lock_nv_write: response is 28b
Failed to lock rec hash space(1f)
Saving nvdata
hard_reset() called!
the fix is to boot into recovery once, then it's business as usual.
using servo, this can be done with:
dut-control power_state:rec
BUG=b:71785303
BRANCH=chromeos-2016.05
TEST=boots on meowth...
Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23298
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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this adds missing ACPI entries for the EC, CPU, and power button.
also, the EC to AP wakeup pin assignment is fixed.
BUG=b:71819257
BRANCH=chromeos-2016.05
TEST=booted on meowth. /sys/class/power_supply now gets populated.
Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/23237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.
BUG=b:71754828
TEST=Build kahlee.
Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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At AGESA AmdInitReset, SATA enable and IDE enable (elements of
FCH_RESET_INTERFACE) are programmed twice (before calling AGESA
for AmdInitReset and from said AGESA function call out), using
different functions with different results. The first would result
in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the
functions of the second set within the first set, and remove them
from the second set.
BUG=b:71754828
TEST=Build kahlle without the change, boot and record output. Rebuild
kahlee with the change, boot and record output. Compare both outputs,
the should be no change except in timing.
Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch removes IccMax settings from device tree since they
are handled in SoC code from patch e1a75d.
BUG=b:71369428
BRANCH=None
TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot
chromeos-bootimage" & ensure the IccMax settings passed
to FSP are from SoC code.
Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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With the tianocore payload on a Thinkpad X200 the filesize increased
by approximately 50% and the time to fetch and decompress the payload
increased by approximately %300 , so something is definitely wrong
with it and it shouldn't be used as the default compression method.
Change-Id: I9661c82750104d737596e7b3a8974324765938a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Turn on the load switch to the FP MCU at startup, so the kernel can
detect it and use it.
The load switch enable pin is connected to the GPP_A11 PCH pin (aka
PCH_FP_PWR_EN).
BRANCH=none
BUG=b:71986991
TEST=on Meowth, see the kernel detecting a cros_fp device at startup:
[ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected.
[ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Configure the FP MCU interface on GSPI1.
BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.
Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The check for `user.name` and `user.email` being set is done in
`gitconfig.sh` and it uses two subshells where none is actually needed.
Stream redirection can be consolidated.
Change-Id: Ia1d19eb3c11f9d11f030dcc179bc175956cd7116
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The `git sup-destroy` alias uses a subshell in order to make `git
submodule deinit` deinitialize all submodules. This isn't necessary as
the `--all` switch does the same.
Furthermore, `git submodule init && git submodule update` equals to `git
submodule --init`.
Change-Id: Ib690d66795da4049bb0bb350a0609cf2e6b5c4c4
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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`Makefile.inc` checks for `.git` to be present under $(top) to define
the value of $GIT. This check is rather weak and doesn't handle many
edge cases like that of a broken gitfile.
Add a proper `git rev-parse` call to check the condition.
Change-Id: Ifd6da19f13d9f2a9fddb6afd7cb5f16daba2401e
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The variable t32 was originally used to do bitwise operations, but it is
not required anymore. Also, it was assigned twice accidentally, which
introduced a new Coverity Scan defect.
Found-by: Coverity (CID 1385126: (UNUSED_VALUE))
Change-Id: I77afd5064304a36991f63cf1328e13820144efb6
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This automatically generates an FMAP region for the MRC_CACHE driver
which is easier to handle than a cbfsfile.
Adds some spaces and more comments to Makefile.inc to improve
readability.
Tested on Thinkpad x200 with some proof of concept patches.
Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This file is no longer there since ACPI pirq routing is now done in an
automated fashion in SSDT.
Change-Id: I8bafafbf670fe0fc2f20b46b5d8abee722931c6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <cp_public@posteo.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This won't compile since '-' is an operator in C.
Change-Id: Icf900c959cbcbd0b07cd83a1f6866bf255fdcf01
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <cp_public@posteo.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Remove the BiosRam read and write functions that were brought over from
the hudson source. The functionality will be superseded later with new
general-purpose functions.
Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22725
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The internal FCH contains 256 bytes of "BiosRam" that maintains its
state until RSMRST# is asserted or standby power is lost. Add functions
to support read and write operations.
Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM.
Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22723
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocate the acpi_get_sleep_type() function out of the southbridge
ramstage file. This will make it more convenient for using elsewhere.
Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The cbmem location holding the heap will be used to store additional
information in subsequent patches. Remove the static designation from
agesa_heap_base.
Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22721
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A subsequent patch will use GetHeapBase() in more files than
heapmanager.c. Convert it to a format more similar to existing
coreboot source.
Change-Id: I8362af849fc9d7cb1b8a93113e8d78dcac51c20a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA
heap was moved completely into cbmem. This was a departure from the
"late cbmem init" method of adding it late in post, then storing the
S3 volatile data to the region. Remove the hardcoded base address
that was missed in that commit.
To prepare for S3 support, split the region into subregions for
heap, AGESA's S3 volatile storage, and an MTRR save area.
BUG=b:69614064
Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the original spi.c file that writes S3 NV data to flash in a
proprietary format. The s3 folder is retained to facilitate new
development.
Change-Id: I1b5fe8e854c3d2dd71506c2acd6ff73e4b86d7d4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The default time for writing MRC data to flash is at the exit of
BS_DEV_ENUMERATE but this is too early for some implementations.
Add an option to Kconfig for allowing a late option to be selected.
The timing of the late option is at the entry of BS_OS_RESUME_CHECK.
TEST=Select option and inspect console log on Kahlee
BUG=b:69614064
Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22937
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ported from commit e6033ce1
soc/amd/common/block/pi: Fix AGESA heap deallocator
The deallocation was always subtracting the header, even when it
shouldn't. This caused problems for the allocator where buffer
sizes were incorrect and freed and used buffers could collide.
Fix the deallocation size.
Clear deallocated concatinated buffer header memory.
Fix the initial calculation of the total buffer size
available to be allocated.
Original-Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36
Change-Id: Ibac916fcd964adca97a72617428e3d53012e13a1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Iaff0852259f0a91fb4c906e1a01d77b92f8a49f1
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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