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2017-09-13fsp1_0/fsp_util: Rename global symbol find_fspDamien Zammit
To avoid error with symbol redefinition (using clang): src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition ".global find_fsp\n\t" Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp. Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mb/google/soraka: Fine-tune USB 2.0 port4Wisley Chen
Fine tune usb 2.0 strength for port 4 to pass eye diagram. BUG=b:65306272 TEST=build on soraka, measure usb2.0 eye diagram, and result is pass. Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13nb/intel/i945/raminit.c: Replace numbers with macrosElyes HAOUAS
Use macro instead of numbers Change-Id: Ife1aff0a5cf311881b3a11533b71a74c518a633f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/21472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-13amd/stoneyridge: Remove multi-node supportMarshall Dawson
The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13amd/stoneyridge: Simplify SB link routingMarshall Dawson
Remove the check for the southbridge link from Stoney Ridge. The APU is an SoC which can never be installed in a multi-node system. It is pointless to detect and remember the sblink value, which is set by hardware and comes up 0. The BKDG marks this as a reserved field vs. documentation for multi-node-capable Family 15h devices. Because there is only one option for SB link now, relocate the register write done by set_vga_enable_reg() and remove the function. Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setupMarshall Dawson
Delete the check for sibling cores and the programming of CPUID HTT and CmpLegacy back-door bits. The code has no effect on modern Family 15h APUs. The bits being modified come up set out of reset. Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Remove PSP BAR init from cpu initMarshall Dawson
Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The BAR is configured in romstage by AmdInitPost(). Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Make cbmem_top SMM awareMarshall Dawson
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to HAVE_SMI_HANDLER. Change the value returned by cbmem_top() to carve out a range to be used by TSEG. The SMM Mask register has a granularity of 128KB but align the value to 16MB to keep down the number of variable MTRRs required. Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13util/lint: Exclude external payloads from coreboot lowercase checkMartin Roth
Change-Id: I70bbf37fad67fd9bda5724811f4bbdcc53779a42 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-13arch/x86: Fix typo with MTRRKyösti Mälkki
Change-Id: I67a470c2c2a659d5355fdd0939d0572c1ff3e291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13soc/intel/cannonlake: Add ramstage uart debug supportLijian Zhao
Use fixed resources for LPSS uart devices for debugging purpose. BUG=NONE BRANCH=NONE TEST=Boot up with coreboot rom, without this changes, serial log will stop print anything during PCI resourcre setup as MMIO address of UART will be re-assigned. Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13asus/p2b-ls,asus/p3b-f: Move to EARLY_CBMEM_INITKeith Hui
These two boards have been boot tested with EARLY_CBMEM_INIT and is good to go. Change-Id: I2e69901ed83502894f6794b3c1d7bab9aab95e51 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21351 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-13intel/i440bx: Implement EARLY_CBMEM_INIT supportKeith Hui
Implement cbmem_top() required for cbmem support in romstage. Boot tested on asus/p2b-ls. Boards to move to this setup in followup patches. Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20977 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-13google/snappy: Update EC keyboard backlight flag by SKU IDKevin Chiu
Set AP SKU ID by ec command EC_CMD_SET_SKU_ID to update EC keyboard backlight flag. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I1153aa0b89250c55f311dd93a01fcef47afd7292 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13ec/google: Add command to set APU SKU ID to ECKevin Chiu
EC needs to have command to set SKU ID from APU to support specific feature (ex: keyboard backlight) for variant board. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I8cd3b8f646d4134d6bfff2869f6df2d9c615c157 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13vendorcode/siemens: Add LegacyDelay to hwilibWerner Zeh
Add a new parameter to hwilib called LegacyDelay. It will be used to define a delay time to wait for legacy devices if coreboot is too fast for old and slow onboard devices. Change-Id: Id0386fdea0ecfb3c1ff6ec1c456071246529950a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13sb/intel/bd82x6x: Add time-stamp around ME DRAM updateNathaniel Roach
Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UARTV Sowmya
This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress for ACPI debug prints. TEST= Build and boot soraka and fetch the ASL debug prints. Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mainboard/intel/cannonlake_rvp: Include ChromeOS supportLijian Zhao
Add ChromeOS support for cannonlake_rvp platform. Change-Id: Ia02407da8ab4aac2c2c33a7796fc71aea12e2925 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mainboard/intel/cannonlake_rvp: Add dummy DSDT tableLijian Zhao
Add dummy ACPI DSDT table for cannonlake rvp platform. Change-Id: If45c2a7da7f5b20ddd3d56bf9d7f68a85d2f791d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao
Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13vboot: Add config to enable EC EFS supportDaisuke Nojiri
This patch makes coreboot set VBSD_EC_EFS flag if CONFIG_VBOOT_EC_EFS is set. Depthcharge/Vboot uses this flag to determine whether it can update EC when it's already running a RW copy. BUG=b:65028930 BRANCH=none TEST=Verify soft sync runs successfully on Fizz. Change-Id: Ic51ddd4819262162a8d8519461c4ace57ee01cb5 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21489 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-09-13Update vboot submodule to upstream masterDaisuke Nojiri
Updating from commit id 3f3a496a 2017-09-01 09:20:19 (image_signing: Fix loem.ini pattern for unibuilds) to commit id 753e34e9 2017-08-31 10:12:40 (futility: Make rwsig sign command produce EC_RW image) This brings in 5 new commits. This also updates Depthcharge stable commit ID. Updating from a843f262 2016-08-16 08:41:04 (kahlee: select emmc boot first if available) to commit id f3bb31fe 2017-08-15 17:15:33 (vboot: Support EC early firmware selection) This brings in 14 new commits. Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12mb/intel/dg43gt: Fix smbus IRQArthur Heymans
This board uses the reset defaults for DxxIP and DxxIR. The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family" mistakenly says in the D31IP register that all function have INTB as default. This is however not true as documented in the reset default value. This fixes the DSDT such that the SMBus device gets a route for the INT C interrupt it uses. Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21442 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12mb/intel/dg43gt: Select right gmbus port for VGA outputArthur Heymans
TESTED: NGI works on VGA with adapter on DVI-I port Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-12mb/intel/dg43gt: Configure clockgenArthur Heymans
This makes the VGA output on the DVI-I connector usable. This reuses vendor settings. Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-12sb/intel/i82801jx: Add smbus block operationsArthur Heymans
Change-Id: I1a84b4451efe25c1c3b0ce33ddbcb6ed06c29f9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-12AGESA boards: Clean up Ids.h and Filecode.h includesKyösti Mälkki
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Drop heapManager.h includesKyösti Mälkki
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA CIMX: Remove empty set_pcie_(de)resetKyösti Mälkki
For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA: Drop unused northbridge/commonKyösti Mälkki
Change-Id: I8c783e966cf90c6def28d87f07903f50a11487d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up some includesKyösti Mälkki
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12cpu/intel/slot_1: Increase CAR size to 8KiBKeith Hui
Because cpu/intel/car/romstage.c assumes a 8KiB stack size when setting up stack guards, and all Slot 1 compatible CPUs have enough L1 cache available for the increase. Adjust DCACHE_RAM_BASE to match. Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz Tualeron. The latter actually requires this patch to boot successfully. Change-Id: I5b440e7be4f3149378db88872872012c92049c20 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-12cpu/intel/car/cache_as_ram.inc: Fix long standing issuesKeith Hui
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. Do not set %ebp before and switch directly to stack returned by romstage_main(). Remove an unneeded 4-byte gap in CAR stack. The caching strategy for flash XIP area should be WRPROT. Clarify the various comments in the file on the logic. Together they lay the groundwork for bringing EARLY_CBMEM_INIT to intel/slot_1 boards. Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21503 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove unused codeKeith Hui
Remove CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore. Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21502 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove broken HT codeKeith Hui
Remove Hyperthreading related code that was missing setup of SIPI vector and did not work. Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21375 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11ec/lenovo/h8: Add WWAN detection supportPatrick Rudolph
* Add support for detecting WWAN. * Allows to turn off power to WWAN if no card is installed. Add the following devicetree values: * has_wwan_detection Set to one to indicate that the following register are sane. * wwan_gpio_num SB GPIO num to read. * wwan_gpio_lvl SB GPIO level for card to be present (usually zero). Don't enable WWAN power if no card is detected. As there are no devicetree values yet, the new code doesn't have any effect. Change-Id: Ie53275b384c85df8adf71fe79b3d54211c868756 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-11mb/lenovo/*/devicetree: Add BDC detection supportPatrick Rudolph
Add support for BDC detection, based on the schematics for each board. Support for boards without schematics needs further testing. Needs test on all boards. Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-11soc/intel/skylake: Fix SPI WP disable status checkRavi Sarawadi
Use SPI write protect disable bit from BIOS_CONTROL register to check write protect status. Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21449 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11soc/intel/common/block: Update common rtc codeLijian Zhao
Move rtc init code into common area and update the implementation for apollolake to avoid build break. Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11mainboard/intel/cannonlake_rvp: enable eMMCBora Guvendik
Set SCS emmc enable FSP parameter. Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21409 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-09-11payloads/coreinfo: Free buffer before returningMartin Roth
Fixes coverity issue 1373370 - Resource leak Change-Id: I71e0d3ae7f9152e1f89f8b3206526f0d344e0351 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-11kahlee: Add RO_VPD region in FMAPMarc Jones
The RO_VPD region is required for ChromeOS. BUG=b:65408869 TEST=Build and check coreboot.rom with fmap_decode. Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin
The original purpose of adjust_cpu_apic_entry() was to set up an APIC map. That map was effectively only used for mapping *default* APIC id to CPU number in the SMM handler. The normal AP startup path didn't need this mapping because it was whoever won the race got the next cpu number. Instead of statically calculating (and wrong) just initialize the default APIC id map when the APs come online. Once the APs are online the SMM handler is loaded and the mapping is utilized. Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-10nb/intel/i945: Clear timeout bits after disabling watchdogNico Huber
Even with the watchdog disabled, these bits influence other hardware blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet before they started). Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-10AGESA binaryPI: Remove heapmanager from romstageKyösti Mälkki
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved from romstage to ramstage, heapamanager in romstage is no longer needed. Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-10sb/intel/common: Fix HAVE_DEBUG_SMBUSKyösti Mälkki
Failed to build with DEBUG_SMBUS=y, slave_bytes is not initialized until inb(). Change-Id: Ia53717756ed74bc797a9529e36fc6965d6872101 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21470 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-10vboot: Use "Google_" as VBOOT_FWID_MODEL prefix if CHROMEOS is setFurquan Shaikh
CONFIG_MAINBOARD_VENDOR is customizable by OEM for Chrome OS devices. However, VBOOT_FWID_MODEL indicates the firmware vendor and hence if CHROMEOS is selected, then VBOOT_FWID_MODEL should always prefix "Google_" instead of CONFIG_MAINBOARD_VENDOR. BUG=b:65493192 Change-Id: I0a2280bfd6d535586bc14d9a3c4a8198287f08bc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-09-10amdfw: Clean up makefiles a bit moreMartin Roth
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig. - Remove 2nd set of variables that are duplicates of the first set. - Delete duplicate set of Prerequisites Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21451 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-09sb/intel/common: Add HAVE_DEBUG_SMBUSKyösti Mälkki
Change-Id: Ifb1a1eff71968f31af9004ff00717f202d3ec29e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09sb/intel/common: Fix i2c block commandKyösti Mälkki
Coding style, sync implementation with SMBus counterpart. Change-Id: I75f24e2308de945fc03289636ae914bb87070838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09sb/intel/common: Tidy up SMBus block commandsKyösti Mälkki
I forgot to push these changes before merging commit 1b04aa2 sb/intel/common: Fix SMBus block commands Change-Id: I7217f8c0cc78f2161faf31a4c49e3e9515026d15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09ACPI S3: Handle LATE_CBMEM_INIT boardsKyösti Mälkki
Followup removes inlined acpi_is_wakeup_s3() from PRE_RAM, and new implementation depends of CAR_GLOBAL. Change-Id: Iea1c5ab2175f8d496baa09bd6137cacc912df2cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09sb/amd: Support CBMEM_TOP_BACKUPKyösti Mälkki
Change-Id: I8d2005e4f2aa5a3b46e30f52556ee66aeb3d10cc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-08soc/amd/stoneyridge: Update amdfw buildMartin Roth
- The SMU firmware used to be named *.sbin, now is named *.csbin. Update the makefile so that the files can be named as they are delivered and don't have to be renamed. - Add a Kconfig option to allow the secure os binaries to be excluded. BUG=b:64932297 TEST=Build with old and new firmware, verify file sizes. Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-08soc/intel/braswell: add USB2 PHY PERPORTRXISET UPDKevin Chiu
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add USB2 phy setting overrideMatt DeVillier
Adapted from Chromium commit 9756af8. Create hook function to override USB2 phy setting from board level. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add SoC stepping identify helperMatt DeVillier
Adapted from Chromium commit 9756af8. Add SOC helper to identify BSW SoC stepping. Will be used to override USB2 phy setting based on stepping in subsequent commit. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add I2C clock config optionsDivagar Mohandass
Cherry-pick from Chromium commit e3c1ec2. This change includes - FSP config parameters to configure I2C clock speed. - Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz. Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08drivers/intel/fsp1_1: Adjust check for FSP header revisionMatt DeVillier
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1 header files, so adjust the header revision check to ensure that the FSP blob isn't newer than the header, rather than an exact version match. This resolves a version mismatch issue with Braswell ChromeOS devices, which ship with FSP blobs newer than the publicly-released blob (1.1.2.0), but older than the current Braswell FSP 1.1 header (1.1.7.0). TEST: build/boot google/cyan and edgar boards, observe no adverse effects from using current FSP header (1.1.7.0) with the factory- shipped FSP blobs (1.1.4.0/1.1.4.2). Change-Id: I8934675a2deed260886a83fa34512904c40af8e1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08soc/intel/common/block: Common ACPIShaunak Saha
This patch adds the common acpi code.ACPI code is very similar accross different intel chipsets.This patch is an effort to move those code in common place so that it can be shared accross different intel platforms instead of duplicating for each platform. We are removing the common acpi files in src/soc/intel/common. This removes the acpi.c file which was previously in src/soc/common/acpi. The config for common acpi is SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's Kconfig file in order to use the common ACPI code. This patch also includes the changes in APL platform to use the common ACPI block. TEST= Tested the patch as below: 1.Builds and system boots up with the patch. 2.Check all the ACPI tables are present in /sys/firmware/acpi/tables 3.Check SCI's are properly working as we are modifying the function to override madt. 4.Extract acpi tables like DSDT,APIC, FACP, FACS and decompile the by iasl and compare with good known tables. 5.Execute the extracted tables in aciexec to check acpi methods are working properly. Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-08siemens/mc_apl1: Disable internal UARTsMario Scheithauer
APL internal UARTs are not used on this mainboard. Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08siemens/mc_apl1: Set bus master bit for on-board PCI deviceMario Scheithauer
There is one on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I45202937eba11da3bea14fef6ebed70599804335 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08intel/car: Fix stack guard placementKyösti Mälkki
Make sure guard placement is above CAR region. Change-Id: I780cdc0b2a549e7ac4b23b0870619f5648a644e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21313 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08AGESA: Drop old ACPI S3 resume pathKyösti Mälkki
Fixed ACPI S3 support will use POSTCAR_STAGE and no longer uses the code removed here. Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08arch/x86/postcar: Support CBMEM_TOP_BACKUPKyösti Mälkki
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE for MTRR setup after adding this file in the build. Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08arch/x86 postcar: Fix use with stage_cacheKyösti Mälkki
Postcar failed when loading from stage_cache, if romstage did not pass same pcf->stack on normal and resume paths. Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08stage_cache: Add rmodule params in metadataKyösti Mälkki
The change allows to update rmodule parameters after it has been loaded from stage cache. Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08soc/intel/skylake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik
This patch implements soc function to get previous sleep state using chipset_power_state global structure. acpi_get_sleep_type is needed in PRE_RAM stage when soc selects CONFIG_EARLY_EBDA_INIT kconfig option. Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-07soc/intel/common/sgx: Fix null pointer dereference warning from klocworkPratik Prajapati
Fix the warnings of klocwork scan. e.g. "Pointer 'dev' checked for NULL at line 158 will be dereferenced at line 159" Change-Id: I6cc9c68652b074c666c86456183460ca38a886ed Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06google/gru: Re-enable 3V rail GPIO on ScarletJulius Werner
We've decided to move control for the 3.0V rail (technically 3.3V on Scarlet, but who cares about millivolts) back to a GPIO on the AP for Scarlet rev2. This patch adds the necessary code to enable it and make ARM TF aware of its existence. Since the pin had previously not been connected to anything, we shouldn't really need to guard this by board ID... older Scarlets will just be twiddling an empty pin. Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-09-06AGESA f14: Work around soft-resetsKyösti Mälkki
Vendorcode expects some DRAM controller registers to be writable, but they are actually locked after soft resets if C6 states are enabled. Without the workaround, raminit fails on soft resets. Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06mainboard/lippert: Refactor SEMA watchdog messageKyösti Mälkki
It's too critical to ignore when sending the message on SMBus fails, so allow for a fair amount of retries. Failure here causes watchdog to do hard reset later. Move it out of mainboard.c as we need to call this early in romstage while we are debugging. Change-Id: I1006b079269d6dd44de630db7a5694124af2f974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kgpe-d16: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kcma-d8: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-09-06asus/kcma-d8 kgpe/d16: Fix regression for shutdownKyösti Mälkki
Fix regression caused by commit: 714709f AMD fam10 ACPI: Use common fixed sleepstates.asl Adding common sleepstates.asl got lost in rebase process. Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Iru Cai <mytbk920423@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-06mb/google/{poppy,soraka,eve}: Add imon and vmon params for Max98927 codecHarsha Priya
This patch adds imon and vmon slot numbers for Maxim 98927 driver. These values are used to confiure IV feedback for audio playback on speakers. BUG=b:36724448 TEST=After boot, the register dump for Max98927 codecs should have imon and vmon slots numbers set in 0x1e register. Change-Id: I4382da4f984507d147751c168e8177b58c88a70f Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06driver/i2c/max98927: Add imon and vmon paramsHarsha Priya
This change list adds imon and vmon slot numbers as params for Maxim 98927 driver. These values are looked up in the kernel driver to confiure IV feedback for audio playback on speakers. BUG=b:36724448 TEST=After boot, the register dump for Max98927 codecs should have imon and vmon slots numbers set in 0x1e register. Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06util/cbmem: Pretty print STAGEx_META and _CACHEKyösti Mälkki
Also align entries without name with additional indents. Change-Id: Ia6aa303daa11e6aec249232aadf4e346bad659d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06soc/intel/cannonlake: remove duplicate uart.c from bootblockNick Vaccaro
There was already a uart.c added to bootblock. Remove the duplicate addition. Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06soc/intel/cannonlake: Add Vboot/ChromeOS supportLijian Zhao
Add Vboot and ChromeOS support in SOC Kconfig, include a separated verstage in Makefiles.inc as well. Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06mb/google/soraka: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. Change-Id: I76742801e84449d0910ddadf31d39597df3263b9 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06soc/intel/skylake: Add config for enabling PCIe AERRizwan Qureshi
Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06tint: Use the current time as random seedNicola Corna
Previously the random seed was fixed, which led to the same sequence of blocks for each run. Now that libpayload has time(), no change is needed in the function rand_init() of tint. Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/20980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-06util/testing: Don't keep tegra lp0 build resultsPatrick Georgi
We don't actually care for them on our testers, just that the files can be built. Change-Id: Ib656a085d70e2aeb1601f1943ad8581af3133839 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21420 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06AGESA vendorcode: Auto include-dirsKyösti Mälkki
AGESA internal headerfiles are allover the place. Luckily, they have unique names within the Proc/ tree so include every existing directory in undefined order. Change-Id: I86f080e514391a3f0f05d379d24d490ce075060e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-063rdparty/vboot: update to latest masterPatrick Georgi
Besides some internal changes that won't have much effect on coreboot, the newer version also supports building host tools on systems that self-designate as i686. Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06util/testing: Also test-build tegra's lp0 resume codePatrick Georgi
The regular build doesn't build it, so it fails every now and then due to changes in its dependencies. Make sure we notice these early. Change-Id: I0603b22887487d8871611d91e6f8ab0ec210bff1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06Revert "soc/intel/cannonlake: Add dummy ACPI DSDT table"Kyösti Mälkki
This reverts commit 6c0f3c7ee1d53872851dbab636787852e3572c98. Reason for revert: Broke master builds, this was submitted out-of-order, some of the dependencies have not passed review with +2 yet. Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-09-06postcar: Add cbmem_stage_cacheKyösti Mälkki
S3 resume path executing through postcar was unable to utilise cached ramstage in CBMEM. Change-Id: Icc8947c701ca32b4f261ebb78dfc1215b7ed2da0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06AGESA: Drop LATE_CBMEM_INIT in new interfaceKyösti Mälkki
Change-Id: Iffa6cf495b4649f73a1095732509f195ac828248 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06AGESA: Rename assembly from .inc to .SKyösti Mälkki
Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06AGESA f14: Fix duplicate call on S3 resume pathKyösti Mälkki
Change-Id: Ie316df6e2babd8b3e9e79f45ea9719b52b0c2902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06AGESA f15tn f16kb: Fix ACPI S3 resume for FCHKyösti Mälkki
This recovers FCH configuration on S3 resume path. Appearst to work, but other defects of HAVE_ACPI_RESUME must be fixed also before S3 support is re-enabled. Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06mb/sapphire/pureplatinumh61: Disable the SuperIO serialNicola Corna
There is no serial port on this platform. In addition, put the LPC serial IRQ into quiet mode. Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/21226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06soc/intel/cannonlake: Add dummy ACPI DSDT tableLijian Zhao
A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06arch/x86/Kconfig: Add deprecation warnings for LATE_CBMEM_INITJonathan Neuschäfer
The deprecation of late (post-romstage) CBMEM initialization was announced in this blog post: https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ There are two warnings: * In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that aims to explain the problem. * In src/mainboard/Kconfig (just below the mainboard selection), there's a warning which points the user at LATE_CBMEM_INIT, if such a board is selected. Also update the function that needs to be implemented, as pointed out by Keith Hui and Kyösti Mälkki. Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-06nb/intel/i945/raminit.c: Refactor tRD selectionArthur Heymans
Inspired by gm45 code, which sets this value the same way. Some values for tRD on 800 and 1067MHz FSB were set wrong because the CAS/Freq selection was wrong. CAS was often selected to low and when fixing CAS this results in tRD being too high, due to an incorrect lookup table which caused instability. PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5 on GA-945GCM-S2L. Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06device/dram/ddr2: Add a function to normalize tCLKArthur Heymans
Also make most significant bit function accessible outside the scope of this file. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06Makefile: Include Makefile from site-localNaresh G Solanki
Include Makefile from site-local even in absence of DOTCONFIG. This will allow execution of Makefile option from site-local in absence of DOTCONFIG as well. Change-Id: I62d1562687ffe18546add80fdde1196700a65236 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/21303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 10:28:20 +0000