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2023-10-03mb/amd/mayan: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5a321680b1b84ca0b2598d2446ff10257947a733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03dell/snb_ivb_workstations: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I80bd87aa2f97da74a1bbcf05b16f0d5980e142f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/lenovo/t520: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I6b71c7c5c9e32e21c757c0ed0e9c6bd9d58a4f75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78131 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/asus/h61-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I6a78efa4be2ee34e7dac06a8b8014da12b21fbdc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/intel/glkrvp: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I817faab0438a35d2e8859342e7c2b2dbaa0afeeb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78129 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/gigabyte/ga-h61m-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iec0829ba80d3d4b4bc79e14a97d085930c4c5202 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78128 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/intel/mtlrvp: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: If6b666478e15a8e843b50b60be490593349240bd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03soc/intel/alderlake: Hook up FSP repo for RPL-P/SMatt DeVillier
Now that Intel has publicly released FSP headers/binaries for RaptorLake-P/S client platforms, set the defaults accordingly if FSP_USE_REPO is not selected. This does not change any existing defaults as the RaptorLake headers in vendorcode are only used when FSP_USE_REPO is not set. TEST=build/boot google/brya (osiris) Change-Id: Ida92d269fcaf6f323599ec174f4dcedbbe65f03c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78190 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-10-03mb/google/dedede: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5527d5968be35f52b912d9d6e1d9f46f24569bbc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/siemens: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Ic199a60013ceedfd15b191a5fe707be6654ad3a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75078 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-10-03mb/google/rex: Fix ISH I2C pad for suspendCliff Huang
During suspend, the ISH I2C transactions cannot go through because the GPIO pads remain the pervious value. The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus active and functional during suspend. BUG=b:302612549 TEST=on Google/rex platform with ISH enabled, do suspend_stress_test and check that no i2c failure. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/78179 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Li1 Feng <li1.feng@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02security/tpm: Enable Hibernate on setup failureJon Murphy
Set default to enabled for hibernate on setup failure for all devices using a Google EC. This will have no impact on devices that don't bring the GSC down on hibernate, but will provide a recovery path for all devices that do. BUG=b:296439237 TEST=Force error on Skyrim with custom build, boot normally with normal build Change-Id: I2d9e8f75b25fb6c530a333024c342bea871eb85d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78098 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punctJonathon Hall
Librem 11's volume keys act as a PS/2 keyboard with only those two keys. Reduce the minimum number of top-row keys to 2. Make the "rest of keys" (alphanumerics, punctuation, etc.) optional. Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-02util/intelp2m: Support Jasper LakeJonathon Hall
Support generating Jasper Lake GPIO configuration from inteltool logs Change-Id: I519d27e0c91c8d9159224d9bc1c6e49c83270b7a Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2023-10-02drivers/pc80/pc: Split up PS/2 keyboard/mouse ACPI definitionsJonathon Hall
Separate these so a mainboard can describe a PS/2 keyboard without a PS/2 mouse or vice-versa. Librem 11 has a PS/2 keyboard for the volume keys, but does not have a PS/2 mouse, and the presence of a mouse device can cause the cursor to appear on the desktop incorrectly. ps2_controller.asl remains since many boards include it, it now just includes the two new files. Change-Id: I13a4c2caf8dc9e5004b775dc0a9ac2488e39f184 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78096 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bitsFelix Held
Simplify the code a bit by returning 0 early in the function when the SYSCFG_MSR_SMEE bit isn't set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78176 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/amd/common: use common physical address bit reservation codeFelix Held
Instead of having the get_usable_physical_address_bits function that only got used in the data fabric domain resource reporting code, drop this function, select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT in the common AMD non-CAR CPU and rename get_sme_reserved_address_bits to get_reserved_phys_addr_bits so that the common cpu_phys_address_size function will return the correct number of usable physical address bits which now can be used everywhere. The common AMD CAR CPU support is only selected by Stoneyridge which doesn't support secure memory encryption, so RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT isn't selected by the SOC_AMD_COMMON_BLOCK_CAR Kconfig option. Before only the MMIO region reporting took the reserved physical address bits into account, but now also the MTRR calculation will take those reserved bits into account. See the AMD64 Programmers Manual volume 2 (document number 24593) for details. Chapter 7.10.5 from revision 3.41 of this document was used as a reference. The MTRR handling code in older Linux kernels complains when the upper reserved bits in the MTRR mask weren't set, but sets them after complaining and then continues to boot. This issue is no longer present in version 6.5 of the Linux kernel. The calculation of the TSEG mask however still needs to take all physical bits into account, including the ones reserved for the memory encryption. When not setting the reserved bits in the TSEG mask, the Mandolin board with a Picasso APU won't boot to the OS any more due to not returning from SeaBIOS calling into the VBIOS. Haven't root-caused what exactly causes this breakage, but I think previously when something else was wrong with the SMM initialization, also something went wrong when calling into the VBIOS. TEST=Ubuntu 2023.10 nightly build boots on Mandolin via SeaBIOS and EDK2 and Windows 10 boots on it via EDK2. TEST=On Ubuntu 2022.04 LTS, the kernel complained with the following warning, but it still continues the boot process as described above: mtrr: your BIOS has configured an incorrect mask, fixing it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-02x86/include/arch/cpuid.h: Fix inline assemblyPatrick Rudolph
In the cpuid helper functions eax is always written to by the cpuid instruction, so add it to the output clobbered list. This prevents GCC from generating code with undefined behaviour when the function is inlined. Test: Verified that the generated assembly is sane and runtime tests showed no "strange" behaviour when calling cpuid functions. Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78192 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-10-02Update fsp submodule to upstream master branchMatt DeVillier
Updating from commit id a72794810884 (2023-09-07): IoT ADL-N MR1 (4172_00) to commit id 481ea7cf0bae (2023-09-19): Move to RaptorLakeFspBinPkg.dec This brings in 9 new commits: 481ea7cf0b Move to RaptorLakeFspBinPkg.dec 55e25b819e Raptor Lake FSP C.1.BD.40 2b0aac4f64 Raptor Lake FSP C.0.BD.40 3fa75657aa Add Client Raptor Lake FSP 8d24189361 Add Alder Lake and Raptor Lake to README.md 98f4a1fe2f Rename to AlderlakeSiliconPkg c78a6784cb Add FvLateSilicon for Alder Lake 849ce8261b Tiger Lake FSP A.0.7E.70 4b0b1eb4e3 Update SplitFspBin.py to latest from edk2 Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78189 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-10-02mb/google/corsola: Move common selects to BOARD_GOOGLE_CORSOLA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CORSOLA_COMMON. Thus, move all selects to the latter option. Change-Id: I498c6671b2dfc72820fc522744af7ce3b0a62930 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-02soc/mediatek/mt8188: devapc: Add SCP domain settingJason Chen
Configure the SCP to operate within domain 8, allowing it to access only the necessary registers. Any unauthorized access will be prevented by the DAPC. - Set SCP domain from domain 0 to domain 8. - Lock register settings down to prevent unexpected modification. BUG=b:270657858 TEST=scp bootup successful with dapc settings Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-02soc/mediatek/mt8188: devapc: Set master domainsNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch sets domains for masters: SSPM - domain 3 CPUEB - domain 14 PCIE0 - domain 2 SPM - domain 9 Change-Id: Ie3e1d5055e72824257b66d6257982652eeb05953 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77862 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/mediatek/mt8188: devapc: Update permission for master domain setupNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch updates the permission settings for domains 2, 3, 4, 5, 7, 8, 9, and 14, as these domains will be assigned masters in the upcoming patch. BUG=b:270657858 TEST=build pass Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77861 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-29arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORTFelix Held
Since also some AMD CPUs have reserved physical address bits that can't be used as normal address bits, introduce the RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT Kconfig option which gets selected by CPU_INTEL_COMMON, and use the new common option to configure if the specific SoC/CPU code implements get_reserved_phys_addr_bits or if the default of this returning 0 is used instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0059e63a160e60ddee280635bba72d363deca7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-29*/include/cpu: use unsigned int for number of address bitsFelix Held
The number of physical address bits and reserved address bits shouldn't ever be negative, so change the return type of cpu_phys_address_size, get_reserved_phys_addr_bits, and get_tme_keyid_bits from int to unsigned int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e67db6bf0c38f743b50e7273449cc028de13a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-29payloads/edk2: Update default branch for MrChromebox repo to 2023-09Matt DeVillier
Update the default branch used for MrChromebox's edk2 fork from 2023-06 to 2023-09. This updated branch has been rebased on the latest upstream stable tag (edk2-stable202308), and fixes some USB detection issues, as well the coreboot Kconfig for prefering internal or external boot devices. TEST=build/boot google boards link, panther, lulu,reef, ampton, akemi, banshee, zork, frostflow with edk2 payload selected. Change-Id: I7c5f9ae1ca4edd8211f55f4ecf2b3b495f473a43 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-29payloads/edk2: Move TPM disable to separate KconfigMatt DeVillier
Disabling TPM support in edk2 can actually cause problems booting from USB on some Intel-based boards with a CR50 TPM when using the edk2 GOP driver option, so rather than disable the TPM for all CR50 boards, restrict the default to only AMD boards, where the boot hang with TPM enabled was originally observed. TEST=build/boot Win11, Linux from usb on google/fizz when built with edk2 payload and edk2 GOP driver option selected. Change-Id: I01509fea2dd42b741c00abcf9fb8b936e895b932 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78031 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-29mb/google/guybrush: Disable WLAN ASPMTim Van Patten
ASPM on the WLAN PCIe bus introduces large latency spikes, which can be measured with cyclictest: $ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec down to 35-65 usec. These latency spikes can impact the user when real-time processes like Audio (cras) are starved of CPU time, leading to buffer underruns resulting in crackling/distorted audio. ASPM is already disabled for Nipperkin devices (CB:63537), so this CL disables it for both in the shared declaration of guybrush_czn_dxio_descriptors. Power impact for Dewatt: * ASPM enabled power_VideoCall.FDO_25min_webrtc w_energy_rate 7.425043688811071 power_Idle.default20min wh_energy_used 1.4164200000000022 * ASPM disabled power_VideoCall.FDO_25min_webrtc w_energy_rate 8.779998551703423 power_Idle.default20min wh_energy_used 1.4860800000000012 When using Google Meet over WiFi, power increases by ~1.5W. BUG=b:297970318 TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-29mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreenShon Wang
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. Support G2 TS have different slave address by fw_config BUG=b:295272539 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-29mb/asrock/b75m-itx: Order Kconfig selects alphabeticallyFelix Singer
Change-Id: I28a90c236e17d1ea15f5416fab8be7360494e92e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-28util/cbfstool: Revise lex/yacc (bison) generationHung-Te Lin
Revise the Makefile.inc rules for generating FMD parser files. - lex: If --header-file is supported then the lex (usually flex) should also support '-o' so we don't need to do redirection (-t). - yacc: Bison is already required by bincfg and sconfig so we can change the default parser compiler to Bison. That also allows us to use -o and --defines to override the output files. - both: Line directives are only helpful when debugging the scanner and the parser, so we should remove them to get better git diff results (-L for lex, -l for bison). Also regenerated the shipped files with latest version of flex (2.6.4) and bison (3.8.2). Change-Id: I15b58ff65dcd9f3f3a6095aa004091ff733ffec3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-28include/acpi/acpi_pld.h: Remove comment on PLDElyes Haouas
Remove comment on PLD horizontal position as ACPI spec 6.5 define that field: https://uefi.org/specs/ACPI/6.5/06_Device_Configuration.html?highlight=pld%20horizontal#buffer-0-return-value Change-Id: I228e0780699c223f1e3227fd45ec094e0c46205e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-28checkpatch.conf: Remove non-existent warningsElyes Haouas
Change-Id: I05ed882990c45625ad5f08a2bff21a7fda2055db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-28soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabledKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. This patch ensures SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE is selected when PSR is enabled. BUG=b:273207144 Change-Id: I7c9bf8b8606cf68ec798ff35129e92cd60bbb137 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78055 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/skyrim: Enable hibernate on TPM errJon Murphy
Enable hibernate on TPM setup error for Skyrim devices. BUG=b:296439237 TEST=Force the error by hard coding the return code and observe the device entering hibernate. BRANCH=None Change-Id: Ibf96b830f07dac98035d3152c8ec220685a912bc Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77668 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28drivers/tpm: Add tpm failure handlingJon Murphy
Add additional failure mode logic for the TPM to enable an automated recovery mode for GSC hangs. BUG=b:296439237 TEST=Force the error by hard coding the return code and observe the device entering hibernate. BRANCH=None Change-Id: Ieec7e9227d538130354dea8b772d0306cdda1237 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77667 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28drivers/tpm: Add return codes to TPM driverJon Murphy
Add additional failure mode reporting to the TPM driver to provide additional visibility into what failures are occurring. BUG=b:296439237 TEST=Verify code paths on Skyrim, ensure behavior is unchanged. BRANCH=None Change-Id: I77a653201acf1bddc1ed1e2af701c8d3dd4f0606 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77491 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-09-28treewide: convert to tpm_result_tJon Murphy
Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28treewide: convert to %#x hex printsJon Murphy
Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Enable ECAM MMCONF supportArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I70db8bf9f553fa9bfd2a5c20a1393119786047f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-28soc/amd/genoa/reset.c: Add reset methodsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifb4d7dda5fcf1ccacb901b24e4f7cf6945ee16e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76503 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa/southbridge.h: Add PM related macrosArthur Heymans
All verified with PPR. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: If288079310ba74333f04173978f6a123ce95f4d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-28soc/amd/genoa: Add timer & tsc supportArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add function to fetch common code dt configurationArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I5d5d3ff27ab0953844f9bbef30b6487fb480e29b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76500 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-09-28soc/amd/genoa: Deal with memory map for 32M or larger flashArthur Heymans
Only the lower half of the flash gets memory mapped below 4G in the current setup. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/76499 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add Kconfig/Makefile to generate PSP imageArthur Heymans
TESTED: AMD onyx reaches x86 code Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/rex/var/ovis: Add DPTF configurationJakub Czapiga
Configure PL1 and PL2 are configured for powerformance. Based on values from Intel Meteor Lake UH Power Map document ID:640982 BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add chipset.cbvbpandya
Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362 Signed-off-by: vbpandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78082 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-09-28mb/google/nissa/var/craask: Correct the USB setting by fw_configRen Kuo
Modify the settings: 1)Add fw_config probe on USB type C for "DB_1C_LTE". 2)Add fw_config probe on USB type A for "DB_1A_HDMI". BUG=b:296791122 TEST=build and check USB functions on craask Change-Id: I2775098ab380995e62f264bc51a430762c256c4b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/intel/alderlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/redrix with 32MB (W25Q256JWEIM) SPI-Flash. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-27Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id c6e5fba929ef (2023-09-02): MDN: Update ABL to version WABLMDN3516B01A to commit id ae822f2d0db7 (2023-09-21): MDN: Restore SMU fw version 90.41.0 This brings in 3 new commits: ae822f2d0d MDN: Restore SMU fw version 90.41.0 d4f752a6fa MDN: Restore MP2 fw version 0A.0D.00.06 7b7b04723b CZN: Update VBIOS to version 021 BUG=b:301109173 BRANCH=none Change-Id: I02b39ea94a23f7c25533347f06cd8488711c37cd Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-27Documentation: Update 4.22 release notes with x86 .data sectionJeremy Compostella
Change-Id: I2d6d611df8930ad0c473489eacee9019cbdacb9e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78000 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-27acpi: Fix typosNaresh Solanki
Change-Id: Ie986c1cbbc9bcc7817dfeb04a4be86898b302987 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-27soc/intel/jasperlake: Set GPE_STS and GPE_EN register basesJonathon Hall
Jasper Lake was missing these bases, so attempting to enable an SCI would poke unrelated registers starting from offset 0. Set them so GPEs can be enabled. GPE is used on the Librem 11 for the keyboard dock connector, its sense signal on GPP_D4 raises a GPE which is used to indicate tablet/laptop mode to the OS. The register offsets are documented in the datasheet volume 2 (Intel document 634545), all groups' GPE_STS/GPE_EN start at the same offsets. Change-Id: Ib6b9b9a79e9cc4467e609eaf591ec4e87b78d617 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78097 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26Documentation/external_docs.md: Add link to EGS paperDavid Hendricks
Intel published a technical paper about coreboot on Eagle Stream. The document number is 778593. Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: Ic67f9a69b7e2ea526c3c5a604e38bb939c72feec Reviewed-on: https://review.coreboot.org/c/coreboot/+/78117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-26payloads/edk2/Makefile: Improve dirty repo check, sync submodulesMatt DeVillier
Don't skip checking out the specified edk2 branch if the repo contains untracked files, which may be the case if the EDK2_GOP_DRIVER option is selected. Also ensure the submodule pointers are correct when checking out. TEST=build google/panther with GOP driver option and edk2 payload 2x, switching branches between builds and ensure the correct branch is used each time and submodules are synced with branch. Change-Id: If7040bd5c49209b37a4b308485bf59352197d3b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-26payloads/edk2: Guard MrChromebox's build optionsSean Rhodes
Several of the build commands passed by the Makefile only exist in MrChromebox's fork of edk2. Guard these, and the corresponding Kconfig options, against the selection of the MrChromebox repository. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I41d8d54e5b91990dd9fb88967fcd549a86cf6fe9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78036 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26amdfwtool: Support firmware offsets of larger than 16MiBZheng Bao
The mapped windows is up to 16M. Even if the flash size is 32MB, it is not mapped at 0xFE000000. So using "0xFFFFFFFF - rom_size + 1" to get the "rom_base_address" can only explain well when rom_size is less or equal to 16MB. For larger size, it is not physically correct (Even though it can get expected result). If the flash size is larger than 16M, we assume the given addresses are already relative ones. So we don't need the physical base address any more. This commit is part of a series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: I9eea45f0be45a959c4150030e7e213923510ad68 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-26soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes
Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-26amdfwtool: Add APCB for new combo entryZheng Bao
Besides fw.cfg, each combo entry needs dedicated APCB files. If no new APCB is provided, the main APCB is used for all entries. The combo is fully supported after this. Change-Id: I21c2bf7d98ded43848ae8a8bb61d1ded1a277f88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58620 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26arch/x86/cpu_common: use cpuid_get_max_funcFelix Held
Use cpuid_get_max_func instead of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I590f0c840bc62bbd0b5038c5827367d811e30d10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-26arch/x86/smbios: fix extended CPUID level check logicFelix Held
Before the cpuid(0x80000001) read in smbios_write_type4, it was previously checked in a slightly convoluted way if the result from cpu_cpuid_extended_level was larger than 0x80000001, but the check should be if it is larger or equal to 0x80000001. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabcfdb2b8b90d80baf8f4c4d2fd79f1f44866dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78107 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26arch/x86/smbios: use cpu_cpuid_extended_levelFelix Held
Use cpu_cpuid_extended_level instead of open-coding the same functionality in smbios_write_type4. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8e20726ea17e8ed94d5ff8f6568758fcfa162ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-26mb/google/brya/var/dochi: Add memory configMorris Hsu
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:298337185 BRANCH=firmware-brya-14505.B TEST=FW_NAME=dochi emerge-brya coreboot Change-Id: I182e287423e6f784712c5004a6fe2d12a5b36190 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-26mb/google/dedede/var/taranza: Add power limits for JSL N4500 and N5100Sheng-Liang Pan
Add PLx from JSL PDG (ID: 613095) in taranza devicetree. Add ramstage.c in Makefile.inc and update Taranza power limits in taranza ramstage.c. BUG=b:296004956 TEST=emerge-dedede coreboot and check psys and PLx value on taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-09-26mb/google/rex/var/rex0: Configure I2C5 timingIvy Jian
Configure I2C5 timing in devicetree to ensure I2C devices meet timing requirement. BUG=b:300177424 TEST=Build and check I2C devices timing meet spec. | | I2C5-Before | I2C5-After | |-------------|-------------|------------| | FSMB(KHz) | 445.400 | 343.638 | | TLOW(us) | 1.543 | 2.068 | | THIGH(us) | 0.475 | 0.604 | | THD:STA(us) | 0.603 | 0.711 | | TSU:STA(us) | 0.612 | 0.611 | | TSU:STO(us) | 0.605 | 0.611 | | TBUF(us) | >1.914 | >2.044 | Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26mb/google/nissa/var/pirrha: Add 4th DTT sensorSeunghwan Kim
Add 4th sensor device for DTT tuning. BUG=b:292134655 TEST=Built and verified DTT tool could monitor the new sensor device Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2023-09-25mb/clevo/cml-u: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I8530bb9b89a12ae831a4716bdec8c66c7f3f74a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-09-25supermicro/x11-lga1151-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I73844dc4686dd014ec2209e296cc4aff47280e9f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-09-25mb/google/oak: Move common selects to BOARD_GOOGLE_OAK_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_OAK_COMMON. Thus, move all selects to the latter option. Change-Id: Id80b8a9bcad9337c8aa76fa6e5d2c9752b8021b7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-25mb/google/guybrush: Use only one option for common selectsFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_BASEBOARD_GUYBRUSH. Thus, move all selects to the latter option. Change-Id: I570c3cfd3d100ad90e35ec5d89686cb6a4bd8e82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-25soc/intel/xeon_sp: Add HDA disable supportPatrick Rudolph
Currently the HDA device can neither be disabled using softstraps nor can it be disabled by using FSP UPDs. Add code to disable it in coreboot when it's marked as 'off' in coreboot's devicetree. TEST: Device 00:1f.3 is hidden and platform boots into OS without issue. Change-Id: Ifa1422d653cf81ee6faf2bdda27a471c2084642b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77873 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25mb/google/brya: Add SOF driver entries for Nissa-based boardsMatt DeVillier
Facilitates correct profile selection by SOF Windows drivers. Profiles for nokris and quandiso will be added once correct board configs can be determined. TEST=build/boot Win11 on google/craask, verify correct audio profiles loaded, audio functional. Change-Id: Id4582b5dd74a4905ea509813ec99663577360095 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-09-25drivers/sof: Add support for rt5650 speaker/jack topologyMatt DeVillier
Enables correct identification of boards using rt5650 codec for either speaker or headset output (or both) by SOF Windows drivers. Change-Id: Ied9717955fcfca33bd63a34f3f6961deb045239c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25soc/amd/common/graphics: Update VBIOS cache data before hashingMatt DeVillier
On the first boot after flashing, the data read from the FMAP and stored in vbios_data is not valid, so hashing it produces a value which will not match on the subsequent boot, requiring an additional boot before the vbios_data and hash match / before the GOP driver can be skipped. To fix this, update vbios_data before hashing. BUG=b:271850970 BRANCH=skyrim TEST=build/boot google/skyrim with USE_SELECTIVE_GOP_INIT selected, verify that GOP driver execution is skipping on 2nd boot after flashing when booting in normal / verified boot mode. Change-Id: Idc10d752bfa004a34b91307a743c620fb97eeb82 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77727 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-25mb/purism/librem_l1um_v2: Add support for Purism Librem L1UM v2Jonathon Hall
This adds support for booting the Librem L1UM v2 mainboard with coreboot, using binaries from the original BIOS. The following features have been tested on PureOS: - USB: front USB3, rear USB3, USB2 header on board - SATA: 8x SATA ports, one M.2 M-key shared with SATA0 - PCIe: two PEG slots, one PCIe slot from PCH, and one M.2 M-key - Network: 2x GbE - Video: BMC VGA and IPMI - Serial: Physical serial port, provided by BMC SuperIO - Hardware monitor - POST code display - TPM2 These binaries are extracted from the original BIOS: - Intel Management Engine - Intel Firmware Descriptor This was developed and tested on a Librem L1UM v2 using a Core i7-9700 CPU. Native graphics init works for the Aspeed AST2500 BMC. For development, the serial port console works from bootblock. Early init waits for the BMC to finish booting since this is required for serial port output. Change-Id: I990f6024d65098a9553d7d1fe7f36614cc55ea19 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75090 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25mb/google/brya/var/dochi: add generic LPDDR5 SPDs for DochiMorris Hsu
Add Makefile.inc to include five generic LPDDR5 SPDs for the following parts for Dochi: DRAM Part Name ID to assign MT62F1G32D2DS-023 WT:B 0 (0000) K3KL8L80CM-MGCT 1 (0001) H58G56BK8BX068 0 (0000) BUG=b:298337185 TEST=USE="project_dochi emerge-brya coreboot" Change-Id: If0fd4bc950cef484db53b7b21849cfdfdd7816a5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-25mb/google/corsola: Move board-specific selects to board optionsFelix Singer
Instead of selecting board-specific options under the common option and making them conditional, move them to their related board option. Change-Id: If9bea61cb84590e7455add908fa7722c60444503 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25mb/google/corsola: Fine tune LCM ADC voltagesRuihai Zhou
The tolerance of LCM voltage table is too small which leads to wrong panel ID detection. Fine tune LCM ADC voltages based on hardware calculations. BUG=b:300418909 TEST=FW screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id8dec043584f4c552837f70adb491584bfda7acf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-25util: Drop flashrom -p host alias which equals to -p internalHsuan Ting Chen
There is a technical debt in ChromeOS flashrom, `cros_alias.c`, which is to work around ChromeOS calling flashrom with `-p host` instead of `-p internal`. Replace all `-p host` occurrences with `-p internal`. BUG=b:296978620 TEST=none Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I81674213b9a21598002f349ced1130f0844841ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25treewide: Adopt TCG standard namingJon Murphy
Adopt TCG standard naming and definitions for TPM Return codes. BUG=b:296439237 TEST=Build and boot to OS on skyrim BRANCH=None Change-Id: I60755723262ec205a4c134948b0250aac4974d35 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77665 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25Revert "soc/intel/jasperlake: Enable early caching of RAMTOP region"Matt DeVillier
This reverts commit 21e61847c4cf643d79855deba8f58fd45808d571. Reverting as it breaks booting on google/dedede based boards. First boot after flashing is successful, 2nd hangs with the following error: [EMERG] FspMemoryInit returned with error 0x80000003! TEST=build/boot google/dedede (magpie, metaknight) Change-Id: I6a2474617b444414c4248dbeda23ed0915704a17 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-09-25commonlib: Make CBMEM_ID_CSE_BP_INFO little endian, fix id for stringSubrata Banik
This patch fixes the mistake introduced with 'commit 17cea380d985 ("commonlib: Add CBMEM ID to store CSE Boot Partition Info")' where single CBMEM ID name `CBMEM_ID_CSE_INFO` is associated with two different name description. Additionally, use little endian format for `CBMEM_ID_CSE_INFO` cbmem id. TEST=Build and boot google/rex. Able to fix the issue introduced in commit 17cea380d985 while running cbmem --list and verify that the associated name string is proper. Change-Id: I4235f1f6881ab86ccb252065e922d5d526f7f1f7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78110 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-09-24Doc/: Remove an extra spacePatrick Georgi
Change-Id: I462d0bd3e9f3b425631987fa793d29323c3f9d61 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-24Doc/infra: Update my contact informationPatrick Georgi
Change-Id: If7081897d8232e3ac84de0fa76689ad05808996d Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/cherry: Move common selects to BOARD_GOOGLE_CHERRY_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CHERRY_COMMON. Thus, move all selects to the latter option. Change-Id: I080201761d0a06d3b8a5a29de6085dde58960a60 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75085 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/asurada: Move common selects to BOARD_GOOGLE_ASURADA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_ASURADA_COMMON. Thus, move all selects to the latter option. Change-Id: Id80523dce70f13f64a49b71656276c51e80ae5cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75084 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/rex: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id69ea99b452e4214fcc81335a5c961b4da3ce48b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/veyron: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id85503a5ec970ea92c07b99ec7048c521d85c79b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id450a4b6e409a548ee4d79b8b2ebf30ef61a3e27 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78083 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23commonlib: Add CBMEM ID to store CSE Boot Partition InfoKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. In order to backup PSR data before initiating firmware downgrade, CSE Lite firmware supports a command to do this. This command works only after memory has been initialized. So the CSE firmware downgrade can be done only in post-RAM stage. CSE firmware sync actions will be moved to early ramstage to support this. Moving CSE firmware sync actions to ramstage results in cse_get_bp_info command taking additional boot time of ~45-55ms. To avoid this, cse_get_bp_info will be sent in early romstage and the response will be stored in cbmem to avoid sending the command again, and re-use in ramstage. This patch adds a CBMEM ID to store this CSE Boot Partition Info response in cbmem. BUG=b:273207144 Change-Id: I914befadab4ad0ac197435e2a2c4343a796b2b1b Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Move cse_store_rw_fw_version from cse_print_boot_partition_infoKrishna P Bhat D
cse_store_rw_fw_version() stores CSE RW firmware version in global variable or cbmem in romstage and ramstage respectively, based on the stage it is called in. The call to this function is from the cse_print_boot_partition_info() in cse_get_bp_info. In the subsequent patches, the idea is to send the cse_get_bp_info early in romstage and store in cbmem once memory is initialized. So when the cse_fw_sync is called in early ramstage, the stored cse_bp_info_rsp is used instead of sending the CSE get boot partition info command again. To de-link the call to cse_store_rw_fw_version from cse_get_bp_info and to ensure the CSE RW FW version is stored in all cases, moving the function to do_cse_fw_sync. BUG=b:273207144 Change-Id: I0add2c167c85cbddef2ecb4c019061a08562bbdf Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Make cse_bp_info response globalKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. PSR data backup command works only after memory has been initialized. Moving only the downgrade would add complexity of splitting the cse_fw_sync across pre-RAM and post-RAM stages. So the idea is to move cse_fw_sync into ramstage when PSR is enabled. We are introducing a flow to get CSE boot partition info in early romstage and then same data will be stored in cbmem once DRAM is initialized. The CSE BP info data in cbmem will be utilized in early ramstage to perform cse firmware sync operations. This helps in avoiding re-sending the CSE get boot partition info command in ramstage. Having cse_bp_info_rsp as global helps in de-linking cse_get_bp_info from cse_fw_sync. Many functions take cse_bp_info as input parameter. Since cse_bp_info_rsp is global now, we can make use of global cse_bp_info and remove it as input parameter from those functions. BUG=b:273207144 TEST=Verify cse_bp_info_rsp holds value across the stage. Change-Id: I0ee050b49fcae574882378b94329c36a228e6815 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77070 Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2023-09-23soc/intel/meteorlake: Reduce memory test sizeSubrata Banik
Enable upd to reduce size of the memory test. BUG=b:301441204 TEST=Able to build and boot google/rex. w/o this patch: 951:returning from FspMemoryInit 650,922 (79,560) w/ this patch: 951:returning from FspMemoryInit 618,490 (45,621) Change-Id: I903591ec749d270a98895dafb2d8f8d0b287c26a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78067 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-23soc/intel/meteorlake: Hook up UPD LowerBasicMemTestSizeSubrata Banik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure it via devicetree. BUG=b:301441204 TEST=Verified by enabling/disabling the UPD on google/rex. Change-Id: Iec466aeaebd72f222d97f720a85bbb8c27e26325 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78066 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-23vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86Subrata Banik
Update header files for FSP for Meteor Lake platform to version 3323.86, previous version being 3323.84. FSPM: 1. Added new UPDs - AcLoadline - DcLoadline - LowerBasicMemTestSize 2. Address offset changes BUG=b:301441204 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-23arch/x86/cpu_common: use cpuid_e[a,c]xFelix Held
Use cpuid_eax and cpuid_ecx instead of sort-of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0dc2be4f602bf63183b9096e38403ae2f45d959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78058 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23arch/x86/cpu_common: use cpu_cpuid_extended_levelFelix Held
Use cpu_cpuid_extended_level instead of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ea22c3997769179311f3c8822e6d8cc15a8834c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78057 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23vboot: Remove the unnecessary PCR digest checkYi Chou
This PCR digest length check is no longer necessary. Signed-off-by: Yi Chou <yich@google.com> Change-Id: I256938c69be7787f5c8fca3e633ac93a69368452 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78084 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-22mb/google/skyrim/frostflow: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on frostflow, verify unknown device for the fingerprint reader no longer present. Change-Id: I666e92706f698608f2df92c8296cfb615d5ece67 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>