| Age | Commit message (Collapse) | Author |
|---|
|
The bus master bit is set at many places in coreboot's code, but the
reason for that is not quite clear. We examined not setting the
bus master bit whereever possible and tried booting without it,
which worked fine for internal PCI devices but not for PCIe. As a PCIe
device we used a Samsung M.2 NVMe SSD.
For security reasons, we would like to disable bus mastering where
possible. Depending on the device, bus mastering might get enabled
by the operating system (e.g. for iGPU) and it might be required for
some devices to work properly. However, the idea is to leave it disabled
and configure the IOMMU first before enabling it.
To have some sort of "backwards compatibility", add a method which
configures bus mastering based on an additional config option. Since
CB:42460 makes usage of this treewide, enable it by default to keep the
current behaviour for now.
Tested with Siemens/Chili, a Coffee Lake based platform.
Change-Id: I876c48ea3fb4f9cf7b6a5c2dcaeda07ea36cbed3
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42459
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means
enable operation and 0 means stop operation. Override tree exposes
this pin as stop GPIO. Thus, it needs to be configured as active low
i.e. 0 = active (stop), 1 = inactive (enable report).
Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
v3.6+ of reference schematics have moved to using active low polarity
for touchscreen GPIO. This change sets the default polarity in
override tree accordingly to active low. To support boards from older
builds, variant_touchscreen_update() already updates the polarity to
active high.
BUG=b:161937506
Change-Id: I370bdb27ea5d0601612d13b515113a6048018964
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I7d8d39bde3b3364ff6ce93030aa2bab34598acd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
4. Clean up upd override in fsp_params.c, will be added later
5. Temporarily remove _weak attributes in fsp_param & romstage.c
6. Add required headers into include/soc/ from jasperlake directory
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
|
|
Clone entirely from Jasperlake
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/36550
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
6. Add required headers into include/soc/ from JSL directory
Elkhart Lake specific changes will follow in subsequent patches.
1. soc/intel/elkhartlake: Update Kconfig
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Able to uniquely identify the chipset without specifying the platform
specific quirks (adl/cnl/icl/jsl/tgl etc.).
BUG=b:153888802
TEST=Able to dump FD contains correctly without specifying platform
quirks on Hatch Platform.
> ifdtool -d coreboot.rom
Without this CL :
ICH Revision: 100 series Sunrise Point
With this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I83763adb721e069343b19a10e503975ffa6abb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch ensures all unused and reserved flash region sections are not
getting listed while using -d option to dump FD.
BUG=b:153888802
TEST=List only used flash region section with below command
> ifdtool -p tgl -d coreboot.rom
Without this CL :
Found Region Section
FLREG0: 0x00000000
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1: 0x1fff0400
Flash Region 1 (BIOS): 00400000 - 01ffffff
FLREG2: 0x03ff0001
Flash Region 2 (Intel ME): 00001000 - 003fffff
FLREG3: 0x00007fff
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4: 0x00007fff
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG5: 0x00007fff
Flash Region 5 (Reserved): 07fff000 - 00000fff (unused)
FLREG6: 0x00007fff
Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
FLREG7: 0x00007fff
Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
FLREG8: 0x00007fff
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
With this CL :
Found Region Section
FLREG0: 0x00000000
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1: 0x1fff0400
Flash Region 1 (BIOS): 00400000 - 01ffffff
FLREG2: 0x03ff0001
Flash Region 2 (Intel ME): 00001000 - 003fffff
FLREG3: 0x00007fff
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4: 0x00007fff
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG8: 0x00007fff
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I900a29d8968bd61d66c04012e60e1ba4baff786d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:153888802
TEST=Able to dump FD contain using below command
> ifdtool -p tgl -d coreboot.rom
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I0c9106051f4daf592d2467ebf79f9ddb037011dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The BT instruction stores its result in CF and not ZF so use the
correct jump instruction.
This fixes a hang in postcar on CPUs lacking support for this
instruction. This concerns older pre-SSE2 hardware.
Change-Id: I704e3c579150fb9b9a292ef0e83050e7bf7cb078
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
Offset Current value Updated value Analysis
1 0x10 0x11 As per SPD spec rev 1.1
5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs
6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix
12 0x02 0x0A 2 ranks per ch, 16 bits device data width
18 0x05 0x04 4267MHz support
29 0x90 0xC0 HW specific
30 0x06 0x68 HW specific
31 0xD0 0x60 HW specific
32 0x02 0x04 HW specific
125 0x00 0xE1 4267MHz support
BUG=b:159319534
TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:155002684
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
- Use a new variable to store the list of warning types;
- print this list when building an image.
TEST = build image on Kontron mAL-10 COMe module:
IASL 3150 2158 3133 warning types were ignored!
IASL build/dsdt.aml disassembled correctly.
Change-Id: I46f761612254b400563f8567be9bd61601f23467
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Checked with the schematics that all PCIe clocks have a corresponding
clock enable pin.
BUG=b:149970243
BRANCH=zork
Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:149970243
BRANCH=zork
Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:149970243
BRANCH=zork
Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Make the general purpose PCIe clock outputs configurable to be either
permanently enabled, permanently disabled or dynamically enabled via
their corresponding external #CLK_REQx pins in the board's devicetree.
BUG=b:149970243
BRANCH=zork
Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The _SHIFT postfix is a bit clearer than the _SHL one and more in line
with the names used for this kind of defines in coreboot. The
documentation on that register is currently wrong and will hopefully be
fixed in the future; the defines should now match the hardware.
BUG=b:149970243
BRANCH=zork
Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The code using the macro was found not working after finally enabling
the HDA PCI device on the hermes board.
Fix a typo to generate the correct verbs.
Tested on prodrive/hermes.
Change-Id: I953c2e9fbebc1f02bdf71ce868a95f578300c3a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I3288fd3cd6df44cdaddff0b225d4dc9eb8300378
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44898
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I8a91d2a8bc6a1fa709aeadd3b7482d1785068276
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
dirinboz does not support stylus, config AGPIO4/5 to NC
to prevent unexpected wake event for s3.
BUG=none
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
berknip does not support stylus, config AGPIO4/5 to NC
to prevent unexpected wake event for s3.
BUG=b:162376046
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I8d9b711ce1d7300181fe496d490dd33b38bc5983
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replacing the existing defines with macros makes them easier to use in a
function that applies the setting for a certain GPP/GFX clock output.
Also add macros for statically enabling or disabling the clock outputs
and not only for configuring them as controlled by the #CLK_REQx pins.
BUG=b:149970243
BRANCH=zork
Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and
this was probably just copied over from stoneyridge.
BUG=b:149970243
BRANCH=zork
Change-Id: I32f459026c4e8632672123681b20736245f198b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id ace23683b:
2019-09-27 Merge changes from topic "ld/stm32-authentication" into
integration
to commit id a4c979ade:
2020-08-26 Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
This brings in 1825 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id26301dae421eec61c10a2d18842053f3228c557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We do not need to set the CS (Command Stop) bit in the Command Ring
Control Register. CS is implied by CA (Command Abort). I'm not sure if
there is a defined execution order for these command bits, so it's
safer to only use the CA bit as it includes the CS function.
Ref: xHCI spec 1.2 (May 2019), Section 5.4.5, Table 5-24.
BUG=b:160354585,b:157123390
TEST=able to boot into recovery using USB stick on servo v2 on volteer
as well as HooToo 8-1 hub
Change-Id: Iaeba98b6da8da49f529358ca6d68270440ea0f42
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This fixes issues with how we handle events generated by the xHCI
"command abort" command. first, depending on the state of the xHCI
controller, the COMMAND_ABORTED may not be generated. If the
controller was between commands, only the COMMAND_RING_STOPPED event
will be generated. Second, do not adjust the command ring "cur"
pointer as that just confuses the controller.
BUG=b:160354585,b:157123390
TEST=able to boot into recovery using USB stick on servo v2 on volteer
as well as HooToo 8-1 hub
Change-Id: I055df680d1797f35d9730e2bfdb4119925657168
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Some Linux kernel drivers bind to "DMI quirks." In this case, the audio
fw_config is added as an OEM string, e.g., "AUDIO-MAX98357_ALC5682I_I2S"
so the audio topology can be correctly discovered.
But add all successfully probed fw_config items as well, because this
makes it easier to view what is selected from userspace.
BUG=b:161963281
TEST=With CBI FW_CONFIG field set to 0x201:
localhost ~ # dmidecode -t 11
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: DB_USB-USB4_GEN2
String 2: AUDIO-MAX98373_ALC5682I_I2S
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7b7586b0ebfe7b2fd888f448a50ae086364fa718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add a backing cache for all successfully probed fw_config fields that
originated as `probe` statements in the devicetree. This allows recall
of the `struct fw_config` which was probed.
BUG=b:161963281
TEST=tested with follower patch
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0d014206a4ee6cc7592e12e704a7708652330eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
'drm_dp_helper.h' file is duplicated and not used.
Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I21378acd6408a4fae5600a54a41f695e54221dc2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44829
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ibc2446d7b8d4334e26ca6335179f50b7abe301cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44831
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Marking dependencies has undergone some change in Chrome OS tree. The
script to cherry-pick the changes to ChromeOS tree prepends "Original-" to
the concerned meta data i.e. Cq-Depend becomes Original-Cq-Depend. This
causes dependencies to not take effect when changes are submitted to the
continuous integration. Do not prepend "Original-" to the dependency
meta data.
BUG=None
TEST=Ensure that the Cq-Depend line is added without any prefix.
Change-Id: I0503234954f872ee56708e19e89cae9d9fa30df7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
GPP_F11 was in the early gpio table, but the definition was missing
from the main gpio_table. This change adds GPP_F11 to the gpio_table
array.
BUG=none
TEST="emerge-volteer coreboot" and verify it builds correctly.
Change-Id: I40f887300a9dfd4f8e790031b77bbee8a014f499
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Add Makefile.inc to include six generic DDR4 SPDs for the following
parts for Eldrid:
DRAM Part Name DRAM ID to assign
H5AN8G6NDJR-XNC 0 (0000)
MT40A512M16TB-062E:J 1 (0001)
H5ANAG6NCMR-XNC 2 (0010)
K4A8G165WC-BCWE 0 (0000)
K4AAG165WA-BCWE 3 (0011)
MT40A1G16KD-062E:E 3 (0011)
Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use
by gen_spd, the generic DD4 SPD generation tool.
Add dram_id_generated.txt to specify DRAM ID strap settings.
NOTE that Eldrid specified DRAM IDs for the first three parts to be 0
though 2 (i.e. no combined DRAM IDs for parts that use the same SPD).
BUG=b:161772961
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
without error.
Change-Id: Ica62e299ed40e60c2d5928b29ead5d2205b1af66
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4c7f23615bcfd9c2bda2cac8808544b98f8e25a2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ib82689150689716bc9afdf8d4527a1dcd5deae56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This SuperIO chip is used on the Intel DQ45EK mainboard. Restore the
driver that was deleted in commit d3a1a4171ee9 ("src/superio: Remove
unused superio chips"). Changes from the previous version include:
- Replacing the early serial implementation with Winbond common code,
- Replacing the license boilerplate with SPDX headers, and
- Removing unnecessary header file references.
Change-Id: I0ff1a63c47d5dff2599c83a1cebe1ac5ff2136b1
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.
Found-by: Coverity CID 1431994
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ib831646b6a231ad57e3bfef85b801b592d572e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: I669a611e804d67bb6e87775d273dc24b03b06691
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44396
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable TBT2 setting in overridetree.cb based on schematic.
BUG=b:165175296, b:166060548
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Set tcc offset to 5 degree celsius for kaisa and duffy
BUG=b:166696500
BRANCH=puff
TEST=Build, and verify test result by thermal team.
Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MODEM_CLKREQ / CNVI_CLKREQ has no external pull-down resistor.
When there is no M.2 card populated, the pin is floating. Thus
enable an internal 20K PD.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I37e0a9d7e9e0a8c8a7ac198abfd3995b8b0f9e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Add CNVi and PCIe wifi devices to the devicetree and enable the wifi
driver and SMBIOS tables in Kconfig.
Test: both CNVi and PCIe wifi devices work fine
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I16e04dbbf5fc3a163ce5a2bb8de646877d5cbc0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43654
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rework the comments:
- fix wrong gpio / net names
- convert all comments to <gpio> / <net name>
- add more information where appropriate
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Convert PAD_CFG_TERM_GPO with pull "NONE" to its shorter equivalent
PAD_CFG_GPO.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9ed4d97ba184fa3e72425d5d16042a142b0640b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43649
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
INTP_OUT can be used as Type-C VBUS sense input/interrupt but is
currently unused in coreboot. It isn't a requirement for PD to work.
Disable it for now.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Disable internal pull-ups for SATAXPCIE pads since there are external
ones at the M.2 slot's PEDET pins.
Test: both, SATA and NVME devices work fine on both slots
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are pads being unused for various reasons:
a) missing board support (DeepSx: SUSWARN#)
b) unneeded feature ID pins
- currently no known device models without keyboard backlight
- currently no known device models without TPM
c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time
d) DDR_TYPE_*: there is only one known ram model
e) strap-only pads
f) unconnected pads
Configure them as NC with appropriate pull-up if no external pull exists.
The latter was checked by schematics and looking at the board.
When any of the unused ID pins is needed in the future, they can be
reactivated easily (configure as GPI).
Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To support CSE Lite firmware update, CSE RW partition is extracted from
CSE blob binary and added to FW_MAIN_A and FW_MAIN_B.
CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and
FW_MAIN_B is increased to avoid an overflow.
BUG=b:140448618
TEST=build with me_rw binary blob for volteer and boot to kernel.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
L140CU has a TPM2 connected via SPI. Add the TPM device to the
devicetree and enable it.
According to Intel doc#615170-001, PIRQ is required for SPI TPM to work.
Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as
TPM interrupt in Kconfig.
Note: The PCH maps either LPC TPM or SPI TPM to the same address and
handles either LPC or SPI communication transparently. Thus we can use
MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address.
Tested, but only polling works currently, because there is some upstream
issue with the tpm_tis module in current Linux kernels. [1]
[1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This allows calling GETSEC[CAPABILITIES] during early init, when the MSR
isn't locked yet.
Change-Id: I2253b5f2c8401c9aed8e32671eef1727363d00cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: I3ca585429df318c31c2ffd484ec91a7971f18f27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44882
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a security lock and is required for TXT, among other things.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I7b2e8a60ce92cbf523c520be0b365f28413b9624
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44884
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
burnet/esche
Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB
BUG=b:165956924
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix an issue the assembler didn't warn about to fix a crash on real
hardware. qemu didn't catch this issue either.
The linker uses the same address for variables in BSS if they aren't
initialized in the code. This results in %edx being set to the value
of %eax, which causes an exception restoring IA32_EFER on real
hardware.
Tested on qemu with KVM enabled.
Change-Id: Ie36a88a2a11a6d755f06eff9b119e5b9398c6dec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
We can now factor out the essentially duplicated ME functions.
We include a .c file to preserve reproducibility. This is needed because
there are two different `mei_base_address` global variables, and we have
to access the same variables in order for builds to be reproducible.
The duplicate global in `me.c` and `me_8.x.c` will be completely gone
once this new `me_common.c` file becomes a standalone compilation unit.
We are wrapping some things in static inline functions, as they won't be
directly accessible anymore after moving to a separate compilation unit.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I057809aa039d70c4b5fa9c24fbd26c8f52aca736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
|
|
Add support for 10th-gen/Comet Lake-U based boards:
- add PCI IDs for host bridge, IGD, LPC devices
- add support for dumping GPIOs, PCRs, etc
Tested on an unbranded CML-U board running AMI firmware
Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
This PCI ID is required in order for the CML devices to perform
SSDT generation for DPTF.
CML Processor, EDS, Vol 1,
Table 9-5, Section 9.2.
BUG=b:158986928
BRANCH=puff
TEST=builds
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
|
|
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa
signature against digest using PSP svc.
This function will be later used by vboot to accelerate rsa
verification.
BUG=b:163710320, b:161205813
TEST=build zork firmware with vboot modification, confirm it's booting
and boot time is reduced by ~230ms.
Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id 3932b1c:
2020-08-19 02:09:04 +0000 - inclusive: change usage of
blacklist/whitelist
to commit id fefcaa6:
2020-08-24 04:32:03 +0000 - vboot: adjust VB2_SECDATA_KERNEL_FLAGS in
non-recovery path
This brings in 2 new commits.
Change-Id: Ia3ff764537b91f76ba6fa3ba2646638964800510
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
For payloads with UI based on CBGFX, they usually start by calling
clear_canvas or clear_screen and then draw the UI elements. However,
that makes the screen flicker.
A typical solution is to identify and minimize the area to redraw.
However for payloads with complicated UI and do not care about latency,
an alternative is to enable buffered I/O.
The new enable_graphics_buffer() will redirect all graphics I/O
into an invisible working buffer. To flush (redraw) the buffer to the
real screen, call flush_graphics_buffer(). To stop buffering, call
disable_graphics_buffer().
BUG=None
TEST=Add the enable, flush and disable calls to payload 'depthcharge',
built a firmware and boots into Chrome OS recover UI. No more
flickering. The average rendering time on x86 platform is 1.2ms.
Change-Id: Id60a2824fd9e164feae16b92b68b003beabea8d3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44654
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify USI_RESET_L GPIO_140 in touchscreen power on/off sequence
to be active low.
BUG=b:160126287
BRANCH=Zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I53dd872fdacb95cda43f297d2c3f9c6723b27bad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting
BUG=b:162302027
Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.
BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.
Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:162302027
BRANCH=zork
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668
Cq-Depend: chrome-internal:3201648
Cq-Depend: chrome-internal:3202602
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.
Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.
In addition, there are some changes to HOB data structures.
Update UPD and HOB header files and adapt soc accordingly.
TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These parts have not been used in any woomax devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=woomax
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611555
TEST=none
Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
These parts have not been used in any berknip devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=berknip
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611704
TEST=none
Change-Id: I9020fc9cbbb4a97664b0c969dd841c5696a4d60f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These parts have not been used in any dirinboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=dirinboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611271
TEST=none
Change-Id: I605550d44ba57d979df1bd5bef114f8ecc94fa3a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44846
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In generating the potential spds the ddr4-spd-empty.hex was
accidentally omitted.
Generated from:
go run util/spd_tools/ddr4/gen_spd.go src/soc/intel/tigerlake/spd/ \
util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt TGL
Change-Id: Ic8b9449830fb5405ebf138ebd54f41b0f76ba584
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44908
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add mem_list_variant.txt, a list of memory parts used by elemi SKUs.
Add dram_id.generated.txt, a list of dram id's to use for each memory part.
Add Makefile.inc, to specify DDR4 and build the SPD file list.
BUG=b:165461530
TEST=none
Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add memory parts needed by zork boards. Attributes are derived from data
sheets.
BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.
Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive
BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.
Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The TS_DONE_LOADING timestamp description had "(ignore for x86)", but
the implementation in vboot_logic.c will read every bytes, so the
timestamp is correct even for devices with memory mapped boot device
(e.g., x86).
To prevent confusion we should remove the 'ignore for x86' message.
BUG=None
TEST=make -j
BRANCH=None
Change-Id: I01d11dd3dd0e65f3a17adf9a472175752c2b62bc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
I noticed that re-running the lpddr4x SPD parts id tool that generates
the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is
used for the H9HCNNNCPMMLXR-NEE part.
$ go run ./util/spd_tools/lp4x/gen_part_id.go \
src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory
src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt
Based on the currently checked in generic SPDs for LPDDR4x, this
operation changes the Makefile.inc to use lp4x-spd-3.hex for the
H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex.
This change updates that discrepancy in Delbin's memory Makefile.inc.
BUG=none
TEST=none
Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit eb7a1dd80e72ef435c71650284f355f7f57ebe72.
MEMORY_TYPE = lines in Makefiles are not longer needed. Drop it.
Change-Id: I96ac39a30555a870e7778a0e71d738407b6b89ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44895
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a SPI-NOR flash controller which supports pio mode.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
For boards that have already assigned memory ids, there needs to be a
way to fix parts to a specific id. After assigning all the fixed ids the
tool still attempts to minimize the SPDs entries. Since a fixed ID could
be anywhere, gaps can be created in the list. So an empty SPD entry is
created to fill the gaps in the list until they are used.
BUG=b:162939176
TEST=Generate various outputs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).
BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..
Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location. This CL moves
the generic SPDs to the new location.
Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".
Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".
Move TGL DDR4 and LPDDR4x generic SPDs into a common location.
Move JSL DDR4 and LPDDR4x generic SPDs into a common location.
Change the volteer/spd/Makefile.inc to use the new path for the spds.
Change the dedede/spd/Makefile.inc to use the new path for the spds.
BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.
Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Check for duplicate entries in mem parts json file.
BUG=b:162939176
TEST=Verified that tool throws error when there is a duplicate.
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
PCO = Picasso
PLK = Pollock
BUG=b:162939176
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Allow comments in json file for better documentation. Comments must be
on seperate line.
BUG=none
TEST=Injest global_ddr4_mem_parts.json.txt with comments
Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non
intel platforms.
BUG=b:162939176
TEST=Run tool
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable IPU for Volteer and Volteer2 variants for MIPI camera.
BUG=165340186
BRANCH=None
TEST=IPU is enabled and shows in lspci.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I66d60474e16c7a9aa8006d42b22510c1495dbd84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44628
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set psyspl2 to 97% of adapter rating, based on our experiment results.
BUG=b:160676773
TEST=Built and check firmware log.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
|
|
Add additional Elkhart Lake specific SA IDs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I41af9b17b8121f3b47f2242d9beeec297893b378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40854
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Elkhart Lake B0 CPU ID.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I90fab9a6392443005ee7224049931c687cb77c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
|
|
DRIVERS_WIFI_GENERIC is a dependency for these SAR settings.
However, coreboot.org builders are not failing, but chromium
builders are only for serial configurations. It's not clear as
to why. Either way correct this.
BUG=b:159304570
Change-Id: I978b622a3a5a2490b0e3aaa14c24807d5afdff9a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44825
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The gpio_common.h needs EINT_BASE from addressmap.h.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I20834e38343410526da0a489fed907acbf479d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Most of the code is generated using autoport.
Working:
* booting Arch Linux from SeaBIOS
* PCIe/SATA/USB ports (see overridetree and early_init for lists)
* LVDS, DisplayPort, VGA, 3.5 mm jacks, RJ-45
* keyboard, touchpad
* C-States, S3 suspend
Not working:
* rfkill hotkey
* color of the mute hotkey
* sleep f-key
Untested:
* internal speakers and microphone (defective on my machine)
* FireWire
* docking station
* TPM (SeaBIOS detects it, no further test done)
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Change-Id: I916583fad375f16e5b02388cbcad2e8a993e042f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Based on schematic and gpio table of lindar, generate gpio and
overridetree.cb settings for lindar.
BUG=b:161089195
TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Document a general overview of when and how microcode should be updated.
Also explain what microcode updates are, and why they are required.
Change-Id: I6dbe25122fa45a416ed64180ef1bfb11afe676ba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44400
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I2cc38115c27cbbe157fc850bbd88b10ae8001f52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
