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2024-06-28mb/google/volteer/baseboard: Drop disabled SATA settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/intel/tglrvp/dt: Make use of device alias namesFelix Singer
Also, remove superfluous comments from devices which repeat their name. Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28include/device_tree.h: Fix function name fdt_node_nameMaximilian Brune
Rename fdt_node_name to the actual function name and also rename the references. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83084 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28device/azalia_device.c: Always read-write GCAPAngel Pons
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO for Gen1 SoCShuo Liu
For Gen1 SoCs, the range starting from the end of VTd BAR to the end of 32-bit domain MMIO resource window is reserved for unknown devices. Get them reserved. TEST=Build and boot on intel/archercity CRB Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamicallyShuo Liu
vtd_probe_bar_size is used to decide the BAR size. TEST=Build and boot on intel/archercity CRB Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28acpi: Add support for DRHD size reportingShuo Liu
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/brox/variants/brox/fw_config.c: Remove unused macroElyes Haouas
Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_configPoornima Tom
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned off, based on fw_config. Otherwise, when device boots without the cbi settings for wifi6, boot may fail with assertion error for line 817 & 819 of file 'src/soc/intel/alderlake/fsp_params.c'. BUG=b:345596420 BRANCH=NONE TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along with enumeration of corresponding BT device. Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_configPoornima Tom
PCIe based GPIOs of Wifi7 module are enabled based on firmware config. BUG=b:345596420 BRANCH=NONE TEST= Based on fw config configured, wifi6 or wifi7 along with bluetooth ports are detected. Change-Id: If0584e91b5143c6df742961657d242c046409b3a Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable Bluetooth for PCIEPoornima Tom
PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe based Wifi7 module. BUG=b:345596420 BRANCH=NONE TEST=With proper FW config enabled, BT gets detected on port8 Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Enable wifi7 on pcie root portPoornima Tom
Enable pcie based, discreete wifi7 on root port4. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Add fw_config fields for wifi6 and wifi7Poornima Tom
Add a new fw config field for wifi category as WIFI_6, which is CNVi based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing CNVi based wifi port as well as bluetooth port. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-28mb/google/nissa/var/nivviks: Update config for CNViPoornima Tom
Add wake configuration and set 'add_acpi_dma_property'=true for CNVi. Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device. BUG=b:345596420 BRANCH=NONE TEST=SSDT dump showed below: Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-27arch/x86/mpspec: Use uintptr_t for mpc_apicaddrElyes Haouas
Change-Id: I6cc2b3947a2c79e8962985e035e7cc74c2deb307 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-273rdparty/arm-trusted-firmware: Update submodule to upstream masterFelix Singer
Updating from commit id 17bef2248: 2024-02-05 23:33:50 +0100 - (Merge "feat(fvp): delegate FFH RAS handling to SP" into integration) to commit id fe4df8bda: 2024-06-07 12:55:56 +0200 - (Merge "feat(rockchip): add RK3566/RK3568 Socs support" into integration) This brings in 713 new commits. Change-Id: Icce3595fef3a844034e7cc76fc8480ed5b21618c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-27mb/google/brask/var/bujia: Configure Serial IO UARTs ModeShon Wang
This patch configures Serial IO UARTs mode as below. UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design. BUG=b:338917836 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-27Makefile: Add cleanall-symlink targetMartin Roth
This target looks for symbolic links in the coreboot directory, excluding the 3rdparty and crossgcc directories, which both typically have numerous symbolic links, and deletes anything that is found. All possible links are verified as symbolic links before being removed. Any removed links show where they were linked from in case they need to be restored. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8a56e7c628701e4a0471833443b08ab2bcceb27e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83123 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-27Makefile: Update symlink targetMartin Roth
This almost completely replaces the original symlink target for creating symbolic links from site-local into the coreboot tree. Changes include: - A comment about the format of the symlink.txt file - Verify that there are symlink.txt files before doing anything. - Note that symbolic links that already exist are being skipped. - Only use the first line of the symlink.txt file - Make sure the symbolic link to be created is inside the coreboot dir. - Output errors to STDERR - echo -e isn't supported by posix shells, so replace /t with two spaces Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9b0d1b5bc19556bc41ca98519390e69ea104bd1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-27mb/google/brox/var/lotso: GPP_B14 used for buzzerJing Tong
ALC257 does not supoort built-in digtal buzzer, So use external pwm to PCBEEP for beep sound. BUG=b:346956771 BRANCH=None TEST=emerge-brox coreboot sys-boot/chromeos-bootimage firmware-shell: devbeep -> can output beep normally. Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-27drivers/wifi: Support Wi-Fi 7 11be EnablementRavi Sarawadi
Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document 559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3. There are countries where Wi-Fi 7 should be disabled by default. This adds capability for OEM to enable or disable by updating the board specific Specific Absorption Rate (SAR) binary. BUG=b:348345300 BRANCH=firmware-rex-15709.B TEST=SSDT dump shows that the _DSM method returns the value supplied by the SAR binary for function 12 Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-27lib/string: use size_t for local variable in strncmpFelix Held
Since the 'maxlen' parameter's type is changed to size_t, the type of the local variable 'i' which this is compared against should also be changed to size_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83224 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-06-27lib/string: change return types to match C standardFelix Held
The return type of strspn and strcspn is supposed to be a size_t and not a signed integer. TEST=Now the openSIL code can be built with the coreboot headers without needing to add '-Wno-builtin-declaration-mismatch' or '-Wno-incompatible-library-redeclaration' to the cflags. Before the build would error out with various 'mismatch in return type of built-in function' errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83223 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-27lib/string: change parameter types to match C standardFelix Held
The third parameter of strncpy and strncmp is supposed to be a size_t and not a signed int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83222 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-27device/azalia_device.c: Use `azalia_enter_reset()`Angel Pons
Use the existing `azalia_enter_reset()` function instead of explicitly clearing the bit (and having to explain in a comment what this means). Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83217 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-27commonlib/device_tree: Improve node and property allocation speedJulius Werner
Now that the device tree code has been made available in libpayload, we should reintroduce the node and property allocation optimization for libpayload's memory allocator that was originally dropped when porting this code from depthcharge to coreboot. On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree, this saves roughly ~145ms. The total scratch space used is about ~1350 nodes and ~5200 properties, so we leave a little room to grow with the constants hardcoded here. Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2024-06-26mb/google/fatcat: Add minimal code support for fatcatSubrata Banik
This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-26mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage fieldAmanda Huang
Follow nissa baseboard setting for storage field. option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-26mb/google/brox/lotso: Add Fn key scancodeWen Zhang
The Fn key on Lotso emits a scancode of 94 (0x5e). BUG=b:322721490 TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204 Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-26mb/google/brox: Disable Touchscreen for hardware board version 1Karthikeyan Ramasubramanian
On board version 1 and later, touchscreen is not stuffed. Hence configure the relevant GPIOs as not connected, disable the concerned I2C bus in the devicetree as well as SoC chip config for board version 1. BUG=b:347333500 TEST=Build Brox BIOS image and boot to OS. Ensure that there are no peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no touchscreen devices are exported through ACPI SSDT table. Ensure that other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure that the device is able to suspend and resume for 25 cycles. Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26mb/google/brox: Add default ACPI brightness levelsKarthikeyan Ramasubramanian
Kernel need the default brightness steps. Otherwise following error messages are observed in the kernel: [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous error (AE_NOT_FOUND) BUG=b:346807006 TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned error messages are resolved. Ensure that the backlight controls are functional. Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-06-26skl mainboards/dt: Move SsicPortEnable setting into XHCI device scopeFelix Singer
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move serirq setting into LPC device scopeFelix Singer
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-06-26skl mainboards/dt: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move genx_dec settings into LPC device scopeFelix Singer
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-25soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500msTony Huang
Some dongles require more time to be ready, this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make sure the tested dongle display works. Before: [WARN ] DP not ready after 500ms. Abort. After: [INFO ] DP ready after 1211 ms BUG=b:348309582 TEST=emerge coreboot verify tested dongles and monitors display works Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-06-25device/azalia: Separate codec checking and initializationNicholas Sudsgaard
This also changes how debug messages will be printed. I focused on reducing clutter on the screen and made the style of the messages consistent. Before: azalia_audio: Initializing codec #5 codec not ready. azalia_audio: Initializing codec #4 codec not valid. azalia_audio: Initializing codec #3 azalia_audio: viddid: ffffffff azalia_audio: verb_size: 4 azalia_audio: verb loaded. After: azalia_audio: codec #5 not ready azalia_audio: codec #4 not valid azalia_audio: initializing codec #3... azalia_audio: - vendor/device id: 0xffffffff azalia_audio: - verb size: 4 azalia_audio: - verb loaded Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80332 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-25lotso: Update board type to BOARD_TYPE_ULT_ULXKun Liu
Update board type to BOARD_TYPE_ULT_ULX BUG=b:348147663 BRANCH=none TEST=Built and compare the results of command 'dmidecode --type 17 | grep Speed' [Before] Speed: 8400 MT/s Configured Memory Speed: 6400 MT/s [After] Speed: 8400 MT/s Configured Memory Speed: 5200 MT/s Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
2024-06-25util/autoport: Move SPDX header before defines in dsdt.aslNicholas Chin
Macros were being printed before the SPDX header in dsdt.asl, so fix this. Previous output: #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB /* SPDX-License-Identifier: GPL-2.0-only */ Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83187 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-25mb/google/dedede/var/kracko: Add LTE only daughterboard supportRobert Chen
Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree. BUG=b:339534479 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-25Kconfig: Update FW_CONFIG Kconfig optionsMartin Roth
If a board supports FW_CONFIG or ChromeEC CBI, the options should be selected by the mainboard. These are not something that need to be a choice to enable or disable in Kconfig. The defaults are pointless, so remove them. The symbols default to no. Correct the descriptions of FW_CONFIG_SOURCE_CBFS and FW_CONFIG_SOURCE_VPD. They come after CBI and do not override any other options. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icf170dc2ef790d6f5a897a9c7c2ea64033bf1dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83118 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-25mb/google/trulo/var/orisa: Fill in ec.hAmanda Huang
Fill in ec.h according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-25mb/google/trulo/var/orisa: Fill in gpio.hAmanda Huang
Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-06-24util/autoport: Remove extra blank lines from generated filesNicholas Chin
The generated dsdt.asl and early_init.c files contained 2 consecutive blank lines, so remove one of them. Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83186 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24acpi/acpi: Fix Qemu's XSDT patching codePatrick Rudolph
Since Qemu doesn't provide an XSDT, coreboot adds one as separate ACPI table. Qemu only provides the smaller ACPI 1.0 RSDP, but the XSDT can only fit into the bigger ACPI 2.0 RSDP. Currently the exsting RSDP is being reused, without a size check, which works fine on the first boot. However after reboot the XSDT pointer seems to be valid, even though the checksum isn't. Since the XSDT then isn't reserved again on reboot, the memory it's pointing to is reused by other tables, causing the payload/OS to see an invalid XSDT. Instead of corrupting the smaller existing RSDP, allocate a new RSDP structure and properly fill it with both, existing RSDT and XSDT. In addition return the correct length of allocated ACPI tables to the calling code. It was ommiting the size of the allocated XSDT and SSDT. TEST: Run "qemu-system-x86_64 -M q35" and reboot the virtual machine. With this patch applied XSDT is always valid from the OS point of view. Change-Id: Ie4972230c3654714f3dcbaab46a3f70152e75163 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83116 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24mb/google/brox: Add support for batteryless bootingShelley Chen
Set PsysPL2 and PsysPL3 in addition to making adjustments to PL2 and PL4 in order to prevent brownouts when we don't have a battery or have an empty battery at boot time. BUG=b:335046538,b:329722827 BRANCH=None TEST=flash Able to successfully boot on a SKU1 with 45W, 60W+ adapters and SKU2 with a 60W or higher type C adapter. 30W is still being worked on. Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-24acpigen_ps2_keybd: Support a Do Not Disturb keyAseda Aboagye
This commit simply adds support for a Do Not Disturb key. HUTRR94 added support for a new usage titled "System Do Not Disturb" which toggles a system-wide Do Not Disturb setting. BUG=b:342467600 TEST=Build and flash a board that generates a scancode for a Do Not Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2024-06-24acpigen_ps2_keybd: Support an Accessibility keyAseda Aboagye
Add support for an Accessibility key. HUTRR116 added support for a new usage titled "System Accessibility Binding" which toggles a system-wide bound accessibility UI or command. BUG=b:333095388 TEST=Build and flash a board that contains an accessibility key. Verify that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. ``` Testing ... (interrupt to exit) Event: time 1718924048.882841, -------------- SYN_REPORT ------------ Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1 Event: time 1718924054.062428, -------------- SYN_REPORT ------------ Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0 Event: time 1718924054.195904, -------------- SYN_REPORT ------------ ``` [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2024-06-24mb/google/brya: Create tereid variantSowmya V
This patch creates a new tereid variant, which is a Twin Lake platform. This variant uses Nereid board mounted with the Twin Lake SOC and hence the plan is to reuse the existing nereid variant code. BUG=b:346442939 TEST=Generate the Tereid firmware builds and verify with boot check. Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24acer/aspire_vn7_572g: Drop superfluous SATA AHCI mode configurationFelix Singer
The SATA controller is configured to AHCI mode by default. Drop the setting from the devicetree. Change-Id: I027b393300e2cbad827e176afddc197007314f10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SataPortsEnable[x] setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop SataSalpSupport setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174 Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SsicPortEnable setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24Makefile.mk: Fix inclusion of site-local/Makefile.incWerner Zeh
In commit 854dd9a5d1153fbb7ace2a7619bb98d024e284ce (Makefile.mk: Put site-local path first) the inclusion of site-local/Makefile.inc was moved to the first place. Unfortunately, the very next line where subdirs-y is modified resets the variable instead of extending it which overwrites the inclusion of site-local/Makefile.inc. This breaks setups where site-local/Makefile.inc is required. This patch fixes it. Change-Id: I36ad1aca5742869c84e2fb556f898f896c6f037a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-06-24mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as inputAmanda Huang
Configure GPP_R2 as input, no pull according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-23skl mainboards: Move cpu_cluster device to chipset devicetreeFelix Singer
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-23util/autoport: Remove bd82x6x/pch.h from generated mainboard.cNicholas Chin
The southbridge/intel/bd82x6x/pch.h header was previously used to configure a few registers in SPIBAR, but these have since been moved to PCH code and the devicetree, making it unnecessary in mainboard.c Change-Id: I904c95394b4fea73b4990342e647595b5f10335f Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82601 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-22mb/emulation/qemu-riscv/cbmem.c: Fix device_tree.h includeElyes Haouas
Change-Id: I0b49ff8b6275fdde326c79ec21c34faa03094f9e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-22treewide: Move device_tree to commonlibMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-22libpayload/include/endian.h: Add 64 bit enc/decMaximilian Brune
Add 64 bit encode/decode functions to libpayload, since it is required in the patch that moves device_tree to commonlib. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I5dba9a7f41147a511ba1250786e7c51ce623e70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/83082 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21Makefile.mk: Put site-local path firstNikolai Vyssotski
"site-local" Makfile(s) may need to override some of the macros/paths used elsewhere in src/* Makefiles. If we include it last src/* Makefile.mk will have already been processed. MAINBOARD_BLOBS_DIR is an example where the path needs to be overwritten in site-local requiring it to be included first before src/mainboard/* Makefile.mk is processed. Change-Id: I8ea865cd73aba5092a628b0422e5c4121b32fb4d Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-06-21libpayload: add cse_*info pointer to lib_sysinfoEran Mitrani
Set a pointer in lib_sysinfo for CSE_BP_INFO and CSE_INFO. BUG=b:343022317 TEST=Verified CBMEM data in depthcharge on Screebo Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I3aa64d1e439a0596e732a3c0608d60913cefd19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/82790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-21coreboot-sdk/Dockerfile: Remove explicit install of 'm4'Elyes Haouas
Remove m4 as an explicity installed package as it will be installed automatically by flex and bison. Change-Id: Ic4f1c5e6f3324429914bf593047d802dfcc0cb30 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82512 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21mb/google/brask/var/constitution: Generate SPD ID for supported partsMorris Hsu
Add supported memory part in mem_parts_used.txt, then generate. H54G56CYRBX247 BUG=b:199645942 TEST=run part_id_gen to generate SPD id Change-Id: I2169d71695d8d133d26cafe5c7be33b976dd8603 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83127 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hAseda Aboagye
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: d0771e49e7 MKBP: Increase key matrix size The original include/ec_cmd_api.h version in the EC repo is: d0771e49e7 MKBP: Increase key matrix size Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Forest Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21include/input-event-codes.h: Update to latest HID treeAseda Aboagye
This commit simply updates the input-event-codes.h to the HID maintainers' tree at SHA c412e40267dd4ac020c5f8dc8c1cccc04e796ff4. Change-Id: Ic1fb9b18ced37866b84230929cd5c785d0dde9ba Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82993 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-06-21util/intelp2m: Remove blank line after '{'Maxim Polyakov
The generator inserts into the gpio.h an unnecessary blank line in front of the list of macros in the table. Let's remove this from the template to make the code cleaner. These changes have no effect on the configuration of macros. Change-Id: I1141ca630cb6d9a46be5bce2b434762ef8e6fdd0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83003 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21util/intelp2m/platforms: Fix DW register number before clear itMaxim Polyakov
This error does not affect the generated files as the tests are running [1, 2, 3]. However, this once again confirms the need to work on updating the utility. [1] CB:67132 [2] CB:67133 [3] CB:67134 Change-Id: I91e74d65977bd5e10589530258d1709ea33f1af5 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83002 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21mb/emulation/qemu: Configure TSEG sizePatrick Rudolph
Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage. The remaining Qemu code can already handle the bigger TSEG region. TEST: Increased TSEG to 8MiB. Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-06-21commonlib/fsp_relocate: Add PE32+ supportPatrick Rudolph
Add support for PE32+ binaries which can be found on X64 UEFI builds. TEST: Able to relocate and boot a X64 FSP. Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82680 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21util: Move remainings from ipqheader to qualcomm directoryElyes Haouas
With commit 101098c41a ("sdm845: Combine BB with QC-Sec for ROM boot"), most files from ipqheader were moved to the qualcomm directory. Change-Id: I4e5136bd5ec4fd47bbd93cea2e4614fa63a3bd4e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-21soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE infoKapil Porwal
Currently, the payload cannot create new CBMEM entries as there is no such infrastructure available. The Intel CSE driver in the payload needs below CBMEM entries - 1. CBMEM_ID_CSE_INFO to - a. Avoid reading ISH firmware version on consecutive boots. b. Track state of PSR data during CSE downgrade operation. 2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition information on consecutive boots. The idea here is to create required CBMEM entries in coreboot so that later they can be consumed by the payload. BUG=b:305898363 TEST=Store CSE version info in CBMEM area in depthcharge on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiBSubrata Banik
This change updates the Northbridge ASL to conditionally include a QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS` is above 4 GiB. If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the PCH reserved range, the existing handling of `SM01` remains unchanged (as a DWordMemory resource). TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB, verified ASL output. Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21util/ifdtool: Add Panther Lake platform support under IFDv2Subrata Banik
BUG=b:347669091 TEST=Able to build ifdtool. Change-Id: Id261898932f11f4c9066453bce18fd889996e171 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-21soc/mediatek/mt8188: Respect ARM64_BL31_OPTEE_WITH_SMC optionYu-Ping Wu
Since BL31_MAKEARGS is already handled in arm64/Makefile.mk, remove the duplication from mt8188/Makefile.mk. In addition, reserve the memory range for running OP-TEE only if ARM64_BL31_OPTEE_WITH_SMC is enabled. BUG=b:347851571 TEST=emerge-geralt coreboot BRANCH=geralt Change-Id: I88a9a07a685a6c9fe9739b6101ccb8a5ce23fd8b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-21arch/arm64: Add Kconfig option ARM64_BL31_OPTEE_WITH_SMCYu-Ping Wu
Add a new Kconfig option ARM64_BL31_OPTEE_WITH_SMC to control whether to build the OP-TEE dispatcher for BL31. This config also enables the BL31 build option OPTEE_ALLOW_SMC_LOAD, which allows loading the OP-TEE image after boot via a Secure Monitor Call (SMC). For ChromeOS devices, CROS_WIDEVINE_SMC is also enabled to allow passing secrets from firmware to OP-TEE. BUG=b:347851571 TEST=emerge-geralt coreboot BRANCH=geralt Change-Id: I4dcf82d47b537146d71ce3cd2050ec597ed0734f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-20libpayload/x86: Extend exception handling to x86_64 architectureSubrata Banik
Adds 64-bit (x86_64) support to libpayload's exception handler, previously limited to x86_32. Ensures `exception_init_asm` is called when building with LP_ARCH_X86_64 Kconfig. BUG=b:336265399 TEST=Successful build and boot of google/rex and google/rex64 on ChromeOS. Verified correct x86_64 exception handling by triggering "Debug Exception" using firmware-shell as below: firmware-shell: mm.l -0 Debug Exception Error code: n/a REG_IP: 0x0000000030023e9f REG_FLAGS: 0x0000000000000046 REG_AX: 0x0000000000000009 REG_BX: 0x0000000000000000 REG_CX: 0x0000002000000000 REG_DX: 0x0000000000000001 REG_SP: 0x0000000034072ec0 REG_BP: 0x0000000000000009 REG_SI: 0x0000000000000029 REG_DI: 0x0000000034072eef REG_R8: 0x0000000000000009 REG_R9: 0x0000000000000000 REG_R10: 0x0000000000000000 REG_R11: 0x0000000034072d70 REG_R12: 0x0000000000000004 REG_R13: 0x0000000000000001 REG_R14: 0x0000000034072ee6 REG_R15: 0x0000000000000004 CS: 0x0020 DS: 0x0000 ES: 0x0000 SS: 0x0018 FS: 0x0018 GS: 0x0050 Dumping stack: 0x340730c0: 3003c32e 00000000 ... 00000000 00000000 0x340730a0: 30034bc6 00000000 ... 0000002a 00000000 0x34073080: 34073234 00000000 ... 00002e65 00000000 ... ... 0x34072ee0: 340730ed 30300000 ... 34073000 00000000 0x34072ec0: 34072ed8 00000000 ... 00000000 00000008 Ready for GDB connection. Change-Id: I8f0aa1da8d179a760e8d49c3764dfd5a69d06887 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83036 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-20cbfstool: Read XIP stage alignment requirements from ELFArthur Heymans
On x86_64 romstage can contain page tables and a page table pointer which have an larger alignment requirement of 4096. Instead of hardcoding it, read if from the ELF phdrs. Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82102 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-20mb/google/nissa/var/sundance: Increase I2C1 hold time to 126nsRoger Wang
According to the vendor spec, I2C1 hold time needs > 100ns. System needs to adjust the I2C1 sda_hold value from 7 to 13, the system will change the I2C1 hold time from 70ns to 126ns. BUG=b:347157276 TEST=built bootleg and verified test result by EE team Change-Id: I722ec93177b6debf6b4c99de2df68c942560a3ff Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83080 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-20mb/google/brox/var/lotso: enable CNVi bluetoothJing Tong
Lotso's WIFI_BT is same design as brox, copy from brox. BUG=b:339612353 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I030e306dc5d9d3fcb6314bc491dbf5c9ae60bcb7 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83126 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-06-19documentation: Fix evaluation of reStructuredTextFelix Singer
eval_rst isn't a valid directive. Use eval-rst instead. Also, add curly braces where necessary since the MyST parser requires them. Change-Id: I68337354e9bd4de4b2c29d4e42c3bb22337fbe06 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-06-19util: Break up spdx identifier text in scripts & makefilesMartin Roth
The SPDX parsers can find the SPDX identifiers in the scripts and makefiles if they aren't broken up. This unnecessarily confuses things when we're doing license parsing. Change-Id: I215ed047397f342c912f1a969315fa184a124f6a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-06-19mb/google/brox/var/lotso: Update devicetree settingJian Tong
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Ic9a7a9062f5c6e45c5bd9617f3b2a0634b8dc1db Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83051 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-19mb/google/brox/var/lotso: Update verb table from ALC256 to ALC257Jing Tong
Update verb table provided by Realtek on 20240614. BUG=b:344471736 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Device list: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ALC257 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Headphone detection: Event: time 1718633617.056092, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1718633621.471708, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0 Event: time 1718633623.898046, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1718633625.743663, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 1 Event: time 1718633625.743678, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 0 Change-Id: Idde8963de9302849f87b7c262f17d9c9d99b46dc Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83109 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18mb/google/nissa/var/riven: Disable unused GPIOs based on fw_configDavid Wu
Disable LTE, stylus and WFC related GPIOs based on fw_config. BUG=b:337169542 TEST=Local build successfully. Change-Id: I91adc4e70d0d23b737d4fa6725cd96e63108f874 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18mb/google/nissa/var/sundance: disable pcie port7Roger Wang
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:328147465 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-18mb/google/nissa/var/pujjoga: disable pcie port7Roger Wang
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:335312655 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18MAINTAINERS: Add Intel DPTF section with Sumeet Pawnikar as maintainerSumeet Pawnikar
I am the one who takes care of end to end DPTF (Thermal Management) related coreboot things across various X86 based platforms. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I08a1ae48bd5b66ee2f7903615e64d0bab5e0d7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-18mb/google/nissa/var/pujjoga: Update DPTF parametersRoger Wang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:346930334 BUG=b:346930334 TEST= built bootleg and verified test result by thermal team Change-Id: I363eaa72b5190212b014fe4e2c2fca10e2a3f408 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83079 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18mb/google/nissa/var/sundance: Update DPTF parametersRoger Wang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:346932306 BUG=b:346932306 TEST= built bootleg and verified test result by thermal team Change-Id: I6a529365249a5372dd87ef28cb9ea8d540b9cac0 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83078 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-06-18soc/amd/cezanne: Add AMD Renoir SOC supportAnand Vaikar
Add AMD SOC Family 17h Renoir CPUIDs per PPR doc #55922 Renoir is similar to Cezanne with only differences in CCX count. Cezanne has one Zen3 CCX with 8 cores per CCX compared to the two Zen2 CCX with 4 cores per CCX. Hence, coreboot side Cezanne SOC code should be mostly compatible with Renoir and can be leveraged. Change-Id: I6b43eb782527351c79b835d094a5b61103cd6642 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83099 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18cpu/x86: Rename paging structure variables for claritySubrata Banik
The following variables have been renamed: * PDPE_table -> PDPT (Page Directory Pointer Table) * PDE_tables -> PDT (Page Directory Table) This change improves the consistency and clarity of the code as per AMD Architecture Programmer's Manual document. PML4 -> PDPT -> PDT -> 2MB Physical Page TEST=Able to build and boot google/rex64. Change-Id: Ib57d1d54c2c1f4fcce2315b508ed7643251a20c5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-18cpu/x86: Rename `PDE_table` to `PDPT` for 1 GiB page mappingsSubrata Banik
This commit fixes an incorrect variable name in the page table setup for 1 GiB pages. The label PDE_table was used when it should have been PDPT, as it represents a "Page Directory Pointer Table (PDPT)", not a "Page Directory Table (PDT) or PDE_Table". This change ensures correct nomenclature and consistency in the code. PML4 -> PDPT --------> 1GB Physical Page As per x86-64 specification, 1GB pages bypass the Page Directory Table (PDT) level of the page table hierarchy, mapping directly from the Page Directory Pointer (PDPT) Table to the physical page. Change-Id: I1e1064653a265215054f31f0e4e46bf8200ca471 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83100 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-17Revert "mb/google/brox/var/lotso: enable CNVi bluetooth"Matt DeVillier
This reverts commit 0e0bc618e3ed1888ac140010057dc7485443c3c2. Reason for revert: Merged out of order, breaks tree Change-Id: I22bd85a2008db471177257a8b779c06898b1010c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83105 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-17util/intelp2m: Add support for Emmitsburg macro generationFabian Meyer
Test: Generated GPIO for ASRock Rack SPC741D8-2L2T/BCM. Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797 Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-06-17mb/google/nissa/var/riven: Disable storage devices based on fw_configDavid Wu
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:337169542 TEST=Local build successfully. Change-Id: I3d71a35e9c0a33b72720b093b5a05eb69d5bb9f8 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83060 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 04:57:22 +0000