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2024-03-19cpu/x86: Use correct config flag for 1GiB page tableBora Guvendik
The commit below uses USE_1G_PAGETABLES config flag instead of the correct USE_1G_PAGES_TLB. "commit ecbc243a45de3b7894e2fe6c8e22b5d07172274b ("cpu/x86: Add 1GiB pages for memory access up to 512GiB")" Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Reviewed-on: https://review.coreboot.org/c/coreboot/+/81343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-19MAINTAINERS: Update email address of Jonathan for Xeon SPShuo Liu
Change-Id: Icbf04f347a02670d0bf38e0328fa6b523d6851b5 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19mb/google/nissa/var/craaskov: Update eMMC DLL settingsIan Feng
Update eMMC DLL settings based on Craaskov board. BUG=b:318323026 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku Change-Id: I56f8329c28261c2bcae9d058da929be6763b293c Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Yang <simon1.yang@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-19mb/google/nissa/var/glassway: Tune I2C timings for 400 kHzFrank Chu
Update touchpad and touchscreen I2C timing. - Data hold time: 300ns - 900ns BUG=b:328724191 BRANCH=firmware-nissa-15217.B TEST=Check wave form and met the spec. I2C1 (touchscreen) Hold time from 83.58ns to 413.87ns I2C5 (touchpad) Hold time from 95.93ns to 425.27ns Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2024-03-19mb/google/nissa/var/glassway: Adjust touchscreen power sequencingFrank Chu
Adjust touchscreen power sequencing for eKTH5015M. The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec. BUG=b:328170008 BRANCH=firmware-nissa-15217.B TEST=Build and check I2C devices timing meet spec. [INFO ] input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4 Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19cpu/x86/mtrr: Error out caching limitation during NEMSubrata Banik
Improves user experience by highlighting a possibility of runtime hangs caused by unsupported WB caching during NEM. Recently we have encountered an issue on Intel platform and came to know about the NEM logical limitation where due to cache sets are not in power_on_two running into a runtime hang upon enabling WB caching. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-19drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heapShuo Liu
There are 2 ways of referring to linker symbols, as extern u8[] or extern u8*. Only the former will be correctly initiated into an immediate operand (a constant) to asm. DECLARE_REGION defines reference in form of extern u8[]. Use DECLARE_REGION as a standard way for these references. TEST=intel/archercity CRB Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81097 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19soc/intel/xeon_sp: Drop RMRR entry for USBPatrick Rudolph
Drop RMRR entry for XHCI controller since it's not under BIOS control. There's no USB-PS/2 emulation done in SMM, hence it's not needed. TEST=intel/archercity CRB Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-19soc/intel/xeon_sp: Drop uncore_fill_ssdtPatrick Rudolph
Let ACPI DSDT figure out by itself if a stack is enabled. Allows to drop uncore_fill_ssdt() on all platforms. TEST=intel/archercity CRB Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81273 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by defaultPatrick Rudolph
As of now coreboot only supported one PCI segment group and thus the MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the default FSP doesn't allow to disable unused IIO stacks a patched version had to be used. Those unused IIO stacks consume lots of PCI bus ranges, leaving no free buses for the secondary side behind PCI bridges. The IIO disable mechanism doesn't work after ACPI G3 exit and thus requires multiple reboots when the previous state was G3. Since coreboot now supports multi PCI segment groups enable 512 MMCONF buses on 4S platforms by default and drop the IIO stack disable UPDs on ibm/sbp1. This allows to boot faster without the need for a patched FSP. The use of multiple PCI segment groups might prevent legacy software from working properly, however the only board where multiple PCI segment groups are used uses u-root as default payload. TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups. TEST=intel/archercity CRB Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19soc/intel/xeon_sp: Initial support for PCI multi segment groupsPatrick Rudolph
Add PCI enumeration support by reading the PCIeSegment reported in the FSP HOB and add it when creating the PCI domain for each stack. The PCI enumeration will be able to scan the additional PCI segment groups and properly handle those devices. TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled to ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19soc/intel/xeon_sp: Add SATC PCI segment group supportPatrick Rudolph
For every PCI segment group generate a new SATC header. Allows to generate proper ACPI code when multiple PCI segment groups are enabled. TEST=Booted on ibm/sbp1 with multiple PCI segment groups. Properly generates multiple SATC headers. TEST=intel/archercity CRB Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19arch/riscv: add constants for Base ExtensionRonald G Minnich
Get used to this rate of change, SBI adds one new function a month, on average, for the last 7 years. Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Change-Id: Iaad763464678d1921dfefdbee1e39fba2fe5585a Reviewed-on: https://review.coreboot.org/c/coreboot/+/81286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-18symbols: Add __maybe_unused flag to region variable symbolsShuo Liu
In DECLARE_REGION and DECLARE_OPTIONAL_REGION, a set of 3 variables will be defined, that is the region 'base', 'end' and 'size'. However, in many codes, the users will only selectively use 'end' or 'size' instead of both of them, which will trigger compiler errors for unused variables. This patch sets __maybe_unused attributes on 'end' and 'size' so that users do not need to use all of them. TEST=intel/archercity CRB Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81209 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-183rdparty/amd_blobs: update submodule pointerFelix Held
Update the amd_blobs submodule pointer to now include the following commit: picasso: Update PSP fw to version 00.08.14.7B TEST=Mandolin boots to the Windows 10 desktop and the GPU driver works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1bd0b37bebcdd600465dbd48162792e2c32bfb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81263 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-18amdfwtool: Compact the parameter transferingZheng Bao
Remove redundant parameter "debug" from open_process_config(). Change-Id: Ib91a505838d7be4980d6b4f1e95fb8601fbbfd16 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81201 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18amdfwtool: Remove the dissociated combo BIOS table for recovery A/BZheng Bao
For recovery A/B mode, the BIOS tables level 2 are traced by PSP table instead of ROMSIG. There should not be a dedicated BIOS table, nor a combo BIOS table. Change-Id: I8735bd91b32bc9a0e4fc70d293e8d836d5e9c36b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18soc/intel/xeon_sp/uncore_acpi: Fix debug printPatrick Rudolph
The DMAR entries of type "PCI" have no "Enumeration ID" and thus there's no need to print it. Drop all unused Enumeration IDs to simplify the code and debug prints. Document ID: Intel Virtualization Technology for Directed I/O Architecture Specification, Rev. 4.0, Order Number: D51397-015 TEST=intel/archercity CRB Change-Id: I009fbfb9f9d62855d351c5db2d3d88722b5dbfa2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81186 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17genbuild_h: Fix and harden major/minor version parsingNico Huber
Our major version is suddenly two digits long to represent the year. This can't be parsed with the current sed scripts. To make sure that no unparsed data ends up in our major/minor versions, we'll run sed with `-n' and only print the extracted numbers if anything. Also, to allow us to use the version numbers in C code, we strip leading zeros (a leading 0 identifies octal numbers, so for instance 08 for August is not a valid number). This can result in empty major/minor version strings, so we move the default `0' to the final variable expansion. As a bonus, this makes an explicit check if the numbers can be parsed unnecessary. Change-Id: Ie39381a8ef4b971556168b6996efeefe6adf2b14 Reported-by: Christoph Zechner <christophz@vrvis.at> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81290 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17util/intelmetool: Print the address in `map_physical` errors in hexMate Kukri
Previously the incorrect 'd' format specifier was used despite the '0x' prefix implying hex to the user. Change-Id: Ib97bd86ee0e0c8fe8c3785e22a4d9f6def3cae61 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17amdfwtool: Set the level based on cookieZheng Bao
It was complicated and weird to check both the cookie and whether one table is a null pointer. Just checking the cookie is enough. TEST=Identical test on all AMD SOC platform Change-Id: Icab74714990f74e11fd5e899661e4e2d41230541 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17amdfwtool: Set the table size only for FWsZheng Bao
The entry in the table has two categaries, file and pointer. For the pointer, it does not take table space. The ISH, PSP level 2, BIOS table are all the pointer type. So integration function only packs FWs located in folder amd_blobs. And only FWs increase the table size. So the table size is only set once. Later calls only update the count and fletcher. The table has a header at least, so the size can not be 0. The fill_dir_header can take the parameter count as 0, such PSP level 1 only with ISH-A and ISH-B. It doesn't have any file type entries. This actually reverts https://review.coreboot.org/c/coreboot/+/78274 and adds other changes. TEST=Identical test on all AMD SOC platform Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81255 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17commonlib: list: Include <stdint.h>Julius Werner
The list macros use uintptr_t, so they need to include the header that declares it. Change-Id: I56b2a988bb11d40c8761717bcd02a8199c077046 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81288 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17libpayload: Make GPL commonlib includes available to payloads and testsJulius Werner
CB:77968 made some non-BSD commonlib files part of libpayload when CONFIG_LP_GPL is set. This patch exports those headers to the payload (again only when CONFIG_LP_GPL is set) so that payloads can also call the functions in them directly. Also make those includes available to tests so that their functions can be tested. There's no menuconfig for unit tests, so they are included unconditionally, but this should be fine since the tests are standalone and won't have to link with any proprietary third-party code. Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-17drivers/spi: Add support for GD25LR512ME flash romMartin Roth
This device is used on the AMD BirmanPlus board. Change-Id: Iadb819e89a349d074e5ae9f4b62a06176f1f8f64 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-17payloads/edk2: Set the EDK2 repository to custom for UPLSean Rhodes
UPL requires the Shim Layer, and those patches exist in the `starlabsltd` fork. Set the repository to custom, to allow this fork and branch to be selected correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieca72498bde51a184d689670449b66ccc78d658a Reviewed-on: https://review.coreboot.org/c/coreboot/+/81277 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-17mb/google/nissa/var/anraggar: Add pen insert/remove for wakeupJianeng Ceng
Currently, inserting the pen does not wake the system, only removing the pen does. This is caused by the wake event configuration being DEASSERTED, so change it to ANY. BUG=b:328351027 TEST=insert and remove pen can wakes system up. Change-Id: Icdea995c2be04ea459e985f79269e49faf88248d Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-03-17mb/google/brya: Create bujia variantShon Wang
Create the bujia variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:327549688 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_BUJIA Change-Id: I453a50f1aa64f8d4119bf0f860d928aa3e00a144 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81198 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2024-03-17src/Kconfig: Make it possible to override CCACHE in site-localArthur Heymans
The value for CCACHE in site-local/Kconfig gets overridden by the default in src/Kconfig. Remove the default to make overrides possible. Change-Id: I6b9dbbb31caa3ef09afd7ecb355c01bd53807b39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17vc/amd/opensil: don't use source path when using stubMarshall Dawson
Add a 'depends on' statement so that path/to/opensil/source is only active when the stub is not built. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81189 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17soc/amd/phoenix: make openSIL stub optionalMarshall Dawson
Convert the 'select SOC_AMD_OPENSIL_STUB' statement to a config option and give it a prompt. This allows for internal development of openSIL and corresponding coreboot source, and controllable using a defconfig. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/81188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-17soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devicesSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17mb/google/rex: Reland RAMTOP caching for OvisSubrata Banik
This patch ensures Ovis baseboard can select RAMTOP caching to improve the boot time w/o any runtime hang. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis with ~30ms savings in boot time. Change-Id: Ic0b73eb8fb9cd6ca70d3d7168b79dfd0fbc550e3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP rangeSubrata Banik
This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17arch/x86: Add API to check if cache sets are power-of-twoSubrata Banik
Introduce a function to determine whether the number of cache sets is a power of two. This aligns with common cache design practices that favor power-of-two counts for efficient indexing and addressing. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified functionality on google/ovis and google/rex (including a non-power-of-two Ovis configuration). Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17util/lint/lint: Fix shellcheck errors in getopt support for darwinMartin Roth
Posix shell doesn't support '==' Change-Id: Icbdc4204f4c07d806e721fa39f96694c4df00e8d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81285 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-16ec/hp/kbc1126/acpi: Drop unnecessary _STA methodsNicholas Sudsgaard
_STA unconditionally returning 0xF is pretty much the default[1] and should be removed to reduce some noise. [1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html#sta-device-status Change-Id: I0390767aa866e322c762038c12116a15b280af1a Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-16ec/hp/kbc1126/acpi: Drop unnecessary method argumentsNicholas Sudsgaard
Method(..., 0, NotSerialized) is the default[1] and can be reduced to Method(...) which reduces some noise. TEST=Timeless build produces the same binary [1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/19_ASL_Reference/ACPI_Source_Language_Reference.html#method-declare-control-method Change-Id: Ic24e004500a7fa2a5a5b38a3f6f0e13e4ce7dfac Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81205 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2024-03-153rdparty/intel-microcode: Update submodule to upstream mainFelix Singer
Updating from commit id ece0d29: 2023-11-14 10:19:09 -0600 - (microcode-20231114 Release) to commit id 41af345: 2024-03-11 19:11:14 -0600 - (microcode-20240312 Release) This brings in 1 new commits: 41af345 microcode-20240312 Release Change-Id: Iaea865100661776c5331cba6c92ef51dfd410159 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-15mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMeSeunghwan Kim
NVMe using clk_src[0] and clk_req[1] mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=0,clk_req=1 in mFIT. BUG=b:328318578 TEST=build firmware and veirfy suspend function on NVMe SKU DUT. Cq-Depend: chrome-internal:7063434 Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-15brox: ish: Add Kconfigs for ISHYuval Peress
Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-15treewide: Move stdlib.h to commonlibMaximilian Brune
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-14soc/intel/xeon_sp: Rewrite acpi_fill_dmarShuo Liu
Rewrite the function by iterating IOMMU (Input/Output Memory Management Unit) devices instead of iterating socket and stacks, which is more aligned to coreboot infrastructure. TEST=intel/archercity CRB coreboot DRHD generation is compared, the order of sections are changed as expected but the content is kept equvalient. Change-Id: I700513e05181303cf3f4effc793a872eb23340cb Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81228 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14soc/intel/xeon_sp: Rewrite acpi_create_drhdShuo Liu
Obtain IOMMU (Input/Output Memory Management Unit) info and enumerate devices using device utils instead of FSP HOB interface, which might change across SoC generations and no ambiguity across multiple PCIe segments. TEST=intel/archercity CRB coreboot DRHD generation log no changes before and after Change-Id: Ic5c404899172a0e4fba2721b8e8ca6c1f0856698 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81227 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14intelblocks/pmc: Assign initial values to pmc_gpe_init variablesGang Chen
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1 and dw2. dw0, dw1 and dw2 are uninitialized before calling soc_get_gpi_gpe_configs. This is error prone for some soc implementations where soc_get_gpi_gpe_configs does nothing. This patch is simple, just to assign zero values to dw0, dw1 and dw0, to enhance the code robustness. TEST=intel/archercity CRB Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14arch/riscv: support physical memory protection (PMP) registersRonald G Minnich
PMP (Physical Memory Protection) is a feature of the RISC-V Privileged Architecture spec, that allows defining region(s) of the address space to be protected in a variety of ways: ranges for M mode can be protected against access from lower privilege levels, and M mode can be locked out of accessig to memory reserved for lower privilege levels. Limits on Read, Write, and Execute are allowed. In coreboot, we protect against Write and Execute of PMP code from lower levels, but allow Reading, so as to ease data structure access. PMP is not a security boundary, it is an accident prevention device. PMP is used here to protect persistent ramstage code that is used to support SBI, e.g. printk and some data structures. It also protects the SBI stacks. Note that there is one stack per hart. There are 512- and 1024-hart SoC's being built today, so the stack should be kept small. PMP is not a general purpose protection mechanism and it is easy to get around it. For example, S mode can stage a DMA that overwrites all the M mode code. PMP is, rather, a way to avoid simple accidents. It is understood that PMP depends on proper OS behavior to implement true SBI security (personal conversation with a RISC-V architect). Think of PMP as "Protection Minus Protection". PMP is also a very limited resource, as defined in the architecture. This language is instructive: "PMP entries are described by an 8-bit configuration register and one XLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 16 PMP entries are supported. If any PMP entries are implemented, then all PMP CSRs must be implemented, but all PMP CSR fields are WARL and may be hardwired to zero. PMP CSRs are only accessible to M-mode." In other words if you implement PMP even a little, you have to impelement it all; but you can implement it in part by simply returning 0 for a pmpcfg. Also, PMP address registers (pmpaddr) don't have to implement all the bits. On a SiFive FU740, for example, PMP only implements bits 33:0, i.e. a 34 bit address. PMPs are just packed with all kinds of special cases. There are no requirements that you read back what you wrote to the pmpaddr registers. The earlier PMP code would die if the read did not match the write, but, since pmpaddr are WARL, that was not correct. An SoC can just decide it only does 4096-byte granularity, on TOR PMP types, and that is your problem if you wanted finer granulatiry. SoC's don't have to implement all the high order bits either. And, to reiterate, there is no requirement about which of the pmpcfg are implemented. Implementing just pmpcfg15 is allowed. The coreboot SBI code was written before PMP existed. In order for coreboot SBI code to work, this patch is necessary. With this change, a simple S-mode payload that calls SBI putchar works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. TEST: Linux now boots partly on the SiFive unmatched. There are changes in flight on the coreboot SBI that will allow Linux to boot further, but they are out of scope for this patch. Currently, clk_ignore_unused is required, this requires a separate patch. Change-Id: I6edce139d340783148cbb446cde004ba96e67944 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-14soc/intel/xeon_sp: Add utils to detect domain0 and stack0Shuo Liu
In Xeon-SP, the domain0, which is located at stack0, usually needs special handling due to the compatible devices on it (HEPT, IO-APIC and legacy IOs). This patch adds util function detect whether a give domain or stack is with such a role. TEST=intel/archercity CRB Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14soc/intel/xeon_sp: Add domain role checking utilsShuo Liu
For Xeon-SP, there are 4 main domain roles (PCIe/CXL/IOAT/UBOX). This patch adds util function to check whether a given domain belongs to one of these roles, or a give device belongs to a domain of the specific role. TEST=intel/archercity CRB Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14soc/intel/xeon_sp: Use common _CRS code generationPatrick Rudolph
Drop SoC specific code and use generic implementation provided by pci_domain_fill_ssdt. TEST=Booted on IBM/SBP1 to Ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14soc/intel/xeon_sp: Drop IIO_UDS argumentPatrick Rudolph
Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob. Allows to drop the argument in Xeon-SP common layer. TEST=intel/archercity CRB Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81181 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14util/nixshell: Add a dev shell for i386 archCrabtux
Add a Nix shell file to provide a simple environment for coreboot development of i386 architecture. Currently, this environment is capable of completing Tutorial Part 1 in https://doc.coreboot.org. The Nix shell can be used by running the following command: $ nix-shell --pure util/nixshell/devshell-i386.nix The `--pure` parameter is optional. In Nixpkgs, there is a package called 'coreboot-toolchain'. It fetches the source code of coreboot, build crossgcc, and export it as output. With the binary cache mechanism of Nix, crossgcc can be directly downloaded and used without compiling on user's machine. This Nix shell has been tested on a NixOS laptop and a Debian 12 server, and they both work fine. Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f Signed-off-by: Crabtux <crabtux@mail.ustc.edu.cn> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-14ec/hp/kbc1126: Use ec/acpi/ec.h instead of its own implementationNicholas Sudsgaard
This also does some light cleaning up: - Place spaces in function names to make it easier to read. - Adds a newline to a console message. TEST=Tested to work on HP ProBook 450 G3 Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81204 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14vendorcode/edk2-stable202302: Remove wchar_t assertsArthur Heymans
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used. The FSP interface does not depend on wchar_t. TEST: the resulting binaries are the same for intel/mtlrvp Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-14mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC configFrank Chu
Define SSFC bit 0-1 in coreboot for add 2nd BOE G7500 touchscreen. BUG=b:329339069 BRANCH=firmware-nissa-15217.B TEST=Check touchscreen can detect and function work. [INFO ] input: GTCH7503:00 2A94:A804 as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-GTCH7503:00/0014 Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-143rdparty/fsp: Update submodule to upstream masterFelix Singer
Updating from commit id dd98487: 2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path) to commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) This brings in 8 new commits: cc6399e IoT MTL-UH & MTL-PS PV (3471_49) FSP 193dfbe Merge branch 'master' of https://github.com/intel/FSP c89f32a IoT ADL-S MR7 (4445_05) FSP bd31c89 IoT ADL-P MR6 (4445_04) FSP 738e498 Copy TGL FirmwareVersionInfoHob.h 9e7be91 IoT ADL-S MR7 (4445_05) FSP 56fb36c IoT ADL-P MR6 (4445_04) FSP 4707bc7 Elkhart Lake IPU2024.2 FSP Change-Id: Ifa21950d6088b561f923587ca0f797de2983b67d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-13mb/google/brox: Enable EC SW SyncShelley Chen
Now that EC software sync has been verified to work on Brox, we can enable it by default. BUG=b:326152804 BRANCH=None TEST=Verify that SW sync occurs Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13cbfs: Remove broken remnants of PAYLOAD_INFO featureJulius Werner
PAYLOAD_INFO is a very old feature that can add a key/value information section to a payload file. It seems to have only ever been generated by coreinfo and never really read by anything. Since CB:1721 in 2012, the feature has been inadvertently broken in practice since the `.note.pinfo` sections that contain the information get discarded from the payload before cbfstool gets to see them. Since CB:28647 in 2018, support for the section in the SELF loader was (inadvertently?) dropped, so if someone actually fed cbfstool a payload ELF that did have a `.note.pinfo` section, modern coreboot would refuse to boot the payload entirely (which is probably not a good state to leave things in). This patch removes the code to generate PAYLOAD_INFO entries entirely, but leaves the support to parse and extract those sections from old payloads in place in cbfstool. Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-13Revert "soc/intel/xeon_sp: Rewrite acpi_create_drhd"Martin L Roth
This reverts commit 6995efbd1b986d0426ca513fd2e56771dd489f16. Reason for revert: Submitted out of order and broke the coreboot build: src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 275 | if (is_dev_on_domain0(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 343 | if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 423 | assert(vtd_mmio_cap != 0xffffffffffffffff); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 455 | assert(ptr); | ^~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 540 | if (is_domain0(dev_get_pci_domain(dev))) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 546 | assert(iommu0); | ^~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ Change-Id: I8b66177119ea5f55913a16aae06a3dcb807c2c64 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-13Revert "soc/intel/xeon_sp: Rewrite acpi_fill_dmar"Martin L Roth
This reverts commit 6833e8c01afc2827f150135f3805dc71820ddaa4. Reason for revert: Submitted out of order and broke the coreboot build. src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 275 | if (is_dev_on_domain0(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 343 | if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 423 | assert(vtd_mmio_cap != 0xffffffffffffffff); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 455 | assert(ptr); | ^~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 540 | if (is_domain0(dev_get_pci_domain(dev))) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 546 | assert(iommu0); | ^~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ Change-Id: If919d6fa578a82fbb6bc5e1fd2adf4e9f59cab95 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81232 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-13payloads: allow selecting a file for FLAT_BINARYRonald G Minnich
085c97363ed6477c64b61263a59d7e9642e05cda introduced a bug in that we could not select a file to use, and, in fact, the payload was never installed into the image in this case. Add FLAT_BINARY to the predicate enabling a file selection dialog. Change-Id: I8174b656b1e6ebb3663172f473e4070b30f19126 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81183 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13mb/google/brya/var/omniknight: Pull down USI_REPORT_EN in romstageJamie Chen
Pull down USI_REPORT_EN(GPP_C6) in romstage to solve an abnormal peek pull high before BL_EN. Because power sequence no meet spec, pre #comment36, it may have ghost touch. BUG=b:326337003 TEST=FW_NAME=omnigul emerge-brya coreboot, measurement of HW and test touch detection by evtest Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80769 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-13soc/intel/xeon_sp: Rewrite acpi_fill_dmarShuo Liu
Rewrite the function by iterating IOMMU (Input/Output Memory Management Unit) devices instead of iterating socket and stacks, which is more aligned to coreboot infrastructure. TEST=intel/archercity CRB coreboot DRHD generation is compared, the order of sections are changed as expected but the content is kept equvalient. Change-Id: I4c1cbf8d8fc93f746640efc3a82c539dcb3fdee2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-13soc/intel/xeon_sp: Rewrite acpi_create_drhdShuo Liu
Obtain IOMMU (Input/Output Memory Management Unit) info and enumerate devices using device utils instead of FSP HOB interface, which might change across SoC generations and no ambiguity across multiple PCIe segments. TEST=intel/archercity CRB coreboot DRHD generation log no changes before and after Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81048 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13soc/intel/mtl: Improve functions in soc_info.cTyler Wang
Remove debug message since it's static information. Remove additional uint_8 varience and return below settings directly: 1. CONFIG_SOC_INTEL_USB2_DEV_MAX 2. CONFIG_SOC_INTEL_USB3_DEV_MAX 3. MAX_TYPE_C_PORTS 4. CONFIG_MAX_TBT_ROOT_PORTS 5. CONFIG_MAX_ROOT_PORTS 6. CONFIG_MAX_PCIE_CLOCK_SRC 7. CONFIG_SOC_INTEL_UART_DEV_MAX 8. CONFIG_SOC_INTEL_I2C_DEV_MAX 9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX BUG=none TEST=Build and test on rex/karis, system can boot to OS Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-13util/inteltool: Add support for Alder Lake-NBrandon Weeks
Reference: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2 (#759603) Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562 Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-03-13Docs: Update gerrit guidelines for -1 reviewsMartin Roth
The -1 review authority has been moved from all registered users to users in the "reviewers" category. The reviewers group is for people who have submitted patches to coreboot. This change is taking the project back to how it was before 2016, and is not due to any issues that we're seeing. The reason it was initially changed was that in 2016, before we required all comments to be resolved so the patch could be merged, it was easy to overlook comments that should have been addressed. Now that the process has changed, the -1 right is no longer needed for all users simply to bring attention to the comment. The feeling in the leadership meeting was that since it's relatively easy to get to reviewer status, this should not be an undue burden on anyone. Change-Id: I0b7f3dcc80b9122b0f923e6703da73391654d26c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-13soc/intel/xeon_sp: Add device find utilsShuo Liu
For Xeon-SP, it's common pattern to find devices under specific socket, stack and domain. This patch adds util function for these operations. TEST=intel/archercity CRB Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-12mb/amd/birman_plus: Update glinda DXIO descriptors per schematicsAnand Vaikar
glinda FP8 SOC PCIe lanes are updated per the Birman+ schematics document 105-D99700-00C revision 1.0. Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81036 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12payloads/Kconfig: Add flat binary as payload optionMaximilian Brune
This add another choice option for adding a flat binary instead of an ELF or some other payload. It keeps the IS_PAYLOAD_FLAT_BINARY hidden in the menuconfig because it is generally not configurable but dependent on the payload you selected. CONFIG_PAYLOAD_OPTIONS has been exposed to be configurable in commit f0055e4a81 (payloads/Kconfig: Add flat binary as payload option) as part trying to enable flat binary payloads. CONFIG_PAYLOAD_OPTIONS do not need to be configurable though unless you have a flat binary. The patch therefore takes a different appraoch by adding a new payload type besides PAYLOAD_ELF and PAYLOAD_FIT. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-12mb/google/brya/var/xol: Use unified AP FW for UFS/Non-UFS SKUsSeunghwan Kim
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS to use unified AP FW for UFS/Non-UFS SKUs. BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81107 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-12soc/intel/common/block: Add support for watchdogMarek Maslanka
Implement watchdog for intel based platform by filling ACPI Watchdog Action Table (WDAT) table. The WDAT ACPI table encompasses essential watchdog functions, including: - Setting and retrieving countdown/timeout values - Starting and stopping the watchdog - Pinging the watchdog - Retrieving the cause of the last reboot, whether it was triggered by the watchdog or another reason The general purpose register TCO_MESSAGE1 stores the reason for the most recent reboot rather than the original register TCO2_STS. This is because the firmware must clear TCO2_STS, and it can't be reused for storing this information for the operating system. The watchdog is designed for use by the OS through certain defined actions in the WDAT table. It relies on the ACPI Power Management Timer, which may result in an increase in power consumption. BUG=b:314260167 TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy both firmware and kernel to the device. Trigger the watchdog by performing the command: “cat > /dev/watchdog”. Wait approximately 30 seconds for the watchdog to reset the device. Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-12soc/intel/xeon_sp: Rewrite acpi_create_satcShuo Liu
SATC is for RCiEPs (Root Complex Integrated EndPoints) but not limited to IOAT domains. Rewrite the func by iterating all domains and its RCiEPs. Currently the codes only support 1 PCIe segment. TEST=intel/archercity CRB coreboot SATC generation logs are unchanged before and after. Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81049 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12soc/intel/xeon_sp: Create CXL domainsShuo Liu
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain is a PCI domain with single bus number and PCIe RCiEPs (Root Complex Integrated End Points) on it. The 2nd domain is a CXL domain with remaining buses for CXL 1.0/1.1 end points and possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual Function) if any. TEST=intel/archercity CRB P.S. The SUT is not with CXL cards however we hope this refactor could be integrated first as an improvement of the design. Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-11mb/google/brya: Create nova variantDavid Wu
Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-03-11vc/amd/opensil/stub: add stub MPIO driverFelix Held
Add a stub MPIO chip driver to the openSIL stub code, so that the devicetree entries needed for the MPIO chip can already be added to the mainboard's devicetree files. This driver won't do anything, but still allows the register settings in the devicetree to be set to make switching over to the actual openSIL code and the corresponding glue code easier. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-09drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI InitJeremy Compostella
FSP can also make use of Multi-Processor services during its multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot take MP ownership as FSP-S may still use EDK2 MP services concurrently. TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09arch/riscv: Remove typedefsMaximilian Brune
typedefs violate our coding-style Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81124 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-09util/docker/Makefile: Create Documentation/_build for docker-build-docsNicholas Chin
If the host directory of a bind mount does not exist, Docker will create it. However, the newly created directory will be owned by root due to the Docker service running within a root context. The docker command in the recipe for docker-build-docs binds Documentation/_build to /data-out within the container, so if it doesn't already exist, the documentation builder will be unable to copy the HTML output into /data-out since it runs with the same UID and GID as the host user. By creating, if necessary, the _build directory before the `docker run` command, there should always be an existing directory owned by the host user for docker to bind /data-out to (ignoring the case of an existing _build directory the current user does not have permission to write to), avoiding the issue where it cannot write the output. TEST: make -C util/docker docker-build-docs completes without issues with and without an existing Documentation/_build directory Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81127 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-09soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-caseJeremy Compostella
Commit 829e8e65b939 ("soc/intel: Use common codeflow for MP init") brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function static. This function needs to be accessible from src/drivers/intel/fsp2_0/fsp_mpinit.c. TEST=Verified on Meteor Lake rex board Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/xeon_sp: Further share domain creation logics in Xeon-SPShuo Liu
With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81098 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09drivers/spi: Add GD25LR256E supportMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id405ed990101a1ceda5e09c6db835f8302047f5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/81125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09mb/google/brya/var/xol: Disable unused controllersSeunghwan Kim
Disable unused controllers in overridetree.cb by referring to xol proto2 schematics. Enabling unused controllers blocks entering s0ix. - I2C3 - SATA - PCIE RP8 - PCIE RP9 - GSPI1 BUG=b:328318578 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81105 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brya/var/xol: Update psys_pmax value to 122WSeunghwan Kim
Update psys_pmax value to 122 from 145. This value is from internal power team. BUG=None BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81104 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09mb/google/brya/var/xol: Configure Acoustic noise mitigationSeunghwan Kim
Enable Acoustic noise mitigation for xol. The setting values are from internal power team. - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=None TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-09tests: Add `DEBUG` make commandline option to generate debug symbolsJulius Werner
Sometimes when a test doesn't work it's convenient to run it through GDB. This patch adds a variable you can set on the make commandline to conveniently enable all the compiler flags needed to make that work. Change-Id: I3ac80ad095e0b72cc3176cbf915d1f390cd01558 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81112 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-03-09arch/riscv: Add SMP support for exception handlerXiang Wang
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841 Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-09mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine typeFelix Held
Explicitly assign the 'PCIE' value to the 'type' field of the corresponding MPIO chips in the devicetree. Since the mpio_type enum element 'PCIE' has the value 0, this won't change the behavior, but explicitly assigning this makes this easier to understand. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/81095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09soc/intel/alderlake: Remove the guard for CnviWifiCoreSean Rhodes
The CnviWifiCore UPD exists for ADL (version 4263) and RPL (version 4415). Remove the guard so it is set correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brox: Enable Wake on WLAN for SKU1Ashish Kumar Mishra
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL. Update gpio config and corresponding ACPI for WoWLAN. BUG=b:327379404 BRANCH=None TEST=Boot image on SKU1 and check Wake on WLAN from S0ix. Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-09util/smmstoretool: support processing ROMsSergii Dmytruk
Input file is parsed for FMAP and SMMSTORE region which is used if found. Otherwise, the whole file is assumed to be the region. Passing an image with FMAP that lacks SMMSTORER is an error. Change-Id: Ieab555d7bbcfa4dadf6a5070d1297acd737440fb Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09util: add smmstoretool for editing SMMSTORESergii Dmytruk
Offline SMMSTORE variable modification tool. Can be used to pre-configure ROM image or debug EFI state stored in a dump. Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09cpu/x86/smm: Set up page tables in safe SMRAMArthur Heymans
Relying on page tables being in RO flash is not safe in every setup, therefore set up some page tables in SMRAM that the permanent smihandler can use. Tested on QEMU. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80336 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 supportJeremy Compostella
Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-08drivers/intel/fsp2_0: Add "silicon" to the multiphase callback nameJeremy Compostella
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-08vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91Ronak Kanabar
Update header files for FSP for Meteor Lake platform to version 3471_91, previous version being 3471_85. FSPM: 1. Address offset changes BUG=b:327688959 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I5a71232018dfefec63b0a83d1e87717e238a4a0a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80782 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp/spr: Fix IOAT resourcesPatrick Rudolph
Do not generate empty mem32 resources for CPMx or HQMx stacks. Switch existing arguments to make sure that base is bigger than limit to indicate that the resource is invalid. Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80793 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Share numa.c among Xeon-SP platformsShuo Liu
NUMA will be supported by SPR and future generations. TEST=intel/archercity CRB Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-07soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platformsJincheng Li
TEST=intel/archercity CRB Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Add memory type check utilsShuo Liu
FSP memory type representations change across Xeon-SP SoCs. This patch adds type check utils to abstract the differences. TEST=intel/archercity CRB Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>