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2016-09-15soc/apollolake: Set up GPIO_TIER1_SCI_EN properlyShaunak Saha
Currently we are setting the gpio_tier1_sci in smihandler before going to S3. But this won't work for S0iX as it happens from Linux kernel and SMI handler is not involved in that flow. We need to set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux kernel before going to sleep checks what values are passed through ASL as wake events (through _PRW), keeps those enabled only and clears other bits in gpe0 enable registers. So we need to inform the kernel to keep gpio_tier_sci also set as these are needed for any wake event. This patch adds ASL code for sleep button device with HID id PNP0C0E. We are adding _PRW method for sleep button device with this patch. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16564 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15mainboard/bap/ode_e20XX: Change SATA from GEN2 to GEN3Fabian Kunkel
This patch disables the SataSetMaxGen2 flag. This flag is a power saving option, which forces the SATA to GEN2. Payload SeaBIOS 1.9.1, Lubuntu 16.04, Kernel 4.4. $ dmesg | grep ahci #before patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode $ dmesg | grep ahci #after patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode Change-Id: I48361190969e6d38ddb5692f5e54b016b359fbb1 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15906 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15lenovo: add ps2 spinup timeout to all H8S based boardsAlexander Couzens
The h8s needs around 3s to respond to ps2 commands Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16505 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15northbridge/intel/nehalem/gma.c: Improve code formattingElyes HAOUAS
Change-Id: Ie7ee547ab34441f93433936334e9881dd7cc0371 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16599 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15southbridge/sis/sis966/lpc.c: Improve code formattingElyes HAOUAS
Change-Id: I5cd04d49e90502394b4dd84f6a5a727e02f19fdc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16601 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15northbridge/amd/amdk8/raminit_f_dqs.c: Improve code formattingElyes HAOUAS
Change-Id: Ib1f9926ced1fd382c782f5098eb1ad98330cf655 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16600 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15northbridge/amd/amdk8/coherent_ht.c: Improve code formattingElyes HAOUAS
Change-Id: I296254d61fdc5c120e1e2abcbecb4677f3216d26 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16598 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15camelbackmountain_fsp: Select SERIRQ_CONTINUOUS_MODEWerner Zeh
In commit 4f2754c 'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode' the default operation mode of SERIRQ was changed from continuous to quiet. Set the mode to continuous for this mainboard to keep the behavior unchanged. Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15checkpatch.pl: Force raw_line to return a defined valueMartin Roth
Fixes the warning: Use of uninitialized value in concatenation (.) or string at util/lint/checkpatch.pl line 4739 Change-Id: Idc3c631735a595517d77cb8b8ec67e1ac00b6685 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16357 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-09-15lint/checkpatch.pl: Pull in coreboot fixesMartin Roth
This pulls in two fixes that were added to coreboot's checkpatch.pl script: - commit 82ef8ada (src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copy): modify checkpatch.pl to ignore spaces before opening brackets when used in inline assembly. - commit ebef00fa (lint/checkpatch.pl: escape \{ in perl regex to fix warnings): Unescaped left brace in regex is deprecated, passed through in regex; Change-Id: Ia2c712c5b1bb5f67953a9098b5a076e31e3bd8d3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-09-15southbridge/amd/sr5650/sr5650.c: Update acpi_fill_ivrsMartin Roth
- Update lines to make them shorter than 80 chaacters - Update using #defines from acpi_ivrs.h Change-Id: I1bf6cdac00e28f5b0969fd8f98e37c66f8e43110 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16568 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-15arch/acpi_ivrs.h: Update 8-byte IVRS entry valuesMartin Roth
I put in the decimal values for these instead of the hex values. Instead of running them through a BCD converter, update them to use the hex values. Change-Id: I3fa46f055c3db113758f445f947446dd5834c126 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16567 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-15amd/sr5650: Update add_ivrs_device_entriesMartin Roth
Functionally, this should be roughly the same. The only real difference should be removing the 4 bytes of padding from the end of the 4 byte entries. The spec mentions a boundary for the 4 byte entries (which we are ignoring), but doesn't mention a boundary for the 8 byte entries, and I can't think of any other reason that the padding might be needed. - Wrap long lines. - Combine if statements to clean up indentation. - Use #defines from acpi_ivrs.h to make commands easier to understand. - Remove padding from 4 byte entries that made them 8 bytes in length. - Set the pointer p at init, and clear the value at p if the device we're looking at is enabled instead of setting p in every if statement. - Look at the command type to update current and length. - Treat malloc & free as if they were typical instead of coreboot specific versions. Check to make sure the malloc worked and only free on the last loop instead of every time. Change-Id: I79dd5f9e930fad22a09d1af78f33c1d9a88b3bfe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16532 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-15google/reef: Remove setting of GPIO_TIER1_SCI enable bitShaunak Saha
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15intel/amenia: Remove setting of GPIO_TIER1_SCI enable bitShaunak Saha
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-09-15driver/intel/fsp20: move lb_framebuffer functionNaresh G Solanki
move lb_framebuffer function in soc/intel/apollolake to driver/intel/fsp20 so that fsp 2.0 bases soc's can use common lb_framebuffer function. Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-15kunimitsu: Add FSP 2.0 support in romstageRizwan Qureshi
Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values. Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16316 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15soc/intel/skylake: Add FSP 2.0 support in romstageBarnali Sarkar
Populate SoC related Memory initialization params. Post memory init, set DISB, setup stack and MTRRs using the postcar funtions provided in postcar_loader.c. TEST=Build and boot kunimitsu, dram initialization done. ramstage is loaded. Change-Id: I8d943e29b6e118986189166d92c7891ab6642193 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15driver/intel/fsp2_0: Make FSP-M binary XIPRizwan Qureshi
If FSP_M_XIP is selected, then relocate FSP-M binary while adding it in CBFS so that it can be executed in place. Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15cbmem: Exit with an errorlevel of 0 after printing helpMartin Roth
cbmem --help should not return an error to the OS. Change-Id: Id00091c679dbb109bc352cf8a81d67c2ae5666ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16574 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-14drivers/i2c/tpm: Clean up handling of command readyDuncan Laurie
The TPM driver was largely ignoring the meaning of the command ready bit in the status register, instead just arbitrarily sending it at the end of every receive transaction. Instead of doing this have the command ready bit be set at the start of a transaction, and only clear it at the end of a transaction if it is still set, in case of failure. Also the cr50 function to wait for status and burst count was not waiting the full 2s that the existing driver does so that value is increased. Also, during the probe routine a delay is inserted after each status register read to ensure the TPM has time to actually start up. Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-14lpss_i2c: Add Kconfig option to enable debugDuncan Laurie
It is very useful to have the ability to see I2C transactions performed by the host firmware. This patch adds a simple Kconfig option that will enable debug output. Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16590 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-14lpss_i2c: Change handling of controller enable/disableDuncan Laurie
This change modifies the lpss_i2c driver to behave more like the Linux kernel driver. In particular the controller is only enabled when processing a transaction, and is disabled after. This means that errors in one transaction will not affect later transactions. Also when disabling the controller the code is supposed to wait on the enable bit in the "enable status" register and not in the enable control register. In order to get access to this register the reg map was expanded to include all registers. This was tested with the cr50 TPM driver to ensure that if a transaction does fail that it can be successfully retried instead of the bus being unusable. Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-14mainboard/intel/amenia: Configure PERST_0 pinVaibhav Shankar
Configure PERST_0 and assign the pin in devicetree. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16350 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboards/apollolake: Set RAPL power limit PL1 value to 12W.Sumeet Pawnikar
This patch sets tuned RAPL power limit PL1 value to 12W in acpi/dptf.asl for RAPL MSR register. With PL1 as 12W for WebGL and stream case, we measured SoC power reaching upto 6W. Above 12W PL1 value, we observed that Soc power going above 6W. With PL1 as 12W, system is able to leverage full TDP capacity. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14soc/intel/apollolake: Update PL1 value in RAPL MMIO registerSumeet Pawnikar
Due to an incorrect value set for the power limit PL1, the system is not able to leverage full TDP capacity. FSP code sets the PL1 value as 6W in RAPL MMIO register based on fused soc tdp value. This RAPL MMIO register is a physically separate instance from RAPL MSR register. This patch sets PL1 value to 15W in RAPL MMIO register. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboard/google/reef: Configure PERST_0 pinVaibhav Shankar
This configures PERST_0 in devicetree. For boards without PERST_0, the pin should be disabled. For boards with PERST_0 the correct GPIO needs to be assigned. BUG=chrome-os-partner:55877 Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-14soc/intel/apollolake: Add PM methods to power gate PCIeVaibhav Shankar
This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14soc/intel/apollolake: initialize GNVS structure to 0Aaron Durbin
The code was not previously initializing the GNVS structure to all 0's in the ACPI write tables path. Fix this and also rearrange the ordering of updating the fields to only handle the chip_info specific bits till last such that most of the structure is filled in prior to bailing out in the case of a bad devicetree. Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16597 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14SeaBIOS: Update stable version to 1.9.3Martin Roth
The SeaBIOS Stable version 1.9.3 was released back in July. This has just 4 fixes over 1.9.1: fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL fw/pci: Add support for mapping Intel IGD via QEMU fw/pci: add Q35 S3 support build: fix .text section address alignment Change-Id: I527df85b5199942706d1188285c6678bf2f726a1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16254 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Omar Pakker Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-13mainboard/google/reef: add MKBP EC event as SCI event.Gwendal Grignou
Add MKBP as a SCI event: the EC is then able to send events coming from the sensors. BUG=b:27849483 TEST=With EC configure to send MKBP events, check sensor information are retrieved by the kernel. Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/16594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13i945.h: fix #include pathAntonello Dettori
Fix the #include path. Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13cpu/amd/family_10h-family_15h: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside cpu/amd/family_10h-family_15h. Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16436 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13lenovo/t60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/t60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16405 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/agesa/hudson: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/agesa/hudson. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16401 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/nehalem: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/nehalem. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16406 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/intel/ibexpeak: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/ibexpeak. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ic569aada9301b37e73196872584e191d553acd86 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16408 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/intel/i82801gx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801gx. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16370 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/intel/i82801ix: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801ix. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ibf20e6c08994b09d2a2e68a1a1d38a7a477493aa Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16403 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/gm45: transation away from device_tFurquan Shaikh
Replace the use of the old device_t definition inside northbridge/intel/gm45. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16402 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/via/vt8237r: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/via/vt8237r. Change-Id: I9c1211e698ef35f56dd71c2c021dea680091c1ee Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16489 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/sis/sis966: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/sis/sis966. Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/nvidia/mcp55: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/nvidia/mcp55. Change-Id: I98ac468940eaf6c456fa95540ec3e718edfe26a7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/nvidia/ck804: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/nvidia/ck801. Change-Id: I43d4d2175f0b6b9e7e2e6fe665ba3d99d792427c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16486 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/sb800: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/sb800. Change-Id: I488cde4504128331106f50b34869905e30f5ab83 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16480 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/sb700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/sb700. Change-Id: I44b0be2070719066dd18bbf2882c417caef5d8b2 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/sb600: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/sb600. Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16478 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/rs780: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/rs780. Change-Id: Ia9929baeec7423e9e2f06324038ddfbec006beb7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16477 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/rs690: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/rs690. Change-Id: Ief43393f62312bfe82e960faf56b1e2ec048f4ff Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16476 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/pi/hudson: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/pi/hudson. Change-Id: I8b22a8d9f0e90afaf0f218c5c0924a78883b7498 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16475 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/cimx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/cimx. Change-Id: Ibe2766b956b0ca02be63621aee9a230b16d9923b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13southbridge/amd/amd8111: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/amd8111. Change-Id: I76cdc32171b7ce819b53c534b3a5e57e9dd5f3dd Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16473 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdht: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdht. Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16468 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdk8: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdk8. Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16467 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdfam10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdfam10. Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16466 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/bcom/winnetp680: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/bcom/winnetp680. Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/gigabyte/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/gigabyte/*. Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/asus/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/asus/*. Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add DDR driverHakim Giydan
This driver is only a prototype driver, real driver will be integrated at a later time. Testing: booted successfully. Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16554 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add MCU driverHakim Giydan
Testing: booted successfully. Change-Id: I003f6929b00476d46be931773cd35418fe6622a6 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15529 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add WDT driverHakim Giydan
Testing: booted successfully. Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15519 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add NVM driverHakim Giydan
This driver uses BootROM callback to read and write to the nvm using I2C. Testing: booted successfully. Change-Id: I8639af3e004f6631d7e596507c106159835f979f Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add A2BUS driverHakim Giydan
A2BUS is a custom fabric. Testing: booted successfully. Change-Id: If6e61f5aa30217eb601ac460d9306166b8433569 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15523 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add PMIC driverHakim Giydan
Testing: booted successfully. Change-Id: I168206585f403d2259efe424e563982be661df0b Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16149 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add APMU driverHakim Giydan
APMU is the AP power management unit. It is a separate processor that handles enabling individual power rails. This driver handles sending and receiving commands from/to APMU. Testing: booted successfully. Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15518 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add load_validate driverHakim Giydan
Load_validate: it loads and validates images from flash using hash values stored in the BDB. Testing: booted successfully. Change-Id: I0b00e8c60ed76622d03cb232d5c4273b4077aae7 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16148 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add flash driverHakim Giydan
Testing: booted successfully. Change-Id: Iaeff9f01dbfad7f313aa237e8c71c36c4ed1e06f Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15509 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add gpio driverHakim Giydan
Testing: booted successfully. Change-Id: I89dee1bbf8b68460897f64bf673b328533e70cd4 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15508 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13google/rotor: Add support for the Rotor mainboardHakim Giydan
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell: Add stub implementation of MVMAP2315 SOCHakim Giydan
Most things still need to be filled in, but this will allow us to build boards which use this SOC. Nvidia Tegra210 SOC and Rochchip Rk3399 SOC has been used as templates to create this directory. Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15506 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13fsp_broadwell_de: Add Kconfig switch for SERIRQ operation modeWerner Zeh
The serial IRQ (SERIRQ) used by the LPC interface can operate either in continuous or in quiet mode. Add a Kconfig switch to select the desired mode. This switch can now be used on mainboard level to enable the needed mode per mainboard. Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPCWerner Zeh
Since this mainboard provides 4 COM ports on LPC, enable decoding of the corresponding addresses using the generic LPC decode registers. Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12src/arch: Improve code formattingElyes HAOUAS
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16434 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-09-12Makefile.inc: build ifdtool using its own makefileAlexander Couzens
Change-Id: I67c73c101b928d104e231064e05d367bf9584730 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16571 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12ifdtool/Makefile: use static dependenciesAlexander Couzens
The generated dependencies doesn't work when used together with our main build system. Change-Id: I93d26858e961d7e275d586a1b8a26b3d33f3bd41 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12ifdtool: fix one whitespace format errorAlexander Couzens
Change-Id: I5b1846eb3ef8253695066b315e8a105803390579 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16570 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12lenovo/t60: add hda_verb.cArthur Heymans
This creates a config for the Lenovo T60 sound card based on values taken from vendor bios (in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). The sound card configuration on the vendor bios is the same as the one on the Lenovo x60. It improves the default behavior of the sound card: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16529 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
This change adds armv7-r support for all stages. armv7-r is an ARM processor based on the Cortex-R series. Currently, there is support for armv7-a and armv7-m and armv7-a files has been modfied to accommodate armv7-r by adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants to src/include/rules.h. armv7-r exceptions support will added in a later time. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15335 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12kunimitsu: Add initial FSP2.0 supportRizwan Qureshi
Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact. Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12vendorcode/skylake: Add FSP header files without any adaptationsRizwan Qureshi
Add header files as is from FSP build output. Move the FSP header files to new location as in apollolake. Update all the FSP structure references now that they are typedef'd. Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16517 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12driver/fsp2_0: Include stdint header file in api.hNaresh G Solanki
'bool' type is reported undefined due to missing stdint.h inclusion, Fix it by including the same. Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrrRizwan Qureshi
In the current implementation of postcar_frame_add_mtrr, if provided size is bigger than the base address alignment, the alignment is considered as size and covered by the MTRRs ignoring the specified size. In this case the callee has to make sure that the provided size should be smaller or equal to the base address alignment boundary. To simplify this, utilize additonal MTRRs to cover the entire size specified. We reuse the code from cpu/x86/mtrr/mtrr.c. Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16509 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12cpu/x86: Move fls() and fms() to mtrr.hRizwan Qureshi
Move the funtion to find most significant bit set(fms) and function to find least significant bit set(fls) to a common place. And remove the duplicates. Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12arch/x86: Always compile postcar library in romstageRizwan Qureshi
postcar_loader.c has a useful library of funtions for setting up stack and MTRRs. Make it available in romstage irrespective of CONFIG_POSTCAR_STAGE for use in stack setup after Dram init. The final step of moving the used and max MTRRs on to stack is moved to a new function, that can be used outside of postcar phase. Change-Id: I322b12577d74268d03fe42a9744648763693cddd Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Enable lpss s0ixVenkateswarlu Vinjamuri
This setting enables lpss to power gate in S0ix. BUG=chrome-os-partner:53876 Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Disable CLKREQ of unused PCIe root portsVenkateswarlu Vinjamuri
1. Removes PCIe blocker for S0ix. 2. Set the correct PCIe root port for wifi/bt on EVT. 3. Turn off CLKREQs of unused PCIe root ports to power gate the IP. Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12fsp_broadwell_de: Correct access to SIRQ_CNTL registerWerner Zeh
The serial IRQ configuration register is only 8 bit wide so switch the PCI access from 16 bits to 8 bits. Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16534 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-11buildgcc: Quote command substitutionIdwer Vollering
There are shells where the result of a command substitution is subject to word splitting (e.g. dash when assigning a value inside an export statement). Change-Id: I70a5bc124af7ee621da2bdb4777f3eaba8adafbb Signed-off-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/15820 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-09-10southbridge/intel/i82801dx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801dx. Change-Id: Ic08a23f672f8b5e40b837d49a9475d52c728a306 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16485 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/i82801ax: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801ax. Change-Id: I46f0cc92e1034f045988b42df7246f5d0c8d24fc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/i82371eb: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82371eb. Change-Id: Ie15a656c817a2ffe0f44ee3a89659d138a1bf212 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16483 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/i3100: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i3100. Change-Id: Ic9616d5135cfb7206e086e51aaf82eb66540c4bb Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16482 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10southbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/fsp_rangeley. Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/x4x: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/x4x. Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16472 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/i5000: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i5000. Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/e7505: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/e7505. Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16469 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09soc/intel/apollolake: Add functions to calculate GPIO addressVaibhav Shankar
Provide iosf and GPIO functions for GPIO address calculation. BUG=chrome-os-partner:55877 Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16349 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-09util/release: Add support for signed tags and releasesPhilipp Deppenwiese
* Add gpg key command-line parameter for signing. * Add username command-line parameter for secure ssh clone. * Tag and releases are signed. * Generates ascii amored signature files. Change-Id: I41347a85145dd0389e3b69939497fb8543db4996 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/16553 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridgeDamien Zammit
Although the goal was to hide the ME device by disabling the PCI bridge, the original comment that this bridge was ME related was a mistake, this bridge is for PEG not for ME. We still need this PCI bridge "on" to enable pci express graphics add-on cards. Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16496 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 01:38:16 +0000